JPH0218624B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel synchronization circuit on the receiving side in a time division multiplex transmission system for multi-channel signals using multilevel class partial response encoding.

Multi-channel signals are time-division multiplexed and transmitted.
In order to separate this at the receiving section, it is generally necessary to send a signal for channel synchronization from the transmitting section. However, when class partial response coding is applied to multi-channel signals, the transmitter transmits a violation that disturbs the encoding rule under certain conditions, and the receiver Using the detected violation as a phase reference signal,
This allows efficient data transmission without allocating time for sending channel synchronization signals. This is the case in the patent application No. 57-26823.
It is detailed in the specification of the issue, so please refer to it. The conditions for giving the above violation are that the code of a specific channel is given at a time position (time slot) in order to provide a phase reference for channel synchronization, and that a characteristic To get a violation,
It is necessary that the code sequence precoated in the transmitting section be given when a specific combination of codes is given. However, for this reason, the channel synchronization signal depends on the pattern of the code sequence to be transmitted, and the degree of occurrence is stochastic and has no temporal regularity, and if the signal is interfered with on the transmission path. The drawback was that synchronization was disrupted.

An object of the present invention is to perform phase control only when two consecutive violations according to a specific pattern are detected in N received symbols.
An object of the present invention is to provide a channel synchronization circuit capable of achieving stable channel synchronization even when a channel synchronization signal is generated irregularly in time and is disturbed on a transmission path.

According to the present invention, class partial response encoding is performed, and with a specific code pattern of a code sequence,
The channel synchronization circuit is applied to a receiving multi-channel separation device in a time division multiplex transmission system in which a violation is given to a time slot of a specific channel for transmission, and the circuit counts N baud rate clocks synchronized with received symbols. a first count output circuit that outputs a pulse every time a violation occurs; and means that generates a pattern detection pulse when the specific code pattern is detected on the received code sequence and two consecutive violations are detected at the same time. a frequency dividing circuit that divides the frequency of the clock signal supplied through the first AND circuit in synchronization with the received code; and a first frequency dividing circuit that performs the logical product of the frequency-divided signal and the output pulse of the pattern detection pulse generating means. a second count output circuit that is reset by the output pulse of the first count output circuit and outputs a pulse every time K output pulses of the pattern detection pulse generation means are counted; , a third count output circuit which is also reset by the output pulse of the first count output circuit and outputs a pulse every time K output signals of the second AND circuit are counted; a first flip-flop that is set by the output signal of the count output circuit and reset by the output pulse of the first count output circuit; and an OR circuit having one input as the output of the third count output circuit. a second flip-flop which is set by the output signal of the count output circuit and reset by the output pulse of the first count output circuit; and a multi-input circuit whose inputs are the outputs of the first and second flip-flops. a NAND circuit, a third flip-flop that latches the output signal of the NAND circuit with the clock signal and generates a pulse, outputs of the first and second flip-flops, and an inverted output of the clock signal;
and a third AND circuit that takes the inverted output of the baud rate clock as an input and supplies the output to the other input of the OR circuit, and a third AND circuit that inputs the output signal of the third flip-flop to one of the inputs of the multi-input NAND circuit. and means for applying the output signal as a phase control pulse to the first AND circuit, and controlling the clock signal passing through the first AND circuit with the phase control pulse to control the clock signal passing through the first AND circuit. A channel synchronization circuit is obtained which is characterized in that it performs phase control of the output signal.

Next, a channel synchronization circuit according to the present invention will be explained in detail with reference to the drawings.

FIGS. 1 and 2 respectively show a block diagram and a time chart of a receiving section as an embodiment of the present invention. In FIG. 1, a received signal a supplied via a transmission path is transmitted to a demodulation circuit 1.
The signal is demodulated by the automatic equalizer 2, equalized, and digitized at the same time to produce a parallel signal (signal b in Fig. 2, (However, the polarity bit is omitted.) Further, the presence or absence of the received signal a is determined by the signal detection circuit 3, and the result is output as a determination signal g. The above parallel signal b is simultaneously applied to the violation detection circuit 4, the parallel-to-serial code conversion circuit 6, and the channel synchronization circuit 9 according to the class partial response encoding rule. Of these, the violation detection circuit 4 compares the signal b with the encoding rule to detect a violation of the encoding rule, that is, a violation. moreover,
If a violation is intentionally added to indicate a phase reference for channel synchronization in the transmitter, it is detected as two consecutive violations, and the information is output as a signal e. In addition,
When two consecutive violations are detected, the signal c is not considered as a code error in the received signal, but when a single violation is detected, the signal c is output as code error information. This signal c is applied to the error rate detection circuit 5 to detect the error rate, and is sent to the channel synchronization circuit 9 as an output d. The parallel-serial code conversion circuit 6 converts the parallel code sequence b shown in FIG. 2 into a serial code sequence f based on the signal h given from the channel synchronization circuit 9. If this signal f is scrambled in the transmitter, it is decoded in the descrambler circuit 7 and then sent to the serial-parallel code conversion circuit 8 as shown in FIG.
It is converted into each code of j, k and l. The channel synchronization circuit 9 is a circuit according to the present invention, in which the demodulation circuit 1 is time-division multiplexed, and the violation is performed only in the time slot where the code of a specific channel exists in the multilevel class partial response encoded signal. When receiving a signal given by , restoring it to an output signal b, and performing further channel separation, the channel synchronization circuit 9 generates timing signals h and i for code conversion.

FIG. 3 shows the channel synchronization circuit 9 in FIG.
This is a block diagram showing an example of the configuration.
In this figure, 10, 11, 12, 13 are
AND circuit (AND circuit), 14 is OR circuit (OR circuit), 15 is NAND circuit (NAND circuit), 16,
17 is an inverter circuit, 18 is a frequency divider circuit, 19 is an N-stage counter (first count output circuit), 20
20a is a pattern detection circuit, 20a is a pattern detection pulse generator, 21 and 21 are K-stage counters (second and third count output circuits), and 23, 24, and 25 are flip-flop circuits. Further, m is a clock signal synchronized with signal b in FIG. 2, and n is a baud clock signal obtained by dividing the signal m by 1/2. The operation of the channel synchronization circuit configured as described above will be explained below with reference to the time chart of FIG. 4.

In FIG. 3, the N-stage counter 19 receives a pulse signal o every time it counts N baud clock signals n.
, and sends a reset signal to the K-stage counters 21 and 22 and flip-flop circuits 23 and 24, respectively. The pattern detection circuit 20 generates a pulse when a predetermined pattern is detected from the code sequence of the signal b. At the time of this pattern detection, the violation detection circuit 4 simultaneously
A continuous violation detection signal e is supplied,
As shown in FIG. 2, a signal u, which is a pattern detection pulse, is obtained at the output side of the AND circuit 11. That is, the pattern detection circuit 20 and the AND circuit 11
This constitutes a pattern detection pulse generator 20a. The frequency dividing circuit 18 divides the frequency of the clock signal m passing through the AND circuit 10 to generate signals h, i, and v. The K-stage counter 21 counts the number of pulses of the applied pulse signal u, and generates a pulse p every time K pulses are counted. On the other hand, K
The stage counter 22 has a second phase relationship between the signals u and v.
Only when the relationship shown in the figure exists and a pulse of signal u is generated, the pulse is received via the AND circuit 12, and every time K pulses are counted, a pulse of q in Figure 4 is generated. . Flip-flop circuit 23 is set with signal p and reset with signal o to generate signal r. The flip-flop circuit 24 is set by the signal q or the output signal of the AND circuit 13, and reset by the signal to generate the signal s. Flip-flop circuit 2
Reference numeral 5 denotes a circuit that sets the output state of the NAND circuit 15 at the rising edge of the clock signal m, thereby outputting a signal t, which is a phase control pulse. The states of the signals g and d applied to the AND circuit 15 are as follows under normal transmission conditions, that is, when there is no disconnection in the transmission path, the signal a is correctly received, and the error rate also satisfies the specified conditions. is logically set to a high level.

Here, a case where the channel synchronization circuit 9 is correctly synchronized and a case where the channel synchronization circuit 9 is out of synchronization will be explained. First, when channel synchronization is achieved, the phase relationship between signals u and v is as shown by the solid line in FIG. Therefore, the operating state of each circuit in the channel synchronization circuit 9 is as shown by the solid line in FIG. Considering the frequency of occurrence of pulses in signal u, which is a problem here, the pulse generation conditions are such that a specific pattern is detected in the code sequence transmitted by the transmitter, and the violet is generated only in the code assignment time slot of a specific channel. It can be seen that this is the case only when a specific pattern is detected in the received code sequence by the receiver, and two violations are detected in succession. Therefore, the manner in which the pulses are generated is stochastic, and the long-time signal u
There is a state where the pulse does not occur. In order to prevent erroneous phase control from being performed in such a case, phase control is performed by detecting two consecutive violations of a specific pattern among the N received symbols. That is, when the pulse of the signal u cannot be obtained, the counter circuit 21 does not generate the pulse signal p on its output side, so the flip-flop circuit 23 is not set. Therefore, the signal t remains at a high level and does not give any phase change to each output signal of the frequency dividing circuit 18.

When the channel is out of synchronization, the phase relationship between the signals u and v will be as shown by the solid line and the broken line in FIG. No pulse appears. Therefore, the K-stage counter 22 which receives this output as an input does not count up, and its output q maintains a low level state as shown by the broken line in FIG. At this time, each input signal of the third AND circuit 13 is shown by the inversion of the signals m and n in FIG. 2 and the logical conditions of the signals r and s in FIG. 4, and the output of the AND circuit 13 is The low level state is maintained until all of the input signals become high level. Therefore, since the second flip-flop 24 is not set, the output signal s remains at a high level.

As a result, all five inputs of the NAND circuit 15 in FIG. 3 become high level, and its output becomes low level. Therefore, as shown in FIG. 4, the phase control pulse t, which is the output of the third flip-flop 25, changes from the high level to the low level (broken line) at the rise of the signal m. Therefore, the first
The AND circuit 10 prohibits the passage of the signal m and temporarily stops the operation of the frequency divider circuit 18.

The third AND circuit 13, which receives the inverted signals m and n and the signals s and r, has remained at low level until now, but when the signals m and n become low level, the high level output is sent to the OR circuit 14. to the second flip-flop 24 to set it. Therefore, its output s is high level (dashed line)
to low level (solid line), changing the output of the NAND circuit 15 to high level. As a result, the third
The phase control pulse t, which is the output of the flip-flop 25, returns from the low level to the high level at the next rise of the signal m, and returns the frequency divider circuit 18 from the previously paused state via the first AND circuit 10. Set to frequency dividing operation state.

As can be easily read from FIG. 4, the pause time in the above operation corresponds to one period of the signal m. That is, the phases of the output signals h, i, and v of the frequency dividing circuit 18 are delayed by one period of the clock signal m. Note that the AND circuit 13 is used to set the inhibition time of the clock signal m by the signal t to one period of the clock signal m per NT seconds. However, the time T is the time of one cycle of the baud clock. The above-described state of out-of-synchronization continues until the pulse generation position of the signal v reaches the position indicated by the solid line in FIG. 2, after which channel synchronization is established.

In the above embodiment, only the operation under normal transmission conditions was explained, but as a synchronization protection method in the event of a disturbance in the transmission path or a line disconnection, the signal g
If the error rate of the received code exceeds the specified value due to disturbance occurrence, the signal d is set to a low level and the signal t is set to a high level unconditionally. , it is possible to prevent incorrect phase control from being performed.

As is clear from the above explanation, according to the present invention, by performing phase control only when two consecutive violations of a specific pattern are detected among N received symbols, temporal This method has great effects in that it is possible to stably establish channel synchronization even with channel synchronization signals that are irregularly received, and system reliability can be maintained even when signal interference occurs on the transmission path.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a receiving section as an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment in FIG.
FIG. 3 is a block diagram showing an example of the structure of the channel synchronization circuit in FIG. 1, and FIG. 4 is a time chart for explaining the operation of the channel synchronization circuit in FIG. In the figure, 1 is a demodulation circuit, 2 is an automatic equalizer,
3 is a signal detection circuit, 4 is a violation detection circuit, 5 is an error rate detection circuit, 6 is a parallel-serial code conversion circuit, 7 is a descramble circuit, 8 is a serial-
Parallel code conversion circuit, 9 is a channel synchronization circuit, 10
~13 is AND circuit, 14 is OR circuit, 15 is
NAND circuit, 16 and 17 are inverter circuits, 1
8 is a frequency dividing circuit, 19 is an N-stage counter (first count output circuit), 20 is a pattern detection circuit, 20
a is a pattern detection pulse generator, 21, 21 are K
Stage counter (second and third count output circuits),
23 to 25 are flip-flop circuits.

Claims (1)

[Claims] 1 Channel synchronization applied to a receiving multi-channel separation device in a time division multiplex transmission system that performs class partial response encoding and transmits with a specific code pattern of the code sequence and with violation of the time slot of a specific channel. A first circuit that outputs a pulse every time N baud rate clocks synchronized with the received symbol are counted.
a count output circuit; means for generating a pattern detection pulse when the specific code pattern is detected on the received code sequence and two consecutive violations are detected at the same time; a frequency dividing circuit that divides the frequency of a clock signal supplied through the AND circuit; a second AND circuit that performs a logical product of the frequency-divided signal and the output pulse of the pattern detection pulse generating means; a second count output circuit that is reset by the output pulse of the count output circuit and outputs a pulse every time K output pulses of the pattern detection pulse generation means are counted; a third count output circuit that is reset by the output pulse and outputs a pulse every time K output signals of the second AND circuit are counted; and a third count output circuit that is reset by the output signal of the second count output circuit. a first flip-flop which is reset by the output pulse of the first count output circuit, and an output signal of an OR circuit whose one input is the output of the third count output circuit; a second flip-flop reset by the output pulse of the first count output circuit; a multi-input NAND circuit whose inputs are the outputs of the first and second flip-flops; and an output of the NAND circuit. a third flip-flop that latches a signal with the clock signal and generates a pulse; outputs of the first and second flip-flops;
A third AND circuit receives the inverted output of the clock signal and the inverted output of the baud rate clock and supplies the output to the other input of the OR circuit, and the output signal of the third flip-flop is connected to the multiplex AND circuit. and means for supplying the output signal as a part of the input to the input NAND circuit and supplying the output signal as a phase control pulse to the first AND circuit,
Channel synchronization applied to a multi-channel separation device for reception, characterized in that the phase control pulse controls a clock signal passing through the first AND circuit to control the phase of the output signal of the frequency dividing circuit. circuit.