JPS60189319A - Semiconductor logical integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a malfunction by setting a state for inverting and sending out an output signal from a logical circuit part, and a state for fixing an output level to a prescribed level, by a control signal, so that all output buffers do not generate the same level variation at the same time. CONSTITUTION:Output buffers B11-Bmn using an NOR gate are provided so as to correspond to each output signal S1-Sn of a logical circuit part LG. Its buffers are divided into plural groups of B11-B1n, B21-B2n...Bm1-Bmn, each of the signals S1-Sn is applied to one input, and the other input is connected in common to each group, and also connected through buffers B1-Bm to control terminals C1-Cm provided on each group. Accordingly, the buffers B11- Bmn become on when a control signal applied to the control terminals C1-Cm is ''L'', and become off when said signal is ''H''. Also, in case of an on-state, the signals S1-Sn are sent out repeatedly, but in case of an off-state, the output level is fixed to ''L'', and the power source current is not varied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in semiconductor logic integrated circuit devices.

[Prior art]

FIG. 1 is a block diagram of a conventional semiconductor logic integrated circuit device (hereinafter referred to as an integrated circuit).
The external input signal applied to input buffer IB
,~IBn, the logic circuit section is given to G, and this\
Logic processing is performed in , and output signals 81 to S
n, and is sent to the outside from output terminals 01-On via output buffers OUTt-OBn.

Note that power lines and power terminals for supplying power to each part are provided commonly to all devices.

In this case, when testing integrated circuits, test equipment (
After being attached to a tester (hereinafter referred to as a tester), test signals are applied from the tester to input terminals 1 to In, and the corresponding output signals from output terminals 01 to On are checked to determine whether the integrated circuit is good or bad.

However, these power supply current changes in response to output level changes of the output buffers OB, ~OBn are small compared to other parts, and when there are a large number of output buffer sofas OB, ~OBn, these power supply currents change at the same time. Since the output level is set to a high logic level (hereinafter referred to as %HJF) or a low logic level (hereinafter referred to as %L〃), the power supply current changes greatly accordingly, and is used when installing an integrated circuit into a tester. Distributed inductance in jigs such as sockets and performance ports, and in the wiring inside the tester induces fluctuations in the power supply voltage in response to transient changes in the power supply current.

On the other hand, since the input signals applied to input terminals ■1 to ■1 are based on the common potential of the tester, fluctuations in the power supply voltage are mixed in as noise), reducing the input operating margin of the integrated circuit. In some cases, this may result in defects indicating malfunction of the device.

Note that as a countermeasure for this, output buffers OB1 to oBn
However, the input signal for testing is determined according to the logic processing conditions of the integrated circuit, so it is necessary to realize the setting conditions described above. This creates the drawback that it is extremely difficult to do so.

[Summary of the invention]

The purpose of the present invention is to fundamentally solve the drawbacks of the conventional art, by dividing the output buffer into multiple groups, giving a control signal to each group, and inverting the output signal from the logic circuit section before sending it out. An extremely effective semiconductor logic integrated circuit in which a state in which the output level is fixed at a predetermined level and a state in which the output level is fixed at a predetermined level are set by a control signal, and all output buffers do not cause the same level change at the same time. It provides equipment.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to FIG. 2 showing an embodiment.

FIG. 2 is a block diagram, and FIG. 3 is a timing chart showing the waveforms of each part in FIG. 2. In FIG.
Output buffers 811 to B1111m using R gates are provided, and these are 1111 to BrnXBzl to
Bsn, -BIBI ~ BmIn, divided into multiple groups,
Output signals S, ~S, are given to one input, respectively, and the other input is commonly connected to each group, and control terminals cl to Cm provided for each group are connected to the buffer B.
1 to B-.

Therefore, the output buffers Bll to I1mn are turned on when the control signal applied to the control terminals C1 to C1 is 1Ll, are turned off when the control signal is %HI, and in the on state, output signals 81 to sn are inverted and sent out. On the other hand, in the off state, the output level is fixed to %Ll, and the power supply current does not change.

Therefore, as shown in Figure 3, the test signal (a) is input to the input terminal! 1 to ■3, and within the change period of these, %(, I and If the control signals (b) to (d) are repeatedly generated in the relationship shown in FIG. Since the signals 81 to Sn are inverted and sent out, and the output levels of the other signals are fixed to -L, the system strobe is applied at the timing when the sending signals (,) to (g) overlap. If a pulse (h) is generated and the tester receives the output signals (,) to (- in response to this pulse, the test can be carried out in the same way as before, and it does not cause a large change in the power supply current. becomes.

However, other equivalent gates or inverters having enable terminals may be used as the output buffers nst to I1mn, and buffers B and to Bm may be replaced with inverters or omitted depending on the conditions. Similarly, the input buffers IB1 to IBn can also be omitted depending on the situation, and various modifications are possible.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, all output buffers 7 do not change their output levels at the same time, and fluctuations in the source voltage are suppressed by reducing changes in the power supply current. Since the occurrence of malfunctions in integrated circuits based on this method is prevented, a remarkable effect can be obtained particularly in testing large-scale integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing chart showing waveforms of various parts in FIG. LG... Reference logic circuit section, 5l-8n11... Output signal, Bll-I1mn... Output buffer, c1-C
Engineering: Control terminal. Agent Masuo Oiwa Figure 1 Envy Figure 3 Procedure Supplement iEi replacement (voluntary) 1. Display of the incident! Destroy III,'! 59-4620
No. 9 No. 2, Title of the invention: Semiconductor logic integrated circuit device 3, Relationship with the amended person case Patent applicant address: Tokyo Kogyo; (1712 Marunouchi 2, 111-ku, Chiyo, Tokyo)
:3 Name (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Column 6 for detailed explanation of the invention in the agent's memorandum, Contents of the amendment 7.11. ” to “input signal terminal I,
The net input voltage applied to ~In is assumed to change by the amount of variation in the power supply voltage. (2) "All output buffers do not cause the same level change at the same time" on page 4, line 13 of the same book is corrected to "all output buffers do not cause the output level change to occur at the same time." (3) "On" in lines 12 and 14 of page 5 of the same book
is corrected as "active", and each "off" is corrected as "inactive". that's all

Claims (3)

[Claims] (1) A logic circuit section that has a logic processing function and sends out a plurality of output signals, and a control signal that is provided corresponding to each of the output signals, is divided into a plurality of groups, and is given to each group. The control signal provided for each group is applied to a plurality of output buffers, which are set to either a state in which the output signal is inverted and sent out, or a state in which the sending level is fixed at a predetermined level. A semiconductor logic integrated circuit device comprising a plurality of control terminals. (2) A state in which the output signal is inverted and sent out according to the level of the control signal, and a state in which the sending level is fixed at a predetermined level, comprising at least an input to which an output signal is given and an input to which a control signal is given. 2. The semiconductor logic integrated circuit device according to claim 1, wherein a circuit set in any one of the following is used as an output buffer. (3) A semiconductor logic integrated circuit device according to claim 1 or 2, characterized in that a two-manpower NOR gate is used as an output buffer.