DE4040382C2 - Integrated semiconductor circuit arrangement with low power consumption and method for its operation - Google Patents

Description

The invention relates to semiconductor integrated circuit devices Arrangements with functional circuit blocks as for example play a memory, an arithmetic logic unit or an I / O controller) for which a low power is sought, for example as a built-in cache memory, for access and multi-bit output with high Speed required, appropriate micropro cessors and methods for operating such circuits with low power consumption (power consumption).

It is common in state of the art microprocessors nik to expand parallel operation and improve cachability build to solve problems caused by the inequality of the Speed of execution of an internal command and the speed of transmission of one command and one Operands caused by an external main memory will. For these reasons, the increase in performance recording has become a serious problem.

A primary purpose for installing a cache is Commands or data ready at high speed to deliver that with the execution speed of the Microprocessor matches.

The clock frequency of a microprocessor of the type complex Instruction Set Computer (CISC) with the currently highest  Speed is 25-40 MHz. It is expected that in the near future reduced-type microprocessors Instruction Set Computer (RISC) with a clock frequency of over 100 MHz can be developed.

In such a high speed microprocessor an ultra high access speed of less than a few nanoseconds for the built-in cache such.

A distinctive feature of a built-in cache is a relatively small number of words and an extremely high one Number of read bits per word (maximum 8 bits in SRAMs for general applications). For example, it is at present 32-bit microprocessors commonly used that several hundred bits can be read out in parallel increase the number of bits to be read in parallel will be introduced in the future when 64-bit microprocessors will.

In general, highly sensitive sense amplifiers are from Differential amplifier type that use bipolar transistors for ultra-high speed read signal amplifiers storage. These circuits each consume but always a lot of electricity. Beyond that too consumed power from other parts of the memory, even then when the memory is not accessed, it is because, special energy saving measures are planned.

Therefore, one-chip microprocessors with ultra high Access speed and multi-bit parallel output Cache the power consumption by the storage circuit extremely high, so on-chip cache ultimately cannot be realized unless suitable electricity savings facilities are provided.  

In a first method according to the prior art, be Knows as electricity saving technology, the memory circuit to reduce actual power consumption through a chip Selection signal CS, which is equivalent to a memory address signal between consumption in standby mode and a consumption switched in normal operation.

In a further device according to the prior art is the change of an address signal by an address change detector circuit (ATD) detects, whereupon for an internal operation required clock pulse in Ab dependence on the detector signal and a read memory amplifier only for a necessary time duration is activated to reduce power consumption.

Furthermore, as shown in JP-A-61-45354, in an LSI Logic, such as a microprocessor,

• a) a method known, each current control commands for a variety of functional blocks and the corresponding functional blocks selectively by Program to reduce electricity consumption activated and the activated,
• b) a method known that a clock control circuit for provides for each functional block and for which the delivery tion or non-delivery of a clock pulse to reduce the Power consumption is controlled, and
• c) a method known that a current control circuit for provides each functional block and the power supply of the functional block that is not involved in the execution of a Command is involved, interrupting power consumption to reduce.

However, the noise is not reflected in the prior art notices that by a sudden change in Stromver supply when switching between normal power up and the lower power consumption in operation voltage line and the ground line is induced. in the The following problems occur in connection with this:

• 1. Since the circuit current in the short time between operation with low power consumption and normal operation changes significantly, becomes a large noise voltage through inductances and resistances of the operating voltage line and the ground line induced.
• 2. The functional circuit itself or another internal one Circuit are disturbed due to the noise voltage. But even if there is no interference, there is a certain time span required to remove the noise voltage, and the effective memory access speed is ver diminishes.

Fig. 1 shows the relationship between the change in the circuit current and the noise voltage.

Fig. 1 (A) shows the development of the noise voltage of the power supply line. Reference numeral 1300 denotes the power supply, reference numeral 1310 denotes a functional circuit block such as a memory circuit, reference numerals 1321 and 1322 denote the inductance of the power supply line or the earth system, and reference numerals 1331 and 1332 denote the resistance of the operating voltage line or the Mass systems.

Fig. 1 (B) shows the change in the current i of the power supply and the change in the supply voltage V ₁ and the ground potential V ₂ when the switch SW is turned on at a time t ₁ and turned off at a time t ₂ .

As shown in Fig. 1 (B), the switching current i changes from zero to a constant current during the period Δt ₁ when the switch SW is turned on at the time t ₁ . The supply voltage V _{1 of} the switching device changes very strongly and shows a peak in the negative direction. The ground potential also changes very strongly and shows a peak in the positive direction. If the switch SW is turned off at the time t ₂ , the circuit current i changes from the constant current to zero in the period Δt ₂ . The supply voltage V _{1 of} the circuit changes very strongly and shows a peak in the positive direction, the ground potential V _{2 also} changes if very strongly and shows a peak in the negative direction.

It is assumed that circuit 1310 of FIG. 1 (A) contains 500 sense amplifiers, each of which has a current consumption of 2 mA, and that the current is switched from zero to constant current in a time Δt ₁ = 1 ns . If it is further assumed that the resistors 1331 and 1332 are disregarded and the inductivities 1321 and 1322 are L = 5 nH, the power supply noise V _{n is} through

given.

Such a high power supply noise is one modern semiconductor integrated circuit, which at a  Operating voltage of 5 volts or less, not permitted.

Even if the noise can be reduced to an appropriate level, the times t ₁ and t _{2 are} necessary to eliminate the power supply noise and the ground potential noise, as shown in Fig. 1 (B). This time depends on the current switching time and is normally 103 ns. Such a period of time is unacceptable for an ultra-high-speed memory that requires an access time of less than a few nanoseconds and represents a major obstacle to high-speed operation.

The one that occurs when the supply current changes Problem can be attributed to a variety of arithmetic logic Units in a semiconductor chip and on other functio Apply circuit blocks.

Various techniques have been introduced in recently developed high-performance microprocessors to improve their processing performance. The processing power of the computers can be assessed as follows:

where CPI is the number of commands required Cycles is.

The remarkable technology has been around for several years of the RISC processors. A main goal of these processors is to increase the CPI to one approach.  

Currently, as further developments of the RISCs are the Super scalar and VLIW (VeryLongInstructionWord) techno logic (very long command word). With this tech nology, up to n commands are generated in parallel errors are decoded in parallel and executed in parallel. If you further increase the parallelism of the hardware, the CPI value in the above formula becomes 1 / n re reduced and increased the performance of the computer. In the high speed arithmetic logic circuit one Super scalar or VLIW type computers will be a dif Reference logic circuit using bipolar transistors or a low amplitude circuit using BiCMOS uses, however, consumes a circuit that constantly requires a direct current, a relatively large amount of electricity.

In super scalar or VLIW microprocessors, n are high speed arithmetic logic circuits with the same Chen function required. Therefore, the performance increases taking arithmetic logic circuits with the factor n.

The corresponding technology is in NIKKEI Electronics No. 487, Nov. 27, 1989, pages 191-200.

As can be seen from the above description, in the State-of-the-art power saving technology at integrier th semiconductor circuits or electronic circuits, such as microprocessors, the problem of rough in ground lines or the operating voltage lines when the power is turned on What causes faults in the circuits or a certain time is required before the noise disappears disappears so that a quick start is not possible.

In a microprocessor according to the prior art an on-chip memory because of the compromise between noise suppression in the power supply scarf  device and higher speed of memory access difficult to operate at a very high speed to reach.

Microprocessors with cache memory are described above been, however, the problems with integrated half conductor circuits or for electronic circuits with a functional block that is a high speed operation requires the same.

An integrated circuit arrangement is known from DE 28 25 770 with function blocks in which information is gradually processed, known in which only the one Function blocks required for information processing the operating voltage source can be connected. For each connection of the operating voltage source is a Sequence control provided after detection of a start criterion is activated by a function block and corresponding switch closes in a predetermined manner or opens. The function blocks are not required Time periods in standby mode with a reduced loading drive voltage or with intermittent operation voltage operated. The problem of reducing or ver avoidance of switching noise by choosing the time Electricity rise and fall at the start of operation or loading The driving end of the function blocks is in this publication not addressed.

US 3,736,569 relates to a system for controlling the current consumption of computers, in which a decoder is provided, which is the duration of operation of a Memory chip determines and causes the current supply of the relevant memory module and is turned off. This publication does not concern either the task of reducing the power supply area nice.  

In the publication "Integrated digital modules", small Internship, by Karl Reiss, publisher Siemens Aktiengesellschaft shaft, Berlin, Munich, 1970, are on pages 214 to 216 protective measures in the voltage supply of TTL Switching elements explained, which are accordingly not functional circuit blocks with associated Power supply is concerned. Because when switching one TTL switching element also the rest potential of other switching links changes and also the load capacity when switched on the line and the inputs connected to it Output of the relevant switched switching element ent will load what loads the ground line of the switching element, are so-called support to avoid these phenomena capacitors provided directly on the switching element, which "support" the operating voltage. Such condensate gates stabilize the power supply of non-switched Switching elements and are not used to implement a ge targets the selected current rise with the switching element switched other.

It is therefore an object of the invention to have an integrated half provide a circuit that has a low power and has operated at high speed ben can be, if the power supply of a functional circuit block is prevented becomes noise and the circuit without Malfunction works. A corresponding procedure is also intended can be specified. This task also relates on microprocessors that have an on-chip memory, like at example, have a cache, and on microprocessors processing in parallel.  

This object is achieved independently by the invention current claims solved. The subclaims relate to partial embodiments of the inventive concept.

The method according to the invention for controlling the current consumption in integrated semiconductor circuit arrangements with a microprocessor with at least one functional circuit block comprises the following steps:

• - Detection of the start of operation of the functional scarf blocks before its actual start of operations,
• - Supply of the functional circuit block with the operating current required for its operation actual start of operation and during its operation and
• - Removal of the operating current from the functional circuit block after its operation ends;

it is characterized by

• - Increase the circuit current of the functional scarf tion blocks for a predetermined period of time before actual start of operation from a standby power, at which the functional circuit block low lei has power consumption on the operating current and
• - Reduction of the circuit current after the end of operation functional circuit blocks during a given Time on standby power.

The integrated semiconductor circuit arrangement according to the invention with low power consumption, which is particularly suitable for carrying out the method defined above, comprises:
a microprocessor which has:

• One or more functional circuit blocks,
• - a command data register,
• - An instruction decoder, the instruction data from the Command data registers decoded and command control signals to control the operation of the functional Circuit blocks generated, and
• - A facility that the start of operation and the Operational end of the functional circuit blocks before their actual start of operations recorded and electricity tax outputs signals to a current control device which Start of operation the circuit current of the functional Circuit blocks from a lower standby current, at which the functional circuit block in question is a has lower power consumption on operation current increases and during the period of operation of the radio tional circuit blocks and after his End of operation the operating current back to standby Lowers electricity;

it is characterized in that

• - The instruction decoder start of operation announcement generated signals and
• - The device is a current control signal generator receives the start of operation announcement signals and Outputs current control signals to the current control device, due to which they change the circuit current of the functional  Circuit blocks during a predetermined period of time their start of operation from standby power to the Be drive current increases and after its end of operation during a predetermined period of time on the standby current ver wrestles.

According to an advantageous embodiment, the Be false decoder two instruction decoders, the first instruction decoder instruction data from the instruction da decoded and command control signals for control Operation of the functional circuit blocks testifies and the second instruction decoder instruction data from the Command data register decoded and start of operation arrival generated signals.

In the invention, the memory can be clock synchronized Memory, and there may be means for generating a Memory clock signal provided for clocking the memory be the integrated on a system clock signal Semiconductor circuit arrangement and the access announcement signal based.

Alternatively, means for generating a pulse to activate a sense amplifier of the memory be seen on the system clock signal of the integrated Semiconductor circuit arrangement and the access announcement signal based, so that part or all of the reading ver stronger of the memory by the activation pulse acti fourth.

In accordance with another feature of the invention, a functional circuit block having a power supply inductance L, an allowable power supply noise V _n and a circuit current change amplitude ΔI, and means for generating an operation start announcement signal are provided to the functional circuit block a time t before the start activate the operation of the functional circuit block, where t, L, V _n and ΔI of the relationship

correspond.

The second instruction decoder can be designed such that he the access announcement signal at least one stage generated before the execution stage of the memory access. The activating agents can be designed so that they a driver current of one intended for the memory current level lower than the predetermined operating current level to the predetermined operating current level in a predetermined speed from the time of generation of the access announcement signal up to the time of loading Increase the beginning of the memory access execution stage.

The microprocessor of the invention includes at least one functional circuit block, a first command decode for decoding a command and forwarding the Execution on the functional circuit block, one second instruction decoder to detect execution through the functional circuit block before the start of the Execution for generating an operation announcement signals and activation means for activating the radio tional circuit blocks before starting execution based on the announcement signal.

The memory of the invention has a functional scarf tion block on which an announcement signal for the Be receives drive start, the circuit current to one before certain level increases in a predetermined time, the  starts receiving the announcement signal to start from an operation with low power consumption on a loading urged to change with normal power consumption and after the execution of the operation the circuit current in one predetermined time to lower the current that is operating corresponds to low power consumption, and in the Be urged to switch lower power consumption; the memory is activated by the access announcement signal and performs a predetermined store operation in accordance tion with an address signal, a read / write control signal and a data input / output signal.

The memory has an information processing unit on, such as a workstation or a Computer that has at least one integrated semiconductor scarf tion arrangement, a microprocessor, a functional Circuit block and / or include a memory.

An exemplary embodiment of the invention is explained in more detail below with reference to FIGS. 2 to 13; show it:

FIG. 2 is a block diagram showing the configuration of a micro processor according to a first embodiment of the invention;

Fig. 3: a command execution stage of a microprocessor;

Fig. 4 is a signal flow diagram of the timing of the operation of the microprocessor Be;

Fig. 5 (A) is a block diagram of the configuration of an access announcement signal generator;

Fig. 5 (B): the configuration of a memory access prediction circuit;

Fig. 5 (C): a signal flow diagram for the operation of the circuit device;

FIG. 6 is a block diagram showing a configuration of a cache memory;

Fig. 7 (A): a circuit diagram of a current control signal generator;

Fig. 7 (B): a signal flow diagram for the operation thereof;

Fig. 8 is a signal flow diagram showing the relationship between the access announcement signal and the supply current;

Fig. 9 (A) is a block diagram showing the configuration of a power control signal generator;

Fig. 9 (B): a signal flow diagram for operating the same;

Fig. 10 (A): a block diagram of a current control signal generator;

Fig. 10 (B): a signal flow diagram for operating the same;

FIG. 11 is a circuit diagram of an address buffer;

Fig. 12: a block diagram of a peripheral circuit of a memory cell and

Fig. 13 is a circuit diagram of an output driver.

The following is an embodiment of an integrated one Semiconductor circuit of the invention with reference to FIG described a microprocessor.

Fig. 2 shows the configuration of a microprocessor (MPU) according to a first embodiment of the invention.

Reference numeral 100 denotes a one-chip microprocessor. To simplify the description, only the elements of the internal configuration necessary for understanding the embodiment are shown, the other elements are omitted.

Reference numeral 101 denotes a program counter that generates a pick-up address of command data in sync with a clock signal CLK. Reference numeral 102 denotes a memory address register that holds a fetch address of an instruction cache 103 . Reference numeral 104 denotes an instruction data register which holds the instruction data fetched from the instruction cache 103 .

Numeral 111 designates another address register holding a read or write address of a data cache 112 , numeral 113 designates a data register holding read data of the data cache 112 or write data for the data cache 112 .

The command data register 104 and the data register 103 are connected by an internal data bus 172 and exchange data with an external data bus 161 via an input / output controller 160 .

Reference numeral 120 denotes a first command decoder which decodes the output 105 of the command data register 104 and generates command control signals 121 and 122 . Reference numeral 140 denotes an arithmetic logic unit which receives the data required for an operation from a register file 150 via an internal bus 73 , which carries out the arithmetic, the logical or the shift operation and the operation result via an internal bus 174 into the register file 150 writes. In another case, it writes the operation result to a memory address register 111 via an internal bus 175 .

The output 121 of the instruction decoder 120 identifies the type of operation for the arithmetic logic unit (ALU) 140 . The output 122 of the instruction decoder 120 identifies a read or write operation for the register file 150 .

Numeral 130 denotes a second instruction decoder that decodes the output 105 of the instruction data register 104 , predicts memory access to the data cache 112, and provides the memory access 112 with a memory access signal 131 .

The data cache 112 executes the predetermined memory access due to the memory access indication signal 131 of the address signal from the memory address register 111 and a read / write control signal (not shown).

The second instruction decoder 130 may have the function of sending arithmetic logic unit 140 , register file 150 and other units start of operation announcement signals 132 and 133 as required.

Fig. 3 shows a typical instruction execution stage of the microprocessor of this embodiment.

Instructions 1 and 2 show an execution stage of a RR (register-to-register operation).

In an IF stage (instruction fetch stage), the instruction data is fetched from the instruction cache 103 . In stage D (instruction decoding stage), they are decoded by instruction decoder 120 . At the Ex stage (instruction execution stage), a predetermined operation is performed by the arithmetic logic unit 140 . Finally, an operation result is written to the register file 150 at a stage W (write stage).

For a load instruction and a store instruction, see FIG. 3 middle, by which access to data cache 112 is requested, stage IF and stage D are the same as these stages of the RR operation. In the next stage AC (address calculation), an effective address is calculated for access to the data cache 112 . At a stage CA (cache access), data cache 112 is accessed. Finally, in stage W, the fetched data is written into register file 150 . As described above, in the load / store instruction, the effective address calculation stage AC is always between the decode stage D and the memory access stage AC. In the present embodiment, the memory access request is predicted at the D stage two stages before the CA stage and the access announcement signal is sent to the cache memory 112 .

Fig. 4 shows the signal flow diagram from the fetch of the command to the generation of the access announcement signal and the access to the memory in more detail.

Reference numeral 3 denotes a system clock CLK. Its period is equal to a stage period of the instruction execution stage of Fig. 3 and may be, for example, 5 ns.

Reference number 3 b denotes the IF stage. The load / store commands M ₁ to M _{5 are} fetched.

Reference number 3 c denotes the D stage, in the stage following the IF stage, the load / store instructions M ₁ to M _{5 are} decoded.

Reference number 3 d denotes the AC stage. The effective addresses A ₁ to A ₅ decoded in D stage 3 c for the load / store commands M ₁ to M ₅ are calculated.

Reference number 3 e denotes the memory addresses A ₁ to A ₃ , which are calculated in the address calculation. The memory access is actually performed in CA stage 3 f using these addresses.

Reference numeral 3 g denotes the memory access prediction signals M ₁ to M ₄ , which are generated by the second instruction decoder 130 shown in FIG. 1. They are generated due to the decoding of M ₁ to M ₅ in D stage 3 c.

The reference numeral 3 h denotes the memory access announcement signal ( 3 ), which is generated by processing the memory access prediction signals M ₁ to M ₅ ( 3 g). It is delivered to data cache 112 .

The access announcement signal 3 h generates a stage before the E ₁ stage 3 f in which the memory is actually accessed, and a stage before the E ₃ stage is also generated.

FIG. 5 (A) shows the internal configuration of the second instruction decoder 130 (see FIG. 2) that generates the memory access announcement signal 131 . Fig. 5 (B) shows the internal configuration of the memory access prediction circuit 410 , and Fig. 5 (C) shows a signal diagram in the corresponding operation.

Reference numeral 410 denotes the memory access prediction circuit which detects whether or not the command data supplied from the command data register 104 represents a command that causes the memory access. Specifically, as shown in Fig. 5 (B), after the load and store fail to be detected, a detection signal DET (detection) is generated as shown by 3g in Fig. 5 (C). Reference numeral 420 be a flip-flop that holds the detection signal DET ( 3 g) on the basis of the clock signal CLK ( 3 a) and at its Q output ( 4 a) the access announcement signal PR ( 3 h) shown in FIG. 5 (C) ) generated.

The signal PR 131 of the embodiment is a positive active signal, although its polarity is not essential.

FIG. 6 shows the internal configuration of the data cache 112 (see FIG. 2).

Reference numeral 510 denotes an address buffer that receives an address signal A _i and generates positive and negative address signals that are requested by an address decoding driver 520 . The output of the Adressendekodie approximately driver 520 is supplied to the selection of a storage field which is to be read or written to a memory array 530th

Numeral 540 denotes a sense amplifier that amplifies a small signal that has been read from the memory array to a given signal level. Reference numeral 550 denotes an output driver which drives an output D _o which has a relatively high load.

Reference numeral 560 denotes a write control circuit that writes write data D _i into a predetermined address of the memory array 530 by a write control signal WE.

Reference numeral 570 denotes a current control signal generator, which receives the access announcement signal PR for generating at least one current control signal 575 . In the exemplary embodiment, assuming that the data cache 112 is being used proportionally or that an access request other than the command execution is being followed, it receives a plurality of announcement signals PR ₁ ,... PR _n for generating at least one current control signal 575 .

The control of the circuit current by the current control signal 575 is applicable to all circuit elements except the current control signal generator 570 in the cache memory 112 . The selection of the circuit to be controlled depends on the configuration and application of the applicable hardware.

Fig. 7 (A) shows the configuration of the current control signal generator (see Fig. 6), and Fig. 7 (B) shows a signal diagram of the current control signal generator.

Reference numeral 610 denotes an OR gate for the OR operation of the access announcement signals PR ₁ to PR _n , the output of which is at an inverter 620 and a flip-flop 660 . Reference numeral 630 denotes a NOR gate for NOR gating the output of the inverter 620 and the Q output of the flip-flop 660 to generate a signal PUMP as shown at 6c in Fig. 7 (B).

Reference numeral 640 denotes an AND gate for ANDing the O output 6 b of the flip-flop 660 and the clock signal CLK 3 a for generating a signal MCLK 6 d, as shown in Fig. 7 (B). Reference numerals 650 and 670 denote an OR gate and a delay circuit, respectively. The OR gate 650 is used to link the MCLK signal 6 d and the MCLK signal delayed by the delay circuit 670 by a predetermined time and generates a signal SA as shown in Fig. 7 (B).

MA 6 e in Fig. 7 (B) shows a memory address in the memory access execution cycle.

As shown in Fig. 7 (B), the memory access to the memory addresses A ₁ and A _{2 takes place} in the clock stages t ₂ and t ₃ ( 6 g). On the other hand, the PUMP signal 6 c rises in stage t ₁ , which is a stage before stage t ₂ , and drops at the end of stage t ₃ .

The circuit current is controlled based on the PUMP signal 6 c. This is shown in Fig. 8. As shown in FIG. 7 a in FIG. 8, the current of the controlled circuit is increased from i ₁ to a predetermined current i ₂ in accordance with the PUMP signal 6 c, and the current level is maintained in the memory access stages t ₂ and t ₃ and from Beginning of the t ₄ stage, in which the memory access was carried out, lowered to a low current level i ₁ .

The MCLK signal 6 d ( FIG. 7 (B)) is a pulse signal which is generated in the memory access stages t ₂ and t ₃ and serves as a clock in a clock-synchronized memory. The clock-synchronized memory is described in the following publications :

• 1. Kevin J. O'Connor, Modular Embedded Cache Memory for a 32b Pipelined RISC Microprocessor, 1987 IS SCC, pp. 256-257.
• 2. Masanori Odaka et al., A512 kb / 5 ns BiCMOS RAM With 1 KG / 150 ps Logic Gate Array, 1989, IS SCC, pp. 28-29.
• 3. Masayoshi Kimoto et al., A 1.4 ns / 64 kb RAM With 85 ps / 3680 Logic Gate Array, 1989 CI CC, pp. 15.8.1-15.8.4.

The SA signal 6 f is generated in the memory access stages t ₂ and t ₃ and only serves as a signal for activating the sense amplifier for a predetermined period of time.

With independent control of the activation of the reading amplifier is caused by the current switching Power supply noise within an allowable range empire and can serve as a signal to the mini the activation time of the sense amplifier, the one has high power consumption.

An example of circuit current control by the PUMP Signal and the SA signal is described below.  

Fig. 9 (A) shows a first example of the circuit that controls the circuit current through the PUMP signal, and

Fig. 9 (B) shows operation pulse waveforms.

Reference numerals 811 and 812 denote PMOS, the sources of which are connected to a power supply V ₁ and the gates of which are connected to one another and to the drain of a PMOS 811 . The reference numerals 821 , 822 and 823 denote NMOS. The drain of the NMOS 821 is connected to the drain of the PMOS 811 , at whose gate the PUMP signal is present and the source of which is connected to a reference potential.

The drain of the NMOS 822 is connected to the drain of the PMOS 812 ; its gate is connected to the output of an inverter 830 and its source is connected to the reference potential. The input of inverter 830 is connected to the PUMP signal.

Reference numeral 840 denotes an active circuit such as a differential amplifier. It is provided in a functional circuit block, such as data cache 112 , arithmetic logic unit 140 or register file 150 (see FIG. 2). A predetermined operating current is supplied by a constant current source 850 through the NMOS 823 . The gate of the NMOS 823 and the ground GND are connected to the integration capacitor C.

The PMOS 811 and 812 and the NMOS 821 and 823 form a current mirror circuit. As shown in Fig. 9 (B), when the PUMP signal rises from the O level to 1, a predetermined charging current flows from the PMOS 812 to the capacitor C, and the gate voltage Vg of the NMOS 823 and the current i of the circuit 840 increase slightly with predetermined tracking speeds (change speeds per unit time) as shown in Fig. 9 (B) center and below. The rise time t ₁ corresponds to the stage t ₁ , as shown in FIG. 8.

Likewise, when the PUMP signal changes from level 1 to level 0, voltage Vg and current i drop slightly at a predetermined tracking rate. The fall time t ₄ corresponds to the stage t ₄ , as shown in FIG. 8. The rise time t ₁ and the fall time t _{4 of} the current i are not necessarily the same. The fall time t ₄ can be short in a suitable range because the switching operation has been stopped.

Fig. 10 (A) shows a second example of the circuit for controlling the circuit current using the PUMP signal, and Fig. 10 (B) shows the operation pulse signal shape.

Reference numerals 911 to 914 denote inverters, reference numerals 921 to 923 denote NMOS. Reference numerals 931 to 933 denote constant current sources, and reference numeral 940 denotes an active circuit, such as a differential amplifier, which is provided in a functional circuit block, such as the data cache 112 of the arithmetic logic unit 140 or the register file 150 (see. Fig. 2).

The delay times of the inverters 912 to 914 are selected so that they increase in the order 914 , 913 , 912. Thus, when the PUMP signal changes from 0 to 1, as shown in FIG. 10 (B), those in the NMOS increase 921 to 923 flowing currents i ₁ to i ₃ with a predetermined time delay, and the operating current of the active circuit 940 increases gradually after the time period t ₁ to a constant current i ₁ + i ₂ + i ₃ .

Likewise, when the PUMP signal changes from 1 to 0, the circuit current 940 gradually drops in time t ₄ . This means that similar to the embodiment of FIG. 9, a soft current change is achieved.

The rise time t ₁ and the fall time t ₄ correspond to stage t ₁ and stage t ₄ of FIG. 8, as is also the case in the first exemplary embodiment.

In the exemplary embodiments described above, the Switching current using the PUMP signal and  SA signal controlled. The circuit current can alternatively can also be controlled by other common methods.

For the first circuit current control circuit, an example of the circuit current control in the data cache 112 is explained (see FIG. 2).

FIG. 11 shows an embodiment of the current control for the address buffer 510 in FIG. 6 of the data cache 112 .

The reference numerals 1011 to 1014 denote NPN transistors, the reference numerals 1021 and 1022 denote resistors, the reference numerals 1031 to 1033 denote NMOS, and the reference numerals 1041 to 1043 denote constant current sources.

The emitters of the NPN transistors 1011 and 1012 are connected to one another and to the constant current source 1041 via the NMOS 1031 . The bases of the NPN transistors 1011 and 1012 are connected to an address signal A _i and a reference potential V _R , respectively, and their collectors are connected to a power supply V ₁ via the resistors 1021 and 1022 . The collectors of NPN transistors 1013 and 1014 are connected to the power supply V ₁ and their bases are connected to the collector of NPN transistor 1011 and the collector of NPN transistor 1012 . The emitters of NPN transistors 1013 and 1014 are connected to constant current sources 1042 and 1043 via NMOS 1032 and 1033, respectively.

The output a _i is taken at the emitter of the NPN transistor 1014 as the non-inverted output of the input i and the output ai is taken at the emitter of the NPN transistor 1013 as the inverted output of the input A _i . The gates of the NMOS 1031 to 1033 are connected together with the control signal Vg, which corresponds to the signal Vg shown in FIG. 9.

The NPN transistors 1011 and 1012 , the resistors 1021 and 1022 and the constant current source 1041 form a dif ferential amplifier. When the current control signal Vg is at level 1 and the address signal A _{i is} higher than Vg, the NPN transistor 1011 turns on, the NPN transistor 1012 turns off, the collector of the NPN transistor 1011 is at the level 0 , and the collector of NPN transistor 1012 is at level 1.

The collector of the NPN transistor 1011 is connected to the base of the emitter follower transistor 1013 , which generates the 0-level output a _i at its emitter. In the same way, the collector of NPN transistor 1012 is connected to the base of emitter follower transistor 1014 , which produces level 1 output a _i at its emitter.

If the address signal A _{i is} lower than V _R , the NPN transistor 1011 and the NPN transistor 1012 operate in opposite directions, so that the ai output is at level 1 and the a _i output is at level 0.

When the current control signal Vg is at level 0, all NMOS 1031 to 1033 are turned off. Since there is no current path from the power supply V ₁ to ground GND, the circuit does not consume any current.

Because the current control signal Vg has the predetermined rise and fall times as shown in Fig. 9 (B), a smooth current change takes place, as shown in Fig. 8, 7a.

Therefore, the power supply and ground line noise (see FIG. 1 (B)) that occur when the power is switched can be suppressed to a desired level.

FIG. 12 shows an example of circuit current control for the decoder 520 driver, memory array 530, and sense amplifier 540 (see FIG. 6) in the data cache.

Reference numerals 1161 and 1162 denote NOR gates which correspond to the end stage of the address decoder.

Reference numerals 1171 and 1172 denote a word driver containing AND gates. The outputs of the address end encoders 1161 and 1162 are connected to one input, the control signal Vg is connected to the other input, and the word lines WL ₁ and WL ₂ are operated by its output.

Reference numeral 1100 denotes a 4-MOS memory cell, but is not limited to this. Only one cell is shown for better clarity.

Reference numerals 1111 and 1112 denote load MOS for pulling up bit lines. Reference numerals 1113 to 1116 denote MOS switches for selecting the bit lines. A desired bit line is connected to a common data line 1120 by the column selection signals C ₁ and C ₂ .

Reference numerals 1121 and 1122 denote emitter follower circuits that contain NPN transistors. They shift the signal level on the common data line 1120 by V _BE (base-emitter voltage) and deliver it to the base of the NPN transistor 1123 and 1124 . The emitters of NPN transistors 1123 and 1124 are connected to one another and to a current source 1151 via an NMOS 1141 . The collectors of the NPN transistors 1123 and 1124 are connected to the power supply V ₁ via the resistors 1131 and 1132 .

NPN transistors 1123 , 1124 , resistors 1131 , 1132 and current source 1151 form a differential amplifier that amplifies a small signal that is read out from memory cell 1100 to a predetermined level. Likewise, reference numeral 1150 denotes a differential amplifier which has two resistors and two NPN transistors and is connected via an NMOS 1142 to a constant current source 1152 .

The two inputs of amplifier 1150 are connected to the collectors of NPN transistors 1123 and 1124 . The signals applied to it are amplified to generate an output signal with a predetermined amplitude at a circuit 1151 .

The current control signal Vg (see FIG. 9) is connected to an input of the AND gates 1171 and 1172 , respectively. When Vg is level 1 , AND gates 1171 and 1172 are selectively driven to selectively drive word lines WL ₁ and WL ₂ . On the other hand, if Vg is at level 0, the word drivers including AND gates 1171 and 1172 are turned off. Accordingly, the currents flowing in the memory cells including the memory cell 1000 are blocked. Therefore, if the memory is not accessed, unnecessary power consumption is avoided.

Likewise, the current control signal Vg is connected to the gates of the NMOS 1141 and 1142 . When Vg is at level 1 , NMOS 1141 and 1142 are turned on and when Vg is at level 1 they are turned off.

Therefore, flows when the memory is not accessed no current in the sense amplifier, and unnecessary current consumption need is avoided.

Numeral 7 a in Fig. 8 shows the change in the circuit current by the current control signal Vg. Therefore, the power supply and ground noise caused by the switching of the current can be reduced to an allowable level and, because there is no noise at the start of the memory access, high-speed operation can be achieved will.

Fig. 12 shows that when switch SW 1180 is switched to the position of signal SA, NMOS 1141 and 1142 are activated for a short period of time. As described above, the signal SA is a pulse signal which assumes the level 1 only for the predetermined time of the memory access stages t ₂ and t ₃ . In the exemplary embodiment, it supplies the current to the sense amplifier only for the time in which the memory is being accessed. Therefore, electricity can be saved.

Fig. 13 shows an example of the current control signal for the output driver 550 (s. Fig. 6) of the data cache memory 112.

Drain, gate and source of a PMOS 1211 to the base of an NPN transistor 1142, the input V _on and the power supply V ₁ is connected. The drain, gate and source of an NMOS 1221 are connected to the base of the NPN transistor 1241 , the input V _one and one end of a resistor 1251, respectively. The drain, gate and source of a PMOS 1222 are connected to the drain of the NMOS 1221 , a current control signal Vg and the base of the NPN transistor 1241 , respectively. A capacitor 1261 is connected in parallel to the resistor 1251 . Anode and cathode of a diode 1231 are connected to the collector and the base of the NPN transistor 1241 , and the power supply V ₁ is connected to the collector of the NPN transistor 1241 . The emitter of NPN transistor 1241 is an output terminal and a terminating resistor 1252 is connected to the output terminal and the power supply V ₂ .

When the current control signal Vg is at level 1, the PMOS 1222 is turned off. When the input V is _a at the 0 level, the PMOS is turned off 1211 and the NMOS 1221st Therefore, the base voltage of the NPN transistor 1241 is increased via the PMOS 1211 , and the output V _out assumes level 1. If V is _a 1 on the level, the PMOS is turned off 1211 and the NMOS 1221 is turned on. Therefore, the base voltage of the NPN transistor 1241 drops and the output V _out assumes the level 0.

The diode 1231 serves as a clamp to suppress the drop in the base potential of the NPN transistor 1241 within a predetermined level.

Resistor 1251 is a current limiting resistor and capacitor 1261 is an accelerating capacitor.

When Vg is at level 0, the PMOS 1222 turns on. The base potential of the NPN transistor 1241 drops without regard to the level of the input V _a decreases so that the output V _from the level assumes 0th

In this way, the same effect as in the circuit current controls for the address buffer 510 , the decoding driver 520 , the memory array 530 and the sense amplifier 540 is achieved.

The circuit current control in data cache 112 (see FIG. 2) has been described above for the first circuit current control, although the second circuit current control (see FIG. 8) or other circuit current control may also be used.

In the embodiment, a reduction in the power was needed when accessing the memory that the Access announcement signal used. The idea of the invention is in the same way on every functional circuit reversible, their operation by decoding a Be is controlled such as an Arith Metic logic unit in a one-chip microprocessor or a register file. In the exemplary embodiment, the Switching current in synchronism with the stage before the Execution stage of the operation. A synchronizer This is not always necessary, but the increase can up to a time before the start of the execution stage be started to lower the power supply and Ground line noise that occurs when the current changes, to a predetermined level is sufficient. In this Case can instead of synchronizing with the stage, before the execution stage, the PUMP signal be made effective at a desired time.

In the exemplary embodiment, the current for the memories increases circuit and the other functional circuit in the Chip microprocessor before the start of the operation by the  Access announcement signal that before the actual loading Drive the circuit is generated with the predetermined Speed. Therefore, the functional consume Circuits that are required for circuit performance Electricity only during actual operation. Therefore the power consumption of the one-chip microprocessor is reduced.

Because thanks to the fact that electricity is saved, new radio can be introduced, it becomes functional high quality and highly integrated arrangement achieved.

Because the circuit current with the functional circuit a predetermined speed is changed, the Power and ground line noise that the current change occurs up to the predetermined level be lowered. It will therefore be a highly reliable one Switching operation achieved.

In the functional circuit according to the embodiment The game is the power supply noise and the mess noise at the time the actual Operating disappeared, the circuit can be among the best Current conditions are operated and works with a high speed.

The invention is also in super-scalar RISC processors advantageously applicable.

In the super scalar RISC processor, several arithmetic Logic units that share a register file seen, and the commands are simplified to the number to reduce the pipeline stages, and a variety of Instructions are used to control the variety of arithmetic Logic units retrieved in one machine cycle. It will namely a variety of commands during a machine cycle accessed and executed in parallel, and a variety  of arithmetic logic units are used to increase the Processing power operated in parallel.

As explained above, an inte free semiconductor circuit arrangement and in particular Microprocessor, the one-chip memory, such as has a cache, and contains a low one Power consumption of the functional circuit block and enables high-speed operation posed.

Claims (13)

1. A method for controlling the current consumption in integrated semiconductor circuit arrangements with a microprocessor with at least one functional circuit block ( 112 , 140 , 150 ), comprising the following steps:

• 1. Detection of the start of operation of the functional circuit block ( 112 , 140 , 150 ) before its actual start of operation,
• 2. Supply of the functional circuit block ( 112 , 140 , 150 ) with the operating current (i ₂ ) required for its operation to begin its actual operation and during its operation (t ₂ , t ₃ ) and
• 3. removal of the operating current (i ₂ ) from the functional circuit block ( 112 , 140 , 150 ) after its end of operation,

marked by

• 1. Increase in the circuit current (i) of the functional circuit block ( 112 , 140 , 150 ) during a predetermined time period (t ₁ ) before the actual start of operation from a standby current (i ₁ ) at which the functional circuit block ( 112 , 140 , 150 ) has low power consumption, on the operating current (i ₂ ) and
• 2. Reduction of the circuit current (i) after the end of operation of the functional circuit block ( 112 , 140 , 150 ) for a predetermined time period (t ₄ ) to the standby current (i ₁ ).

2. The method according to claim 1, characterized in that the beginning of the predetermined period (t ₁ ) during which the circuit current (i) from the standby current (i ₁ ) to the operating current (i ₂ ) is increased, not with the Operating cycle (t ₂ , t ₃ , CLK) of the functional circuit block ( 112 , 140 , 150 ) is synchronized point in time. 3. The method according to claim 1, characterized in that the beginning of the predetermined period (t ₁ ) during which the circuit current (i) from the standby current (i ₁ ) to the operating current (i ₂ ) is increased, with the operating cycle (t ₂ , t ₃ , CLK) of the functional circuit block ( 112 , 140 , 150 ) is synchronized time. 4. The method according to any one of claims 1 to 3, characterized in that the functional circuit block ( 112 , 140 , 150 ) is a data cache memory ( 112 ), an arithmetic logic unit ( 140 ) or a register file ( 150 ). 5. The method according to any one of claims 1 to 4, characterized in that when a command is decoded, it is averaged which functional circuit block ( 112 , 140 , 150 ) should go into operation at its actual start of operation. 6. Integrated semiconductor circuit arrangement, in particular for performing the method according to claims 1 to 5, with a microprocessor ( 100 ) which has:

• 1. one or more functional circuit blocks ( 112 , 140 , 150 ),
• 2. a command data register ( 104 ),
• 3. a command decoder ( 120 , 130 ) that decodes command data from the command data register ( 104 ) and generates command control signals ( 121 , 122 ) for controlling the operation of the functional circuit blocks ( 112 , 140 , 150 ), and
• 4. a device ( 570 ) which detects the start of operation and the end of operation of the functional circuit blocks ( 112 , 140 , 150 ) before their actual start of operation and outputs current control signals ( 575 ) to a current control device which, at the start of operation, the circuit current (i) of the functional Circuit blocks ( 112 , 140 , 150 ) from a lower standby current (i ₁ ), in which the functional circuit block in question ( 112 , 140 , 150 ) has a lower power consumption, increased to the operating current (i ₂ ) and during the Duration (t ₂ , t ₃ ) of the operation of the functional circuit block ( 112 , 140 , 150 ) is maintained and the operating current (i ₂ ) is reduced again to the standby current (i ₁ ) after its end of operation,

characterized in that

• 1. the command decoder ( 120 , 130 ) Betriebsbe start announcement signals ( 131 , 132 , 133 ) generated and
• 2. The device ( 570 ) is a current control signal generator which receives the start of operation announcement signals ( 131 , 132 , 133 ) and outputs current control signals ( 575 ) to the current control device, on the basis of which it blocks the circuit current (i) of the functional circuit blocks ( 112 , 140 , 150 ) during a predetermined period of time (t ₁ ) before the start of its operation from the standby current (i ₁ ) to the operating current (i ₂ ) and after its end of operation for a predetermined period of time (t ₄ ) to the standby current (i ₁ ) decreased.

7. The semiconductor circuit arrangement according to claim 6, characterized in that the command decoding device ( 120 , 130 ) comprises two command decoders, the first command decoder ( 120 ) decoding command data from the command data register ( 104 ) and command control signals ( 121 , 122 ) for controlling the operation of the functional circuit blocks ( 112 , 140 , 150 ) and the second instruction decoder ( 130 ) decodes instruction data from the instruction data register ( 104 ) and generates start of operation announcement signals ( 131 , 132 , 133 ). 8. A semiconductor circuit arrangement according to claim 6 or 7, characterized in that the current control device is designed such that the start of the predetermined period (t ₁ ) during which the circuit current (i) from the standby current (i ₁ ) to the operating current (i ₂ ) is a time that is not synchronized with the operating cycle (t ₂ , t ₃ , CLK) of the functional circuit block ( 112 , 140 , 150 ). 9. A semiconductor circuit arrangement according to claim 6 or 7, characterized in that the current control device is designed so that the start of the predetermined period (t ₁ ) during which the circuit current (i) from the standby current (i ₁ ) to the operating current ( 12th ) is increased, is a time synchronized with the operating cycle (t ₂ , t ₃ , CLK) of the functional circuit block ( 112 , 140 , 150 ). 10. A semiconductor circuit arrangement according to one of claims 6 to 9, characterized in that the functional circuit block ( 112 , 140 , 150 ) is a data cache memory ( 112 ), an arithmetic logic unit ( 140 ) or a register file ( 150 ). 11. A semiconductor circuit arrangement according to one of claims 6 to 10, characterized in that the command decoding device ( 120 , 130 ) the start of operation announcement signals ( 131 , 132 , 133 ) at least one stage before an operating stage of the functional circuit blocks ( 112 , 140 , 150 ). 12. Semiconductor circuit arrangement according to one of claims 6 to 11, characterized in that the current control signal generator ( 570 ) controls the current control device so that the circuit current (i) with a given rate of change to the operating current (i ₂ ) is increased. 13. Semiconductor circuit arrangement according to one of claims 6 to 12, characterized in that one or more functional circuit blocks ( 112 , 140 , 150 ) have a power supply line inductance L, a permissible power supply noise V _n and a circuit current change Δi and the period t before the start of operation of the relevant functional circuit blocks ( 112 , 140 , 150 ) of the relationship
corresponds.