DE4040382A1 - Current consumption controller for IC and microprocessor - involving activation of circuit blocks after detecting start of their operations and de-activating at end - Google Patents

Abstract

A method of controlling the current consumption in an integrated semiconducting circuit and a microprocessor with at least one functional block involves detecting the start of operation of a block before it begins, activating and then deactivating it after completion of the operation. A memory access is detected by detecting a load/memory instruction and the memory activated accordingly. USE/ADVANTAGE - High speed, low current consumption of integrated semiconducting circuit and microprocessor.

Description

The invention relates to integrated semiconductor circuit arrangements with a functional circuit block (like for example a memory, an arithmetic logic unit or an I / O controller) for which a low power consumption is sought, for example as a built-in cache, for access and multi-bit output with high speed, appropriate Microprocessors and methods for operating such Circuits with low power consumption (power consumption).

It is common in state of the art microprocessors Technology to expand parallel operation and Improve the processability of a cache built in to solve problems caused by inequality the speed of execution of an internal Command, and the speed of transmission of a Instruction and an operand from an external main memory are caused. For these reasons, the increase in Power consumption has become a serious problem.

A major purpose for installing a cache is it, commands or data at high speed provide that with the execution speed of the Microprocessor matches.

The clock period of a type microprocessor Complex Instruction Set Computer (CISC) with the current one highest speed is 25-40 MHz. It's closed expect a microprocessor type Reduced instruction set computer (RISC) at one speed of over 100 MHz is developed.

In such a high speed microprocessor  is an ultra high access speed of less than a few nanoseconds for the built-in cache required.

A distinctive feature of a built-in cache is a relatively small number of words and an extreme one high number of read bits per word (maximum 8 bits in SRAMs for general applications). For example, it is at 32-bit microprocessors currently used commonly have several hundred bits can be read out in parallel, the number of bits to be read out in parallel will increase if in the future 64-bit microprocessors be introduced.

Generally, there are highly sensitive sense amplifiers of the differential amplifier type, the bipolar transistors use, for read signal amplifiers of ultra high-speed memories suitable. However, these circuits consume relatively a lot of electricity at all times. In addition, other parts of the memory consumes electricity, even then, if the memory is not accessed unless it is special energy saving measures are planned.

Therefore, one-chip microprocessors with ultra high Access speed and multi-bit parallel output caches the power consumption by the storage circuit extremely high, so on-chip cache ultimately does not are realizable, unless suitable power saving devices be provided.

In a first prior art, known as Power saving technology, is the memory circuit to the actual Reduce power consumption through a chip selection signal CS, which is equivalent to a memory address signal, between a consumer on standby and a consumer switched in normal operation.

In a further device according to the prior art Technology is the change of an address signal by a Address transition detector circuit (ATD) detects, one for one  internal operation required clock pulse becomes dependent generated by the identifier signal, and a sense amplifier a memory is only available for a necessary period activated to reduce power consumption.

Furthermore, as shown in JP-A-61-45 354, one LSI logic, such as a microprocessor

• a) a method known, each current control commands for a variety of functional blocks and selectively through the corresponding functional blocks activated a program to reduce electricity consumption and deactivated,
• b) a method known that a clock control circuit for each functional block and where the Power supply or non-supply of a clock is controlled, the circuit for lowering the power consumption is controlled and
• c) a method known that a current control circuit provides for each functional block and the power supply of the functional block that is not in the execution a command is involved, interrupts the power consumption to reduce.

However, the noise is not in the prior art taken into account by a sudden change in the Power supply when switching between normal power consumption and the lower power consumption in the Power line and the earth line is induced. In connection this causes the following problems:

• 1) Since the circuit current in the short time between the operation with low power consumption and the Normal operation changes significantly, becomes a large noise voltage through inductances and resistances of the power line and earth line induced.
• 2) The functional circuit itself or another internal circuits are disturbed due to the noise voltage. But even if there is no disturbance, there is a definite one  Time period required to remove the noise voltage and becomes the effective memory access speed reduced.

Fig. 24 (A) shows the development of the noise voltage in the power line. Reference numeral 1300 denotes the power supply, reference numeral 1310 denotes a functional circuit block such as a memory circuit, reference numerals 1321 and 1322 denote inductances of the power supply line or the earth system and reference numerals 1331 and 1332 denote resistances of the power supply line or the earth system.

Fig. 24 (B) shows a change in a power supply i and changes in a supply voltage v₁ and a ground potential v₂ when the switch SW is turned on at a time t₁ and turned off at a time t₂.

As can be seen from the figure, the circuit current i changes during the period delta t _i from zero to a constant current when the switch SW is turned on at time t 1. The supply voltage v₁ of the circuit changes very much and shows a peak in the negative direction. The earth potential also changes very strongly and shows a peak in the positive direction. If the switch SW is turned off at the time t₂, the circuit current i changes in the period delta t₂ from the constant current to zero. The supply voltage v 1 of the circuit changes very strongly and shows a peak in the positive direction, the earth potential V 2 also changes very strongly and shows a peak in the negative direction.

It is assumed that circuit 1310 of FIG. 24 contains 500 sense amplifiers, each of which has a current consumption of 2 mA and that the current is switched from zero to constant current in a time delta t 1 = 1 ns. Furthermore, assuming that resistors 1331 and 1332 are disregarded and inductors 1321 and 1322 are L = 5 nH, the power supply noise v _{n is} through

given.

Such a high power supply noise is at a modern semiconductor integrated circuit, which at operated with a supply voltage of 5 volts or less is not permitted.

Even if the noise can be reduced to an appropriate level, the times t 1 and t 2 are necessary to eliminate the power supply noise and the ground potential noise, as shown in Fig. 24 (B). This time depends on the current switching time and is normally 103 ns. Such a period of time is unacceptable for an ultra high-speed memory that requires an access time of less than a few nanoseconds and is a major obstacle to high-speed operation.

The one that occurs when the supply current changes Problem can be found on a variety of arithmetic logic units in a semiconductor chip and on others Apply functional circuit blocks.

In recently developed high-performance microprocessors Various techniques have been introduced to their Increase processing performance. The processing power the computer can be rated as follows:

where CPI is the number of commands required Cycles is.

The remarkable one has been around for several years Technology of the RISC processors. A main goal of this Processors are designed to increase the cycle by Approximate inches to one.

At present there are further developments of the RISCs Super scalar and VLIW technology (very long command word) to call. With this technology, up to n commands pulled in parallel, these commands are decoded in parallel and executed in parallel. If you look at parallel processing hardware increases, the number of cycles per Inch reduced to 1 / n in the formula above and the power of the computer increased. In the high speed arithmetic logic circuit of a super scalar or computer VLIW type is a differential logic circuit using bipolar transistors or a circuit with low Amplitude used with the help of BiCMOS; however consumed a circuit that constantly needs a direct current, relatively much electricity.

In super scalar or VLIW microprocessors, n High speed arithmetic logic circuits with the same function required. Therefore, the power consumption increases of arithmetic logic circuits with the Factor n.

The corresponding technology is in NIKKEI Electronics No. 487, Nov. 27, 1989, pages 191-200.

As can be seen from the above description, in the state of the art power saving technology with integrated Semiconductor circuits or electronic Circuits, such as microprocessors, the problem the noise in earth lines or the supply lines, if the power is turned on, disregarded, which causes interference in the circuits or a certain time is required before the noise disappears,  so that a quick start is not possible.

In a microprocessor according to the prior art An on-chip memory is because of the compromise between the noise suppression in the power circuit and the Memory access speed increase difficult, one to achieve very high operating speed.

Microprocessors with cache memory are described above been, however, the problems with integrated Semiconductor circuits or for electronic circuits with a functional block that is a high speed operation requires the same.

It is therefore an object of the invention to provide an integrated Semiconductor circuit and a microprocessor to provide the have a low power consumption and a high one Speed are operated. Another job of Invention is in a functional circuit block an integrated semiconductor circuit has a low power consumption and achieve high speed.

Another object of the invention is to provide a integrated semiconductor circuit and a microprocessor to provide where when electricity becomes a functional Circuit block is switched, is prevented from Noise occurs and they work without interference.

Furthermore, the invention is directed to a low power consumption and high speed a microprocessor that has on-chip memory, such as having a cache.

Another object of the invention is to provide a low power consumption and high speed to achieve a parallel processing microprocessor. The The aforementioned object is achieved according to the invention that a semiconductor integrated circuit or a microprocessor provided with at least one functional block is the beginning of an operation of the functional Circuit blocks detected before the operation begins  functional circuit block where the beginning of the Operation was activated before the operation begins and the functional circuit block after the Operation disabled. Appropriate procedures are also intended to operate the circuits mentioned with low power consumption can be specified.

To provide a predetermined service for the operation of the circuit is necessary are activation means and to deliver less power than that predetermined performance, deactivation means are provided.

The semiconductor integrated circuit of the invention contains a memory, detection means for detecting a Memory access before the memory access match with information related to memory access and means for activating the memory before the memory access, when the detection means detects the memory access to have.

In the invention, the memory can be clock synchronized Storage and there can be means of generation a memory clock signal is provided for clocking the memory be the integrated on a system clock signal Semiconductor circuitry and the access announcement signal are based.

Alternatively, means for generating a Impulse to activate a sense amplifier of the memory be provided on the integrated system clock signal Semiconductor circuitry and the access announcement signal based so that part or all of it Memory sense amplifier by the activation pulse is activated.

In accordance with another feature of the invention, there is provided a functional circuit block having power supply inductance L, an allowable power supply noise V _n, and a circuit current change amplitude Delta I, and means for generating an operation start announcement signal to provide the functional circuit block with a time t before the operation begins activate functional circuit blocks, where T, L, V _n and Delta I of the relationship

correspond.

The microprocessor of the invention is characterized in that that a memory, a first instruction decoder for Decode a command and forward the execution message to the memory, a second instruction decoder for Capture access to memory before the start of Access to generate an access announcement signal and Activation means for the previous activation of the memory are provided depending on the announcement signal.

The second instruction decoder can be designed that it has the access announcement signal at least one stage generated before the execution stage of the memory access, and the activating agents can be designed so that they a driver current of one intended for the memory current level lower than the predetermined operating current level to the predetermined operating current level in one predetermined speed from the time of generation of the Access announcement signal until the start of the Increase memory access execution state.

The microprocessor of the invention has at least one functional circuit block, a first instruction decoder to decode a command and forward execution to the functional circuit block, a second Instruction decoder to detect execution by the functional circuit block before starting execution for generating an operation announcement signal and  Activation agent to activate the functional Circuit blocks before the start of execution due to the Announcement signal.

The memory of the invention has a functional one Circuit block on, which is an announcement signal for the Start of operation receives a circuit current on one predetermined level increases in a predetermined time starts receiving the announcement signal to start from one Operation with low power consumption on operation with normal power consumption switch and after execution the operation, the circuit current in a predetermined Time to cut down on the electricity that is operating at low Power consumption corresponds and lower in operation Switch power consumption, and the memory is through the access announcement signal activates and carries one predetermined storage operation in accordance with a Address signal, a read / write control signal and a data input / output signal out.

The memory has an information processing unit, such as a job or one Computer, the at least one of the semiconductor integrated circuit arrangements, the microprocessor, the functional one Circuit block and memory includes.

The invention will now be described with reference to Drawings explained in more detail; it shows

FIG. 1 is block diagram showing the configuration of a microprocessor according to a first embodiment of the invention;

Fig. 2 instruction execution stage of a microprocessor;

Fig. 3 signal flow diagram of the timing of the operation of the microprocessor;

Fig. 4 (A) block diagram of the configuration of an access announcement signal generator;

Fig. 4 (B) Configuration of a memory access prediction circuit;

Fig. 4 (C) control diagram for the operation of the circuit;

Fig. 5 is block diagram of a configuration of a cache memory;

Fig. 6 (A) Circuit diagram of a current control signal generator;

Fig. 6 (B) signal flow diagram about the operation of the same;

Fig. 7 is waveform diagram showing the relationship between the access announcement signal and a power supply;

Fig. 8 (A) block diagram of the configuration of a current control signal generator;

Fig. 8 (B) signal flow diagram for the operation of the same;

Fig. 9 (A) block diagram of a signal generator for current control;

Fig. 9 (B) signal flow diagram for the operation of the same;

Fig. 10 circuit diagram of an address buffer;

FIG. 11 is block diagram of a peripheral circuit of a memory cell;

Fig. 12 circuit diagram of an output driver;

Fig. 13 command list;

FIG. 14 is block diagram showing the configuration of a microprocessor according to a second embodiment;

Fig. 15 instruction execution stage of the microprocessor of the second embodiment;

Fig. 16 instruction execution stage of the microprocessor in the event of competition;

Fig. 17 circuit in an arithmetic logic unit;

Fig. 18 is another circuit in the arithmetic logic unit;

Fig. 19 is another circuit in the arithmetic logic unit;

Fig. 20 is another circuit in the arithmetic logic unit;

Fig. 21 Rules for combining instructions when two instructions are executed in parallel;

Fig. 22 instruction execution stage for a branch instruction;

Fig. 23 instruction execution stage in a load consuming operation and

Fig. 24 Relationship between the change in circuit current and a noise voltage.

The following is an embodiment of an integrated one Semiconductor circuit of the invention with reference described on a microprocessor.

Fig. 1, the configuration of a microprocessor (MPU) according to a first embodiment of the invention.

Reference numeral 100 denotes a one-chip microprocessor. To simplify the description, only the elements of the internal configuration necessary for understanding the embodiment are shown, the other elements have been omitted.

Reference numeral 101 denotes a program counter which generates a pick-up address of command data in synchronism with a clock signal CLK. Reference numeral 102 denotes a memory address register that holds a fetch address of an instruction cache 103 . Reference numeral 104 denotes an instruction data register which holds the instruction data fetched from the instruction cache 103 .

Numeral 111 designates another address register that holds a read or write address of a data cache 112 , numeral 113 designates a data register that holds read data of the data cache 112 or write data for the data cache 112 .

The command data register 104 and the data register 103 are connected by an internal data bus 172 and exchange data with an external data bus 161 via an input / output controller 160 .

Reference numeral 120 denotes a first instruction decoder, the output 105 of the instruction register 104 decodes and generates instruction control signals 121 and 122 . Reference numeral 140 denotes an arithmetic logic unit which receives the data required for an operation from a register file 150 via an internal bus 73 , which performs the arithmetic, the logical or the shift operation and the operation result via an internal bus 174 into the register file 150 writes. In another case, it writes the operation result to a memory address register 111 via an internal bus 175 .

The output 121 of an instruction decoder 120 identifies the type of operation for the arithmetic logic unit (ALU) 140 . The output 122 of the instruction decoder 120 identifies a read or write operation for the register file 150 .

Reference numeral 130 denotes a second instruction decoder that decodes the output 105 of the command register 104, the data cache 112 predicts the memory access and the data cache 112 provides a memory access notice signal 131st

The data cache 112 performs the predetermined memory access that is based on the memory access announcement signal 131 of the address signal from the memory address register 111 and a read / write control signal (not shown).

The second instruction decoder 130 may have the function to send operation start announcement signals 132 and 133 to the arithmetic logic unit 140 , register file 150 and other units as required.

Fig. 2 shows a typical instruction execution stage of the microprocessor of this embodiment.

Instructions 1 and 2 show an execution stage an R-R operation (register-to-register operation).

In an IF stage (instruction fetch stage), the instruction data is fetched from the instruction cache 103 . In a D stage (instruction decoding stage), they are decoded by the instruction decoder 120 . In an EX stage (instruction execution stage), a predetermined operation is performed by the arithmetic logic unit 140 . Finally, an operation result is written to the register file 150 at a W stage (write stage).

For a load instruction and a store instruction, see FIG. 2 middle, by which access to the data cache 112 is requested, the IF stage and the D stage are the same as the stages of the RR operation. At the next AC stage (address calculation), an effective address is calculated to access data cache 112 . Data cache 112 is accessed at a CA (cache access) state. Finally, in the W stage, the fetched data is written into the register file 150 . As described above, in the load / store instruction, the effective address calculation stage AC is always between the decode stage D and the memory access stage AC. In the present embodiment, the memory access request is predicted at the D stage two stages before the CA stage and the access announcement signal is sent to the cache memory 112 .

Fig. 3 shows the signal flow diagram from the fetch of the command to the generation of the access announcement signal and the access to the memory in more detail.

Reference numeral 3 denotes a system clock CLK. Its period is equal to a stage period of the instruction execution stage of Fig. 3 and may be, for example, 5 ns.

Reference number 3 b denotes the IF stage. The load / store commands M₁ to M₅ are fetched.

Reference number 3 c denotes the D stage, in the stage following the IF stage, the load / store commands M 1 to M 4 are decoded.

Reference number 3 d denotes the AC stage. The effective addresses A₁ to A₅ decoded for the load / store instructions M₁ to M₅ in the D-stage 3 c are calculated.

Reference number 3 e denotes the memory addresses A₁ to A₃, which are calculated in the address calculation. The memory access is actually performed in CA stage 3 f using these addresses.

Reference numeral 3 g denotes the memory access prediction signals M₁ to M₄, which are generated by the second instruction decoder 130 shown in FIG. 1. They are generated due to the decoding of M₁ to M₅ in D stage 3 c.

The reference numeral 3 h denotes the memory access announcement signal ( 3 ), which is generated by the processing of the memory access prediction signals M₁ to M₅ ( 3 g). It is delivered to data cache 112 .

The access announcement signal 3 h is generated a stage before the E 1 stage 3 f, in which the memory is actually accessed, and it is also generated a stage before the E 3 stage.

Fig. 4 (A) shows the internal configuration of the second instruction decoder 130 (see Fig. 1) which generates the memory access announcement signal 131 , Fig. 4 (B) shows the internal configuration of the prediction circuit of the memory access 410 and Fig. 4 (C) shows a signal diagram in the corresponding operation.

Reference numeral 410 designates the memory access prediction circuit which detects whether the command data provided by the command register 104 represents a command that causes the memory access or not. Specifically, as shown in Fig. 4 (B), after the load and store instructions have been detected, a detection signal DET (detection) is generated, as shown by 3 g in Fig. 4 (C). Reference numeral 420 denotes a flip-flop which holds the detection signal DET ( 3 g) on the basis of the clock signal CLK ( 3 a) and, at its output ( 4 a), generates the access announcement signal PR ( 3 h) shown in FIG. 4 (C).

The signal PR 131 of the embodiment is a positive active signal, although its polarity is not essential.

FIG. 5 shows the internal configuration of the data cache 112 (see FIG. 1).

Numeral 510 denotes an address buffer that receives an address signal A _i and generates positive and negative address signals requested by an address decoding driver 520 . The output of the address decoding driver 520 is provided to a memory array 530 for selection of a memory array to be read or written.

Numeral 540 denotes a sense amplifier that amplifies a small signal that has been read from the memory array to a given signal level. Reference numeral 550 denotes an output driver which drives an output D₀ which has a relatively high load.

Reference numeral 560 denotes a write control circuit that writes write data D _i into a predetermined address of the memory array 530 by a write control signal.

Reference numeral 570 denotes a current control signal generator which receives the access announcement signal PR for generating at least one current control signal 575 . In the exemplary embodiment, assuming that the data cache 112 is being used proportionally or that an access request other than the command execution is taking place, a plurality of announcement signals PR 1,... Are generated to generate at least one current control signal 575 . . . PR _n .

Control of the circuit current by the current control signal 575 is applicable to all circuit elements except the current control signal generator 570 in the cache 112 . The selection of the circuit to be controlled depends on the configuration and application of the hardware that can actually be used.

Fig. 6 (A) shows the configuration of the current control signal generator (see Fig. 5) and Fig. 6 (B) shows a signal diagram of the generator.

Reference numeral 610 denotes an OR gate for ORing the access announcement signals PR₁ to PR _n , the output of which is at an inverter 620 and a flip-flop 660 . Reference numeral 630 designates a NOR gate for OR-NOT linking the output of the inverter 620 and the output of the flip-flop 660 to generate a signal PUMP as shown at 6 c in Fig. 6 (B).

Reference numeral 640 denotes an AND gate for ANDing the O output 6 b of the flip-flop 660 and the clock signal CLK 3 a for generating a signal MCLK 6 d as shown in Fig. 6 (B). Reference numerals 650 and 670 denote an OR gate and a delay circuit, respectively. The OR gate 650 is used to combine the MCLK signal 6 d and the MCLK signal delayed by the delay circuit 670 by a predetermined time and generates a signal Phi SA as shown in Fig. 6 (B).

MA 6 e in Fig. 6 (B) shows a memory address in the memory access execution cycle.

As shown in Fig. 6 (B), the memory access to the memory addresses A₁ and A₂ takes place in the clock stages t₁ and t₃ ( 6 g). On the other hand, the PUMP signal 6 c rises in stage t 1, which is a stage before stage t 2, and falls off at the end of stage t 3.

The circuit current is controlled based on the PUMP signal 6 c. This is shown in FIG. 7. As 7 a in Fig. 7 shows, the current of the controlled circuit is increased from i₁ to a predetermined current i₂ in accordance with the PUMP signal 6 c and the current level is maintained in the t₂ and t₃ memory access stages and from the beginning of t₄ stage in which the memory access has been performed, lowered to a low current level i₁.

The MCLK signal 6 d ( Fig. 6 (B)) is a pulse signal which is generated in the memory access stages t₂ and t₃, and is used in a clock-synchronized memory as a memory clock. The clock-synchronized memory is described in the following publications:

• 1) Kevin J. O'Connor, Modular Embedded Cache Memory for a 32b Pipelined RISC Microprocessor, 1987 IS SCCC, pp. 256-257.
• 2) Masanori Odaka et al. a., A512 kb / rns BiCMOS RAM With 1 KG / 150 ps Logic Gate Array, 1989, IS SCC, pp. 28-29.
• 3) Masayoshi Kimoto et al. a., A 1.4 ns / 64 kb RAM With 85 ps / 3688 Logic Gate Array, 1988 CI CC, pp. 15.8.1-15.8.4.

The Phi-SA signal 6 f is generated in the memory access stages t₂ and t₃ and serves only for a predetermined period as a signal to activate the sense amplifier.

If the activation of the The sense amplifier is caused by the current switching Power supply noise within an acceptable range and can serve as a signal to minimize the Activation time of the sense amplifier, which is high Power consumption has to be used.

An example of circuit current control by the PUMP signal and the Phi-SA signal is described below.

Fig. 8 (A) shows a first example of the circuit that controls the circuit current through the PUMP signal, and Fig. 8 (B) shows operation pulse waveforms.

Reference numerals 811 and 812 denote pMOS, the source of which is connected to a power supply V 1 and the gate of which is connected to one another and to the sink of a pMOS 811 . Reference numerals 821, 822 and 823 denote nMOS. The sink of the nMOS 821 is connected to the sink of the pMOS 811 , at the gate of which the PUMP signal is present and the source of which is connected to a reference potential.

The sink of the nMOS 822 is identical to the sink of the pMOS 812 ; its gate is connected to the output of an inverter 830 and its source is connected to the reference potential. The input of inverter 830 is connected to the PUMP signal.

Reference numeral 840 denotes an active circuit such as a differential amplifier. It is provided in a functional circuit block, such as data cache 112 , arithmetic logic unit 140 or register file 150 (see FIG. 1). A predetermined operational current is supplied from a constant current source 850 through the nMOS 823 . A connection is established through the gate of the nMOS 823 and the ground GND with the integration capacitor C.

The pMOS 811 and 812 , the nMOS 821 and 823 form a current mirror circuit. As shown in Fig. 8 (B), when the PUMP signal rises from level 0 to 1, a predetermined charge current flows from the pMOS 812 to the capacitor C, and the gate voltage Vg of the nMOS 823 and the current i of the circuit 840 rise slightly to predetermined ones Tracking speeds on (change speeds per unit time) as shown in Fig. 8 (B) middle and below. The rise time t 1 corresponds to the stage t 1, as shown in FIG. 7.

Likewise, when the PUMP signal changes from level 1 to level 0, voltage Vg and current i drop slightly at a predetermined tracking rate. The fall time t₄ corresponds to the stage t₄, as shown in FIG. 7. The rise time t₁ and the fall time t₄ of the current i are not necessarily the same. The fall time t₄ can be short in an intolerable range because the switching operation has been stopped.

Fig. 9 (A) shows a second example of the circuit for controlling the circuit current using the PUMP signal, and Fig. 9 (B) shows operation pulse waveforms.

Reference numerals 911 to 914 denote inverters, reference numerals 921 to 923 denote nMOS. Reference numerals 931 to 933 denote constant current sources and reference numeral 940 denotes an active circuit, such as a differential amplifier, which is provided in a functional circuit block such as, for example, the data cache memory 112 of the arithmetic logic unit 140 or the register file 150 (see FIG. 1 ).

The delay times of the inverters 912 to 914 are selected so that they increase in the order 914, 913, 912 . Thus, when the PUMP signal changes from 0 to 1, as shown in FIG. 9 (B), the currents i 1 to i 3 flowing in the nMOS 921 to 923 increase with a predetermined time delay and the operating current of the active circuit 940 gradually increases after that Duration t₁ to a constant stage current i₁ + i₂ + i₃.

Likewise, when the PUMP signal 1 changes to 0, the circuit current 940 gradually drops in time t₄. That means, similar to the embodiment of FIG. 8, a smooth current change is achieved.

The rise time t₁ and the fall time t₂ correspond to the stage t₁ or the stage t₄ of FIG. 7, as is the case in the first embodiment.

In the above-described embodiments the circuit current using the PUMP signal and the Phi-SA signal controlled. The circuit current can alternatively can also be controlled by other common methods.

For the first circuit current control circuit, an example of the circuit current control in data cache 112 is illustrated (see FIG. 1).

FIG. 10 shows one embodiment of the current control for the address buffer 510 in FIG. 5 of the data cache 112 .

The reference numerals 1011 to 1014 denote npn transistors, the reference numerals 1021 and 1022 denote resistors, the reference numerals 1031 to 1033 denote nMOS and the reference numerals 1041 to 1043 denote constant current sources.

The emitters of the npn transistors 1011 and 1012 are connected to one another and to the constant current source 1041 via the nMOS 1031 . The bases of the npn transistors 1011 and 1012 are connected to an address signal A _i or a reference potential V _R and their collectors are connected to a power supply V 1 via the resistors 1021 and 1022 . The collectors of the npn transistors 1013 and 1014 are connected to the power supply V₁ and their bases are connected to the collector of the npn transistor 1011 and the collector of the npn transistor 1012 . The emitters of the npn transistors 1013 and 1014 are connected to the constant current sources 1042 and 1043 via the nMOS 1032 and 1033, respectively.

The output a _i is taken at the emitter of the npn transistor 1014 as the non-inverted output of the input i and the output is taken at the emitter of the npn transistor 1013 as the inverted output of the input A _i . The gates of the nMOS 1031 to 1033 are connected in common to the control signal Vg, which corresponds to the signal Vg shown in FIG. 8.

The NPN transistors 1011 and 1011 , the resistors 1021 and 1022 and the constant current source 1041 form a differential amplifier. When the current control signal Vg is at level 1 and the address signal A _{i is} higher than Vg, the npn transistor 1011 turns on, the npn transistor 1012 turns off, the collector of the npn transistor 1011 is at the level 0 and The collector of the npn transistor 1012 is at level 1.

The collector of the NPN transistor 1011 is connected to the base of the emitter follower transistor 1013 , which produces the 0-level output at its emitter. In the same way, the collector of the npn transistor 1012 is connected to the base of the emitter follower transistor 1014 , which generates the 1-level output a _i at its emitter.

If the address signal A _{i is} lower than V _R , the npn transistor 1011 and the npn transistor 1012 operate in opposite directions, so that the output is at level 1 and the a _i output is at level 0.

When the current control signal Vg is at level 0, all nMOS 1031 to 1033 are turned off. Since there is no current path from the power supply V 1 to the ground GND, the circuit does not consume any current.

Because the current control signal Vg shown the predetermined rise and fall times, as shown in Fig. 8 (B), comprising, a gentle stream of waste takes place as a point 7 in FIG. 7 shows.

Therefore, the power supply and ground noise (see Fig. 24 (B)) that occur when the power is switched can be suppressed to a desired level.

Fig. 11 shows an example of the current control circuit for the driver of the decoder 520, the memory array 530 and the sense amplifier 540 shows (s. Fig. 5) in the data cache memory.

Reference numerals 1161 and 1162 denote NOR gates which correspond to the end stage of the address decoder.

Reference numerals 1171 and 1172 denote a word driver that contains AND gates. The outputs of the address decoders 1161 and 1162 are connected to one input, the control signal Vg is connected to the other input and the word lines WL 1 and WL 2 are operated by its output.

Reference numeral 1100 denotes a 4-MOS memory cell, but is not limited to this. Only one cell is shown for clarity.

Reference numerals 1111 and 1112 denote load MOS for pulling up bit lines. Reference numerals 1113 to 1116 denote MOS switches for selecting the bit lines. A desired bit line is connected to a common data line 1120 by the column selection signals C₁ and C₂.

Reference numerals 1121 and 1122 denote emitter follower circuits containing npn transistors. With the help of the V _BE (base-emitter voltage), they push the signal level over the common data line 1120 and deliver it to the base of the npn transistor 1123 or 1124 . The emitters of the NPN transistors 1123 and 1124 are connected to one another and to a current source 1151 via an nMOS 1141 . Collectors of the NPN transistors 1123 and 1124 are connected to the power supply V 1 through the resistors 1131 and 1132 .

The NPN transistors 1123, 1124 , the resistors 1131, 1132 and the current source 1151 form a differential amplifier which amplifies a small signal which is read out from the memory cell 1100 to a predetermined level. Likewise, reference numeral 1150 denotes a differential amplifier, which is connected to two resistors and two npn transistors and via an nMOS 1142 to a constant current source 1152 .

Two inputs of amplifier 1150 are connected to the collectors of NPN transistors 1123 and 1124 . The signals to be delivered there are amplified at a terminal 1151 to generate an output signal with a predetermined amplitude.

The current control signal Vg (see FIG. 8) is connected to an input of the AND gates 1171 and 1172 , respectively. When Vg is 1, the AND gates 1171 and 1172 are selectively driven to selectively drive the word lines WL 1 and WL 2. On the other hand, when Vg is 0, the word drivers including AND gates 1171 and 1172 are turned off. Accordingly, the currents flowing in the memory cells including the memory cell 1000 are blocked. Therefore, if the memory is not accessed, unnecessary power consumption is avoided.

Likewise, the current control signal Vg is connected to the gates of the nMOS 1141 and 1142 . When Vg is at level 1, nMOS 1141 and 1142 are turned on and when Vg is at level 1 they are turned off.

Therefore, if the memory does not flow is accessed, no current in the sense amplifier and unnecessary Power consumption is avoided.

Numeral 7 a in Fig. 7, the change in the circuit current indicated by the current control signal Vg. Therefore, it can reduce the by switching the current caused power supply and ground noise to an acceptable level, and because the start time of the memory access is no noise, a high speed operation be achieved.

In Fig. 11, when the switch SW is switched to the position of the signal Phi SA 1180, the nMOS 1141 and 1142 are turned on for a short period. As described above, the signal Phi SA is a pulse signal which assumes level 1 only for the predetermined time of the memory access stages t₂ and t₃. In the exemplary embodiment, it supplies the current to the sense amplifier only for the time in which the memory is being accessed. Therefore, electricity can be saved.

FIG. 12 shows an example of the current control signal for the output driver 550 (see FIG. 5) of the data cache 112 .

Sink, gate and source of a pMOS 1211 are connected to the base of an npn transistor 1142 , the input V _IN and the power supply V₁. Sink, gate and source of an nMOS 1221 are connected to the base of the npn transistor 1241 , the input V _one and one end of a resistor 1251 , respectively. The sink, gate and source of a pMOS 1222 are connected to the sink of the nMOS 1221 , a current control signal Vg and the base of the npn transistor 1241 , respectively. A capacitor 1261 is connected through resistor 1251 . Anode and cathode of a diode 1231 are connected to the collector and the base of the npn transistor 1241 and the power supply V₁ is connected to the collector of the npn transistor 1241 . The emitter of the npn transistor 1241 is an output terminal and a terminating resistor 1252 is connected via the output terminal and the power supply V₂.

When the current control signal Vg is at level 1, the pMOS 1222 is turned off. When the input V is _a at the 0 level, the pMOS is turned off 1211 and the nMOS 1221. Therefore, the base voltage of the npn transistor 1241 is increased via the pMOS 1211 and the output V _out assumes level 1. If V is _a 1 on the level, the PMOS 1211 is turned off and the nMOS 1221 is turned on. Therefore, the base voltage of the npn transistor 1241 drops and the output V _out assumes the level 0.

The diode 1231 serves as a clamp to suppress the drop in the base potential of the npn transistor 1241 within a predetermined level.

Resistor 1251 is a current limiting resistor and capacitor 1261 is an accelerating capacitor.

When Vg is at level 0, pMOS 1222 turns on. The base potential of the NPN transistor 1241 drops without regard to the level of the input V _a decreases so that the output V _from the level assumes 0th

In this way, the same effect as in the circuit current controls for the address buffer 510 , the decoding driver 520 , the memory array 530 and the sense amplifier 540 is achieved.

The circuit current control in data cache 112 (see FIG. 1) has been described above for the first circuit current control, although the second circuit current control (see FIG. 9) or other circuit current control may also be used.

In the exemplary embodiment, a reduction in Described the power consumption when accessing the memory, who uses the access announcement signal. The The idea of the invention is equally functional Circuit applicable, the operation of which by decoding the Command word is controlled, such as a Arithmetic logic unit in a one-chip microprocessor or a register file. In the exemplary embodiment, the Switching current in synchronism with the stage before the Execution stage of the operation. A synchronization is not always necessary, however, the increase before Start of execution stage started up to a time to reduce power and ground noise, that occurs when the current changes, to one predetermined level is sufficient. In this case instead of synchronizing with the stage prior to Execution stage is, the PUMP signal to a desired Effective date.

In the exemplary embodiment, the current for the Memory circuit and the other functional circuit in the One-chip microprocessor before starting the operation the access announcement signal that precedes the actual Operation of the circuit is generated to the predetermined Speed. Therefore, the functional consume Circuits that are required for circuit performance Electricity only during actual operation. Hence the Power consumption of the one-chip microprocessor reduced.

Because thanks to the fact that electricity is saved, one new function can be introduced becomes functional high quality and highly integrated arrangement achieved.

Because the circuit current of the functional circuit can be changed at a predetermined speed the power supply and ground line noise that at the current change occurs up to the predetermined level  be lowered. It will therefore be a highly reliable one Switching operation achieved.

In the functional circuit according to the execution Examples are the power supply noise and the earth noise at the time the actual Operating disappeared, the circuit can be among the best Current conditions are operated and works with a high speed.

The following is the use of the invention in a super scalar RISC processor explained.

There are a lot in the Super Scalar RISC processor of arithmetic logic units, which is a register file share, provided and the commands are simplified to the Reduce number of pipeline stages and a variety of commands is used to control the variety of arithmetic Logic units fetched in one machine cycle. It will namely a variety of commands during a machine fetched and executed in parallel and a variety of Arithmetic logic units will increase the processing processing power operated in parallel.

Fig. 13 shows a list of instructions of a processor described in the second embodiment. The instructions are divided into basic instructions, branch instructions, load / store instructions and system control instructions. For convenience and simplicity, the number of commands has been limited, although more commands can be used.

Fig. 14 shows the configuration of the second embodiment. Numeral 1400 denotes the memory interface, numeral 1401 denotes a data cache, 1402 denotes a sequencer, 1403 denotes an instruction cache, 1404 denotes a first 32-bit instruction register, 1405 denotes a second 32-bit instruction register, 1406 denotes one first decoder for a first instruction, reference numeral 1408 denotes a first decoder for the second instruction, reference numeral 1409 denotes a second decoder for a second instruction and reference numeral 1407 denotes a second decoder for the first instruction. The first and second decoders 1408 and 1409 may have the same function as the second instruction decoder 130 described in the first embodiment ( FIG. 1), namely the function of generating the start announcement signal, the signal for the operation of the functional circuit block, though that was not described here. Reference numeral 1413 denotes a competition detector for detecting a competition between the first and second commands, reference numeral 1410 denotes a first arithmetic logic unit, reference numeral 1412 denotes a second arithmetic logic unit, and reference numeral 1411 denotes a register file. In the exemplary embodiment, up to two commands are fetched and executed in parallel in one machine cycle. A most basic operation of the pipeline processing of the embodiment is shown in Fig. 15. The pipeline contains five stages: IF (fetch instructions), D (decode), EX (execute), T (test) and W (write).

The operation will be explained with reference to FIG. 14. At the IF stage, two instructions, identified by a program counter in sequencer 1402 , are fetched from instruction cache 1403 and inserted into first instruction register 1404 and second instruction register 1405 via buses 1415 and 1417, respectively.

In the D stage, the content of the first instruction register 1404 is decoded by the first decoder 1406 and the content of the second instruction decoder 1405 is decoded by the second decoder 1407 . The content of the register identified by the first source register field of the first command register 1404 is then sent to the first arithmetic logic unit 1410 by a bus 1425, and the content of the register identified by the second source register field is sent to the first arithmetic logic logic via a bus 1426. Unit 1410 sent. The contents of the register identified by the first source register of the second instruction register and the contents of the register identified by the second source register field are sent to the second arithmetic logic unit 1412 via a bus 1427 and a bus 1428, respectively.

The operation of the EX stage is explained below. In the EX stage, the first arithmetic logic unit 1410 processes the data sent over the buses 1425 and 1426 in accordance with the operation code of the first instruction register. In parallel, the second arithmetic logic unit 1412 processes the data that was sent via the buses 1427 and 1428 in accordance with the operation code of the second instruction register 1405 . The address calculation for the load / store command is carried out.

Operation in the T stage is explained below. In the T stage, the basic information continues to hold the data. At this stage, the load / store instruction performs memory access to data cache 1401 based on the address calculated in the previous EX stage and provided by bus 1429 or bus 1431 . The data to be stored simultaneously for the store command is provided via bus 1437 .

Finally, the operation in the W stage is explained. In the W stage, the operation result of the first arithmetic logic unit 1410 is stored via the bus 1429 in the register identified by the destination field of the first command register. The operation result of the second arithmetic logic unit 1412 is stored via the bus 1431 in the register identified by the identification field of the second command register. For the load command, it is stored via bus 1430 in the register identified by the determination field in the load command.

Fig. 15 shows a sequential execution flow of the basic commands. Two commands are executed in one machine cycle. In the example, the first arithmetic logic unit and the second arithmetic logic unit always work in parallel.

However, depending on the combination of the first command and the second instruction a case occur in which both instructions can not run in parallel, which then competition is called.

For example, a competition takes place when that through the destination register field of the first instruction designated register and that by the first source register field of the second instruction or the register designated by designated the second register field of the second instruction Registers are the same.

When such competition occurs, the hardware is controlled to execute the instruction stored in the first instruction register in one machine cycle and the instruction stored in the second instruction register in the next machine cycle. This means that the first command or the second command are executed in one machine cycle. Fig. 16 shows a pipeline during a competition. In the example, both the first and the second command are ADD commands. The following applies to both commands at address 2 : the contents of register R ( 1 ) of register R ( 2 ) must be added to the first command, after which the sum is stored in register R ( 3 ); add the contents of register R ( 4 ) and register R ( 3 ) to the second command, after which the sum is stored in register R ( 5 ). The destination register R ( 3 ) of the first instruction competes with the source register R ( 3 ) of the second instruction. In such a case, an instruction is executed in one machine cycle, as shown in FIG. 16.

Namely, the first command is executed and the parallel second command is invalidated in PC 2 . In the next cycle, the first command is invalidated and the parallel second command is executed. The competition that occurs between destination and source when the executions are staggered by one cycle can be decided by a known short route.

As shown in Fig. 14, the super-scalar RISC processor has two arithmetic logic units. Only one arithmetic logic unit can be used in a competition, the other arithmetic logic unit operates in a non-significant manner.

When competition is detected in the super-scalar RISC processor, it is important to activate one of the arithmetic logic units to be used before starting the operation. This will be explained with reference to FIG. 14. After the first command and the second command are fetched at the IF stage, competition between the first and second commands is controlled by the command capture 1413 at the D stage.

If a competition has been detected in the competition control, only one arithmetic logic unit is operated. Therefore, the unit to be used is activated by signals 1432 and 1433 .

If no competition occurs, both arithmetic logic units activated. If a control signal for the next machine cycle during the last half of the informed about the activation of the current machine cycle, the activated arithmetic logic unit remains activated. If the control signal does not indicate activation, the arithmetic logic unit at the end of the deactivated machine cycle.

The operation in the event of a competition is explained in detail below. When the competition detector detects competition between the first and second commands, the first arithmetic logic unit is informed of activation via bus 1433 by control signal 1435 so that it can execute the first command first and it is activated. At the same time, the second arithmetic logic unit is informed about the non-activation via the bus 1432 by the control signal 1436 . In this way, the second arithmetic logic unit is kept deactivated, that is, it is in the state of low power consumption.

Signal 1434 informs sequencer 1402 of the detection of the competition.

In the next cycle, the first arithmetic logic unit is informed of the non-activation via the bus 1433 by the control signal 1435 so that the second command can be executed. This deactivates the first arithmetic logic unit. At the same time, the second arithmetic logic unit is informed about the activation via the bus 1432 by the control signal 1436 .

In the present embodiment, when the Competition in the parallel execution system for two commands was detected, the arithmetic logic unit to be used detected and activated before the start of the operation, so that the deactivated arithmetic logic unit at the stage remains low power consumption and the total power consumption is kept low.

Figs. 17 to 19, the first arithmetic logic unit indicate 1410, the second arithmetic logic unit 1412 and the register file 1411 of FIG. 14. The connections are not shown.

The first and the second arithmetic logic unit in FIG. 17 uses at least one differential input circuit, for example an ECL circuit. When the competition is sensed in the super scalar microprocessor having such an arithmetic logic unit, one instruction is executed in one machine cycle. Thus, the first or second arithmetic logic unit that is actually operated is activated by signal line 1435 or 1436 and a predetermined current flows from the current source to enable the operation, but is in the remaining deactivated arithmetic logic unit the current from the power source is reduced or blocked. In this way, power consumption is reduced.

In Figs. 18, 19 and 20 have the first and the second arithmetic logic unit is a base-emitter logic circuit with at least one bipolar transistor, for example an ECL circuit or a BiMOS circuit. The circuit configuration is shown in detail in JP-A-60-1 75 167. This circuit has the disadvantage that a direct current flows and that the current consumption increases when the bipolar transistor conducts. It is therefore effective to block the power consumption of the non-operated arithmetic logic unit when the competition occurs. The control method may be the same as the method shown in FIG. 17.

FIGS. 18 and 19 are different with respect to the power saving method. In Fig. 18, a p-channel MOS is inserted between the collector of a bipolar transistor and Vcc. The circuit is activated when the p-channel MOS transistor is switched on and deactivated when it is switched off.

Referring to FIG. 19, the circuit is held in the operation state. However, when a signal 1435 or 1436 is switched, a bipolar transistor is forcibly turned on to block the collector-emitter current of the bipolar transistor. This means the inevitable blocking of the direct current. This saves electricity.

FIG. 20 shows the first arithmetic logic unit 1410 , the second arithmetic logic unit 1412 , the register file 1411 and the clock distribution circuit of FIG. 14. Furthermore, reference is made to the clock driver in the distribution circuit of FIG. 20.

The clock driver A delivers the clock independently only to the first arithmetic logic unit 1410 , to the register file 1411 and to the second arithmetic logic unit 1412 . In the super-scalar microprocessor with the arithmetic logic units, which contains such a distribution circuit, the instructions, when the competition is detected, are each executed in one machine cycle. The first or second arithmetic logic unit, which is not in use at the moment, controls the interruption of clock forwarding via signal lines 1435 and 1436 to a specific area of the clock distribution circuit. This means that the logic circuits are fixed below the clock distribution circuit. The clock is delivered to one of the two arithmetic logic units, which then works. However, the clock is not delivered to the other arithmetic logic unit.

The CMOS circuit or the basic BiMOS circuit has a complementary characteristic, the normal power consumption is very low, but power is consumed during a transition period when the data input changes. If no clock is supplied, it means that the logic circuits are fixed and do not change. Electricity can therefore be saved. The control method of Fig. 20 is effective for the arithmetic logic unit including the CMOS circuit or the basic BiMOS circuit.

As described in connection with FIGS. 17 to 20, in the deactivated mode current can be saved in accordance with the circuit configuration of the arithmetic logic unit. It can also be seen that power can be saved in the configuration of the arithmetic logic unit, which is a combination of the circuits of Figures 17 and 18.

In the present exemplary embodiment, the competition between the registers was described. Another competition is possible in a case where the parallel execution is suppressed by a combination of commands (for example, a combination of the load command and the load command). An example of this combination is shown in FIG. 21. However, such a combination is determined by the implementation of the hardware and has no direct connection to the invention. In Fig. 21, if there is a limitation on one or more combinations, it is said that the combination of commands has caused competition.

Another operation of the competition detector 1413 and the decoders 1406 , 1408 , 1409 and 1407 as a third embodiment will now be explained with reference to FIG. 14.

In the previous embodiments, when the competition is sensed, the arithmetic logic unit to be operated was sensed and activated before the start of the operation. In the third embodiment, when the competition is detected, the arithmetic logic unit not to be operated is detected and deactivated before the operation is started. This is explained in detail with reference to FIG. 14. After the first and second commands are fetched at the IF stage, competition between the first and second commands is controlled by the competition detector 1413 at the D stage. When the competition is detected, only one arithmetic logic unit executes the command and the remaining arithmetic logic unit can be deactivated by signal 1432 or 1433 . Namely, when the competition detector detects competition between the first and second instructions, the first instruction is executed first and the second instruction invalidates the first decoder of the second instruction by signal 1432 and deactivates the second arithmetic logic unit by control signal 1436 . Signal 1434 informs sequencer 1402 of the detection of the competition. In the next cycle, the first decoder of the first instruction is invalidated by the competition detector output 1433 and the first arithmetic logic unit is deactivated by the control signal 1435 . The second command is executed in parallel. The deactivated arithmetic logic unit is reactivated in the last half of the machine cycle so that it can execute the following command.

According to this embodiment, in the two parallel instruction execution systems any competition between two commands that can be executed in parallel checked and when it is detected, the arithmetic logic unit, which is not in operation, deactivated so that the total power consumption is reduced.

Figs. 17 to 19, the first arithmetic logic unit indicate 1410, the second arithmetic logic unit 1412 and the register file 1411 of FIG. 14. The compounds were omitted. The power saving method of the arithmetic logic units is the same as the method of the second embodiment.

In the super scalar microprocessor with such arithmetic logic units, once the competition is detected, one instruction is executed per machine cycle, and in the first or the second arithmetic logic unit, which is not currently operating, is used with the help of signal 1435 or 1436 electricity saved. In the first or second arithmetic logic unit that is actually operated, the current required for the function to be performed flows from the current source. Therefore, the predetermined current flows through one of the units while saving electricity in the other unit.

It is therefore apparent that in the arithmetic logic unit, which is a combination of the circuits of FIGS. 17 and 18, as in the second embodiment, power is also saved in this embodiment. In this embodiment, the competition between the registers was described. Another contest may concern a case where parallel execution is blocked by a combination of instructions (a combination of the load instruction and the load instruction) as described in the second embodiment. Fig. 21 shows an example of this combination. However, this combination is determined by the implementation of the hardware and is not directly related to the invention, as already mentioned in the second embodiment. As shown in Fig. 21, if there is a restriction on one or more combinations, it means that the competition has taken place through the combination of commands.

In this embodiment, the combination of basic instructions has been described. The arithmetic logic unit can also operate in a non-significant manner when using data loaded by an instruction immediately following a branch or load instruction. (This is called load usage). The invention can also be used effectively in such a case. Fig. 22 shows an example of a branch instruction and Fig. 23 shows an example of the load use. The operation is easy to understand, which is why no further explanation is given here.

If a command where the arithmetic logic unit is not actually operated, such as a NOP instruction or a system control command is detected, the Arithmetic logic circuit deactivated for the detected command will.

In Fig. 14, the second decoder 1408 for the first command and the second decoder 1409 for the second command decode the commands to determine whether the commands require actual operation of the arithmetic logic units.

If that was detected by the second decoder 1408 for the first instruction, the first arithmetic logic unit 1410 is deactivated by the signal line 1435 and if this was detected by the second decoder 1409 for the second instruction, the second arithmetic logic Unit 1412 deactivated via signal line 1436 . This saves electricity in the arithmetic logic units.

In this embodiment, the super scalar microprocessor described for two commands. However, the Invention equally effective in other control systems of the Super scalars and in a processor with a parallel processing function for multiple commands as opposed to Processing of two commands can be used. The Invention is not only in the RISC processor but also applicable to a CISC processor.

In this embodiment, the one-chip microprocessor described. Integrated in another Semiconductor circuit arrangement, such as a one-chip LSI, can be predicted by the start of surgery a functional circuit block and through Control the circuit current of the functional circuit block achieve a similar effect. In this case depends on the procedure for predicting the start of surgery and the time control for switching current control from the Configuration and use of the arrangement. Thereby, that the start of surgery before the start of surgery is predicted and the functional circuit block before the beginning of the operation to avoid malfunctions, caused by switching the current activated, it is ensured that electricity is saved and that normal operation is ensured and that high Operating speed of the arrangement is achieved, which in Agreement with the essence of the embodiment. The embodiment is not only on the integrated Semiconductor circuit, but also to conventional electronic circuits applicable.

According to the invention, the semiconductor integrated circuit arrangement, especially the microprocessor that a one-chip memory, such as a cache memory, contains a low power consumption of the  functional circuit blocks and high speed operation enables, guarantees.

Claims (22)

1. A method for controlling the power consumption in an integrated semiconductor circuit arrangement and a microprocessor with at least one functional circuit block, which comprises the following steps:
Detecting the start of operation of the functional circuit block before it starts operating,
Activation of the functional circuit block for which the start of operation has been detected before the start of operation,
Deactivation of the functional circuit block after its operation has ended. 2. Integrated semiconductor circuit arrangement with a memory,
Detection means for detecting the memory access before the memory access on the basis of information relating to the memory access and
Means for activating the memory before the memory access when the detection means detect the memory access. 3. Integrated semiconductor circuit arrangement according to Claim 2, characterized in that the detection means a load / store command to capture. 4. microprocessor with
a memory ( 112, 150 ),
an arithmetic logic unit ( 140 ),
a first decoder ( 120 ) for decoding a command and for forwarding the command execution to the memory or the arithmetic logic unit ( 140 ),
a second instruction decoder ( 130 ) for detecting access to the memory before the start of the access to generate an access announcement signal and
Activation means ( 570 ) for the previous activation of the memory depending on the announcement signal. 5. Microprocessor according to claim 4, characterized in that the second instruction decoder ( 130 ) generates the access announcement signal at least one stage before an execution stage of the memory access. 6. Microprocessor according to claim 4, characterized in that the activation means ( 570 ) with a predetermined rate of change the operating current of the memory from a current level which is lower than a predetermined operating current level, to the predetermined operating current level from the time of the occurrence of the access announcement signal until the time of Increase the start of memory operation. 7. microprocessor with
at least one functional circuit block ( 112, 150, 140 ),
a first instruction decoder ( 120 ) for decoding an instruction and notifying the functional circuit block of the execution of the instruction,
a second instruction decoder ( 130 ) for detecting execution of the functional circuit block prior to the start of execution and providing an operation announcement signal to the functional circuit block at which execution has been detected and
Activation means ( 570 ) for activating the functional circuit block before execution. 8. Integrated semiconductor circuit arrangement according to claim 2, characterized in that the memory ( 112, 150 ) is a clock-synchronized memory. 9. Integrated semiconductor circuit arrangement according to Claim 8 with Means for generating a memory clock signal for the operation of the memory based on a system clock signal semiconductor integrated circuit device and the access announcement signal are based. 10. Integrated semiconductor circuit arrangement according to Claim 8 with Means for generating a pulse for activation a sense amplifier of the memory based on a system clock signal the integrated semiconductor circuit arrangement and based on the access announcement signal. 11. Integrated semiconductor circuit arrangement with a functional circuit block, which has a power supply line inductance L, a permissible power supply noise V _n and a circuit current change amplitude Delta I, and means for generating an operation announcement signal for activating the functional circuit block at a time T before the start of operation, where T, L, V _n and Delta I of the relationship correspond. 12. Method for controlling the power consumption of a functional circuit block, comprising the steps:
Receiving an announcement signal from the start of the operation of the functional circuit block before the start of the operation,
Increasing the circuit current of the functional circuit block to a predetermined level in a predetermined time, starting from the time of receiving the announcement signal, to change from a low power consumption state to the operating state,
Performing the operation of the functional circuit block in the operating state and
Lowering the circuit current to the low power operation in a predetermined time after completion of the execution of the operation of the functional circuit block to change to the low power state. 13. memory ( 112, 150 ) with
a memory field ( 530 ),
an address decoder ( 520 ) for selecting the address field as a function of an address signal for selecting the address field,
a sense amplifier ( 540 ) for amplifying a low level signal read from the memory array to a predetermined signal level and
a current control signal generator ( 570 ) for generating a current control signal to increase the circuit current of the memory array, an address decoder or the sense amplifier to a predetermined level in a predetermined time in response to an access announcement signal for the read array. 14. The memory of claim 13, characterized in that the current control signal generator ( 570 ) includes means for generating a control signal to the circuit current of the memory array, the address decoder or the sense amplifier in a predetermined time after the operation of the memory array of the address decoder or the sense amplifier to a predetermined level. 15. Information processing unit with
at least one integrated semiconductor circuit arrangement according to claim 2,
the microprocessor according to claim 4,
the functional circuit block according to claim 9, and
the memory of claim 13. 16. Microprocessor for the parallel provision and decoding of n (n 2) instructions and for the parallel execution of n instructions by n arithmetic logic units with detection means ( 1408, 1409 ) for the previous detection of an instruction for the arithmetic logic unit and means ( 1435, 1436 ) for activating at least one arithmetic logic unit for which the command was acquired by the detection means before the operation was carried out, and for deactivating the activated arithmetic logic unit after the operation was completed. 17. Microprocessor according to claim 16 with means ( 1413 ) for detecting a competition between the instructions to be executed in parallel, characterized in that, when the competition has been detected, a signal is sent to the detection means so that one of the arithmetic Logic units are activated according to the instructions to be executed before the operation is carried out, and the other arithmetic logic circuits are deactivated. 18. Microprocessor for the parallel provision and decoding of n (n 2) instructions and for the parallel execution of n instructions by n arithmetic logic units
Means for detecting a competition between the instructions to be executed in parallel,
Means for responding to the detection of the competition which previously acquire the command to the arithmetic logic units from the commands provided before the competition and
Means for activating at least one arithmetic logic unit in accordance with the command and detected by the detection means prior to the execution of the operation
Means for deactivating the activated arithmetic logic unit after completion of the operation. 19. A microprocessor containing means for providing and decoding n (n 2) instructions in parallel and for executing n instructions in parallel by n arithmetic logic units and for detecting a competition between the instructions to be executed in parallel and means for executing the subsequent instructions including competition of the instructions provided in parallel, the microprocessor comprising:
Means for previously acquiring the instructions for the arithmetic logic units from the preceding instructions, including the competition of the instructions fetched in parallel, if the competition was detected and
Means for activating at least one arithmetic logic unit in accordance with the command and detected by the detection means prior to the execution of the operation
Means for deactivating the activated arithmetic logic unit after completion of the operation. 20. Information processing unit with at least one microprocessor according to claim 18 or 19. 21. Microprocessor containing means for providing and decoding n (n 2) instructions in parallel, for executing n instructions in parallel by n arithmetic logic units and for detecting a competition between the instructions to be executed in parallel and means for executing the pre-competition existing instructions of the instructions provided in parallel and for executing the subsequent instructions including competition of the instructions provided in parallel, the microprocessor comprising:
Means for previously acquiring the instructions for the arithmetic logic units from the pre-competition instructions when the competition is acquired, and
Means for deactivating at least one arithmetic logic unit in accordance with the instruction which was not acquired by the detection means and the subsequent instructions, including competition from the instructions provided in parallel, and
Means for deactivating the activated arithmetic logic unit before the end of the operation. 22. A microprocessor according to claim 18, 19 or 21, characterized in that the acquisition means for acquiring the command for the  Arithmetic logic unit do not acquire a NOP instruction.