JPS60188930A - Driving system of liquid crystal display device - Google Patents

Abstract

PURPOSE:To reduce the cost of a device by using a single power source, discriminating an effective applied voltage of turning on and off display by the number of pulses, holding a good display quality, and simplifying a power source and a circuit. CONSTITUTION:In case of an (n)X(m) matrix display, an EX-OR31 consists of (h) pieces of EX-OR circuits and a number extracting circuit for outputting a number which becomes a logical value ''1''. An input of this extracting circuit is a bus signal 25 of (h) bit and a display data signal 33 of (h) bit. A deciding device 32 is a deciding device whose main constituting element is an adder, and emits ''1'' in case when a number N of the logical value ''1'' is N>n/2. A frequency divider 34 for dividing into 1/m in case when X electrodes are (m) pieces generates a latch pulse 200 of an X electrode driving circuit. In this way, in case of the (n)X(m) matrix display, the display can be driven by a single power source.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a completely new driving method for a liquid crystal display device in which voltage averaging is performed by varying the number of applied pulses within a display frame.

[Conventional drive method]

An example of a conventional drive system will be explained with reference to FIG. 1 is a display of a liquid crystal display device, which is a 4×16 matrix display.

This matrix can be used to display 8-digit numbers including a decimal point in 4 x 2 segments by changing the Y' [pole and the handle. 2tiY [A pole drive circuit periodically emits a 4-level voltage waveform as a drive signal to "I * y, e Y, # Y4. 3 is an X electrode drive circuit that controls the 16 display data processors 7. A shift register that shifts data each time a shift pulse 5a arrives and a latch pulse 6I!L of an I/16 frequency divider 6 are used to shift data into 16 f-
It latches the data and emits a four-level voltage wave in response to changes in the Y drive circuit 2. 5 is a clock generator, which is necessary for the entire system (not shown) and is also used as a lock.

4 is a power supply, which has 6 levels for the display body 10YX electrode drive circuit and a level for other circuits, making it a power supply of 7 levels in total. 6-Level Power Supply for Driving Display Body 1 The present invention attempts to solve such defects by using a single power supply driving system.

〔the purpose〕

The purpose of the present invention is to turn on the display like a liquid crystal display.

Although the OFF state is determined by the applied effective voltage, the driving method uses peak value averaging to reduce power consumption with a single power supply, maintains good display quality, and reduces costs by simplifying the power supply and circuit. The purpose of this invention is to propose a driving method for a liquid crystal display device.

〔Example〕

1 and 2, an outline of the driving method of the liquid crystal display device of the present invention and its generalization when the scale of the display matrix is further expanded will be explained. The hardware aspects of the drive system of the present invention will be explained with reference to FIGS. 6 and 4.

- FIG. 1 shows an example in which the driving method of the present invention is applied to the same display body 1 explained in FIG. 5.

An 8a binary 4-bit counter can express 16 states. Reference numeral 8b denotes a latch circuit which delays the output of the counter 8a by one clock and applies it to the Y% pole of the display 1. 9 is an X electrode drive circuit whose main components are a shift register and a latch circuit that give two values of high and low to the X electrode. 10 is a clock generator, which includes a counter 8a and a latch circuit abI frequency divider 11. Give a pulse to the X electrode drive circuit.

The divider 11 divides the frequency by 1/16 and gives a latch pulse to the pole drive circuit by X%. Reference numeral 12 denotes a display data processor that converts the data into display contents, and every time the counter 8a advances one time, it outputs display data SlrSt*S3+S4 in which 4-bit data in the Y direction of the display body 1 is arranged in parallel for 16 times. .

Reference numeral 13 denotes a logic determination circuit comprising a Z X -0'R logic circuit and a determination circuit for determining the number of each logic Qh'''1'' of the EX-OR logic circuit. In Figure 1, F! x-OR
The logic circuit is 4 bits and the counter 8a outputs y + + 7t
+ 7s + 74 and the display data SI p St + s, l s4 of the display data processor, 1KX-OR logic is taken, and "1" is % = 2 <
If it is 3 or more, "1" is emitted from 13a and applied to the X electrode drive circuit 9. An actual example of the logic judgment circuit 16 is shown in the first (b)
) shown in figure. 14 is four BX-OR logic circuits, 15 is two OR logic circuits, 16 is two AND logic circuits, 1
7 is an OR logic circuit. With this configuration, if five or more "1"s occur in any combination of the four EX-OR logic circuits 14, the configuration of the OR logic circuits may change for several seconds.

Reference numeral 14 denotes a power supply, which includes two power supplies, one for display and one for other circuits. With the display capacity shown in FIG. 1, a single power supply in which the display and circuit power supplies are reversed is also possible.

Next, referring to FIG. 2, an example of the operation of the drive system of the present invention shown in FIG. 1 will be specifically explained. On the right side of the figure, three operation examples are shown in which one X electrode is used, with black circles indicating lighting and white circles indicating non-lighting. In Figure 2, a
, is the 4-bit voltage waveform of the counter 8a, and t is 0 and 1.
It is expressed as a logical value. bl is the voltage waveform applied to the X% pole when all four dots are turned off. b2
is a table showing the negative lighting position when voltage waveforms of 1 and 2 are added within one frame of O to F. Even if all the lights are off, there will be five lights on. The effective voltage applied to the liquid crystal is the power supply voltage in V. Then, 01 and C2 are the applied voltage when lighting two dots among the four dots and 17 rem 11 of each dot, and that of the non-lit dots is 5 like b2. Effective voltage averaging is therefore maintained.

In this case, the effective voltage applied to the lit dot is VOFF (Vth <von), where vth is the threshold voltage for lighting and non-lighting of the liquid crystal, and good display quality can be obtained.

Next, d and dt are tables showing the applied voltage waveform and the number of lights lit within 17 rem when all four dots are lit. In this case, all 11 elements maintain effective voltage averaging. In this way, even with a single power supply or depending on the timing of the applied voltage, the effective voltage of the total time width of lighting and non-lighting is kept constant, and good display quality can be obtained. f = VoN/Voyy =, /1115, which represents the index of goodness.
=1.485 is not inferior to the multi-power supply system.

Next, the rules for generating Au applied voltages such as ,C,,d will be explained.

Each table in FIG. 2 shows the contents of the counter 8a as 3'1+7!
*Vs + 74, display data "'I + s,
If l s, IS, then y, and SI, Yt and S
3. Take the EX-OR logic of y3, S3.74, and S4, and if the number of 1'' in each logical value is 5 or 4, change the applied voltage to °°1.
The rule is that it is sufficient to apply ``, or H voltage.'' The logic judgment circuit 13 executes this.

Since this logic judgment circuit 15 is executed for all the X electrodes, it does not require processing time equal to one clock of the input clock of the counter 8a, and a latch circuit 8b is required to delay the contents of the counter 8a by one clock. .

Next, a generalized case where Yl has n poles will be explained. Expanding the table in Figure 2 to n x 2n and considering the lowest combination of 1'' in the entire table, V(MxNx) = n(2-C
) n-1-)(n-1) O= C nnn-In-1 However, C=-door-c= a n r r r-(n-r),' , n If On-10n is an even number, then Take an integer close to (n-1). This is the number for the entire table, so per dot is y (uINx)
/n = 2 − '! *Therefore, the effective n- of yoyy
14(n-1) The voltage is vO,, = 17 times c)/2''vo n-1+(n-1) Similarly, consider the case where the table becomes inflated.

=n(2+O) n-1-) (n-1) As before, VON becomes:

■'''='F++l11'+(n)7y'a The index formula f(n) is as follows.

Even in the case of this film, we can use the EX-OR logic of the corresponding bits of the n-bit counter contents and the display data in the Y direction to calculate the logic [If the number N that becomes "1" is N>-i, then 61
” to the X electrode.

Here, in the example of Figure 1, n=4, so the same result as before was obtained.

Next, a configuration example of the Y[pole drive circuit and logic determination circuit expanded in FIGS. 5 and 4 will be described. In FIG. 3, reference numeral 20 shows a block when the Y' pole drive circuit is integrated into an IC.

21 is a clock. 22a is h bit output Q1□Q
up Qls e Q10 emits a 4h bit output. In the figure, cIJ is a clock input terminal and a carry signal to the upper digits of Oa. 22b latches the output of color/re 22a and connects it to the Y electrode with Q, tt*Q□, and Re Q10.
This is a latch circuit that provides a 4h output. Reference numeral 23 denotes a selection circuit which selects one of the four pieces using a 2-bit selection signal β.

E represents a selection signal for selecting the Y drive circuit 20.

24 is a signal from the selection circuit 25, which is a 3-state gate that sends the output of the counter 22a to the common data bus 25; Using the Yg and 2° lever drive circuits shown in Figure 3, fc
FIG. 4 is a diagram illustrating a configuration example for creating four signals at the Xi pole in the case of FIG. Reference numeral 27 performs a 4-minute IK using a branching device, and converts this 2-bit signal into a selection signal β. 2B is a 4/n splitter, and Y
'lE Camellia drive circuit p, clock and X electrode drive circuit shift pulse 100 e Pt e Pt...
...Fk is the name of the Y electrode drive circuit 20. The Y.29 decoder generates selection signals for the k Y[pole drive circuits 2o. Also, each of the above chest guards B n = 4 h
It is k.

28a is the input of the decoder 29, and the divider 28's NIB 31 is a number extraction circuit that outputs h EX-OR circuits and a number that has a logical value of "1".The input of this extraction circuit is the h-bit bus. Signal 25 and h-bit display data signal.32
This is a determiner whose main component is a ti-key device, and the logical value "
If the number N of '1'' is N>, then 11'' is emitted.

Numeral 34 is a frequency divider which divides the frequency by m when the number of X% poles is m, and generates the latch pulse 200 of the X electrode drive circuit.

In this way, even in the case of nXm matrix display, the display can be driven with a single power supply.

Note that the term matrix in the present invention also includes segment type.

[Function and effect]

As described above, since the driving method of the liquid crystal display device according to the present invention uses a single power source, voltage accuracy can be easily improved. Since the effective voltage for lighting and non-lighting is controlled by the time width applied to the liquid crystal, this also has the feature of high accuracy.

If n is an even number, the alternating signals applied to the liquid crystal within 17 rem will not be balanced. In this case, the life of the liquid crystal will be shortened, so the logic circuit is configured so that a reverse voltage is applied in the next 17 Rems.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a diagram showing a specific example of a conventional driving method for a liquid crystal display device. FIG. 1 is a diagram showing a simple example of the driving method according to the present invention. FIG. 2 is a diagram specifically explaining the operation of FIG. 1. FIGS. 3 and 4 are diagrams showing an example of a hardware configuration when n in the graphics display is large. Applicant: Epson Corporation Agent Patent Attorney Mogami (1)) Figure 2 1'J Figure 3

Claims (1)

[Claims] In a liquid crystal display device ffK that displays by forming an IJ layer with n Y electrodes and m X electrodes, the voltage applied to the liquid crystal display device is binary and generates a predetermined clock. A clock generating means, a 1/n frequency dividing means for counting the clock and generating a single or a plurality of operating signals, a counter whose main component is n bits for counting the clock of the frequency dividing means, and the counter. The first circuit consists of a latch circuit that latches the output and provides a binary signal to the YW pole.
means, which performs n equivalent EX-OR logics of the output of the counter and the display data in the Y direction, and releases @1 if the number of logical values "'1" is equal to or more than n/2; 2 means,
A driving method for a liquid crystal display device comprising a third means for sequentially accumulating the output signals of the second means in parallel and simultaneously applying lighting/non-lighting signals to the xg and poles.