JPS60183725A - Implantation of high-dose ions - Google Patents

Implantation of high-dose ions

Info

Publication number
JPS60183725A
JPS60183725A JP3985384A JP3985384A JPS60183725A JP S60183725 A JPS60183725 A JP S60183725A JP 3985384 A JP3985384 A JP 3985384A JP 3985384 A JP3985384 A JP 3985384A JP S60183725 A JPS60183725 A JP S60183725A
Authority
JP
Japan
Prior art keywords
film
ion
resist film
opening
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3985384A
Other languages
Japanese (ja)
Inventor
Minoru Hori
堀 稔
Jiro Ida
次郎 井田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP3985384A priority Critical patent/JPS60183725A/en
Publication of JPS60183725A publication Critical patent/JPS60183725A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation

Abstract

PURPOSE:To etch easily after the ion implantation and to eliminate adverse effect to a semiconductor water, by employing as an ion blocking mask a laminated structure which consists of a metal film having a larger ion-stopping power as an upper layer and a photo resist film being difficult to contaminate the wafer as a lower layer. CONSTITUTION:After a photo resist film 5, a metal film 6, and a photo resist film 7 are sequentially laminated, an opening 8 is formed in the photo resist film 7. When the metal film 6 within the opening 8 is etched away using the resist film 7 as a mask, and the resist film 7 and the resist film 5 within the opening 8 are removed by plasma-etching using oxygen, an ion blocking mask which consists of laminations of the resist film 5 and the metal film 6 and which has a common opening 8 are formed on the wafer. Thereafter, high dose ions are implanted near the opening 8 to form an ion-implanted area 9 on the wafer surface. However, the high dose ions irradiated on the metal film 6 are blocked by the film 6, only to form a very shallow ion-implanted area 10 on the surface.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、半導体集積回路の製造プロセス等において使
用されるイオン注入法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an ion implantation method used in the manufacturing process of semiconductor integrated circuits.

従来技術と問題点 半導体集積回路の製造プロセスにおいては、ウェハ内の
所望の個所にイオン注入を行う場合、所定箇所以外への
イオン注入を阻止するため、イオン阻止能の大きな物質
全マスク材料として使用している。即ち、第1図(A)
 K示すように、半導体ウェハ1上に開口3を有するイ
オン阻止用マスク2を形成した後、(B)に示すように
開口3の近傍にイオンビームを照射する。この結果、開
口3の直下の半導体ウェハ1内にはイオン注入領域9が
形成されるが、イオン阻止用マスク2上に照射されたイ
オンはここで阻止されて半導体ウェハ1ににイオン阻止
用マスク2全溶解やエツチング等によって除去し、次の
工程に進む。
Prior Art and Problems In the manufacturing process of semiconductor integrated circuits, when ions are implanted into a desired location within a wafer, a substance with a large ion-stopping ability is used as a total mask material to prevent ion implantation into areas other than the designated location. are doing. That is, FIG. 1(A)
After forming an ion-blocking mask 2 having an opening 3 on the semiconductor wafer 1 as shown in FIG. 1B, an ion beam is irradiated near the opening 3 as shown in FIG. As a result, an ion implantation region 9 is formed in the semiconductor wafer 1 directly under the opening 3, but the ions irradiated onto the ion blocking mask 2 are blocked here and the ion blocking mask 2 is exposed to the semiconductor wafer 1. 2. Remove by complete dissolution, etching, etc., and proceed to the next step.

従来、イオン阻止用のマスク膜としては、フォトレジス
ト膜、金属膜、酸化シリコン膜等が使用されている。し
かしながら、フォトレジスト膜をイオン阻止用マスクに
用いて筒ドーズfl(1015ions/Cm2以上)
のイオン注入を行うと、フォトレジスト膜が硬化し、通
常行われている硫酸等の薬品による溶解や、酸素プラズ
マによるアッシング等によってはこれを除去出来なくな
るという問題がある。
Conventionally, a photoresist film, a metal film, a silicon oxide film, etc. have been used as a mask film for ion blocking. However, if a photoresist film is used as an ion blocking mask, the tube dose fl (1015 ions/Cm2 or more)
When ion implantation is performed, the photoresist film hardens, and there is a problem in that it cannot be removed by conventional methods such as dissolution with chemicals such as sulfuric acid or ashing with oxygen plasma.

また、アルミニュウム等の金属膜全イオン阻止用マスク
として使用する場合、金属イオンがウェハ内に浸透して
ウエノ・全汚染する虞れがある。更に、酸化シリコン等
の酸化膜をイオン阻止用マスクとして使用する場合、酸
化膜の形成に高温処理が必要なため、ウエノ・内の不純
物分布が変化する虞れがある。
Furthermore, when a metal film such as aluminum is used as a mask for blocking all ions, there is a risk that the metal ions will penetrate into the wafer and contaminate the entire wafer. Furthermore, when an oxide film such as silicon oxide is used as an ion-blocking mask, high temperature treatment is required to form the oxide film, which may change the impurity distribution within the oxide film.

発明の目的 本発明は、上記従来技術の問題点に鑑みてなされたもの
であり、その目的は、イオン注入の終了後に容易に除去
することができ、しかもウエノ・になんらの悪影響も及
ぼすことのないイオン阻止用マスクを使用した高ドーズ
イオンの注入法を提供することにある。
Purpose of the Invention The present invention has been made in view of the problems of the prior art described above, and its purpose is to provide a material that can be easily removed after ion implantation and that does not have any adverse effect on the ion implantation. It is an object of the present invention to provide a method for implanting high-dose ions using an ion-blocking mask.

発明の構成 上記目的を達成する本発明は、半導体ウエノ・上に順次
フォトレジスト膜及び金属膜を積層し、該積層膜にエツ
チングにより開口を形成し、該開口の形成された積層膜
をイオン阻止用マスクとして高ドーズイオン注入を行う
ように構成されている。
Structure of the Invention The present invention achieves the above object by sequentially laminating a photoresist film and a metal film on a semiconductor wafer, forming an opening in the laminated film by etching, and applying ion blocking to the laminated film in which the opening is formed. The mask is configured to perform high-dose ion implantation.

以下、本発明の更に詳細を実施例によって説明する。Hereinafter, further details of the present invention will be explained with reference to Examples.

発明の実施例 第2図は、本発明の一実施例を説明するだめの工程図で
ある。
Embodiment of the Invention FIG. 2 is a process diagram for explaining an embodiment of the invention.

まず、(A)に示すように、半導体ウエノ・1上にフォ
トレジスト膜5.金属膜6及びフォトレジスト膜7をそ
れぞれ数μの厚みで順次積層する。フォトレジスト膜5
,7の形成は周知のスピンオン法によシ、またアルミニ
ュウム等の金属膜6の形成はこれも周知の真空蒸着法等
によp行う。
First, as shown in (A), a photoresist film 5. A metal film 6 and a photoresist film 7 are sequentially laminated to a thickness of several μm each. Photoresist film 5
, 7 are formed by the well-known spin-on method, and the metal film 6 of aluminum or the like is formed by the well-known vacuum evaporation method.

次に(B)に示すように、イオン注入を行うべきウェハ
領域上方のフォトレジスト膜7に、周知の7オトリング
ラフイ技術によシ開口8を形成する。
Next, as shown in FIG. 2B, an opening 8 is formed in the photoresist film 7 above the wafer area where ions are to be implanted using the well-known 7-otrinography technique.

引続き(C)に示すように、上層のフォトレジストj摸
7をエツチングマスクとして使用して、開[18内の金
属膜6をエツチングにより除去する。金属膜6がアルミ
ニュウムの場合には、エツチング液として燐酸液等を使
用する。
Subsequently, as shown in (C), the metal film 6 within the opening 18 is removed by etching using the upper layer photoresist 7 as an etching mask. When the metal film 6 is made of aluminum, a phosphoric acid solution or the like is used as the etching solution.

次に(I))に示すように、ガス棟に酸素を用いた周知
のプラズマエツチングを行い、上層のフォトレジスト膜
7と開口8内の下層フォトレジスト膜5全アツシングに
よシ除去する。この精米、フォトレジスト膜5と金属膜
6の積層から成シ共通の開口8を有するイオン阻止用マ
スクが半導体ウェハ1上に形成される。
Next, as shown in (I)), well-known plasma etching is performed using oxygen in the gas ridge, and the upper photoresist film 7 and the lower photoresist film 5 in the openings 8 are all removed by ashes. From this polishing and lamination of the photoresist film 5 and metal film 6, an ion blocking mask having a common opening 8 is formed on the semiconductor wafer 1.

この後(E)に示すように、上記積層膜のイオン阻止用
マスクの開口8の近傍に、周知の方法によりiaドーズ
(1015tons/ Cm2以上)のイオン注入を行
う。これにより、開口8内の半導体ウェハ1の表面には
イオン注入領域9が形成されるが、金属膜6上に照射さ
れた高ドーズイオンはこの金属膜6によって阻止され、
その表面に極めて浅いイオン注入領域10全形成するに
留まる。
Thereafter, as shown in (E), ions are implanted in the vicinity of the opening 8 of the ion-blocking mask of the laminated film at an ia dose (1015 tons/Cm2 or more) by a well-known method. As a result, an ion implantation region 9 is formed on the surface of the semiconductor wafer 1 within the opening 8, but high-dose ions irradiated onto the metal film 6 are blocked by the metal film 6.
Only the entire extremely shallow ion implantation region 10 is formed on the surface.

最後に、(F)に示すように、薬液等を使用して金属膜
6を除去しく金属膜6がアルミニュウムの場合には燐酸
溶液等を使用する)、この後下層の7オトレジスト膜5
を前述のアッシング等によシ除去することによυ、所望
の箇r!J′TVC所望密度の高ドーズ領域9が形成さ
れた半導体ウエノ・1が得られる。
Finally, as shown in (F), the metal film 6 is removed using a chemical solution (if the metal film 6 is made of aluminum, a phosphoric acid solution or the like is used), and then the lower layer 7 photoresist film 5 is removed.
By removing the above-mentioned ashing etc., the desired location is reached! A semiconductor wafer 1 in which a high-dose region 9 having a desired J'TVC density is formed is obtained.

上述の例では、工程(C)と(E)においてフォトレジ
スト膜を除去するのにアッシングを行ったが、これに代
えて薬液を使用して溶解除去を行っても良い。高ドーズ
イオンの注入の際、イオン阻止能の大きな金属膜6が上
層として存在するため、注入されたイオンは下層のフォ
トレジスト丼に5まで到達せず、従ってこのフォトレジ
スト膜5が硬化して薬液に浴解しにくくなることはない
In the above example, ashing was used to remove the photoresist film in steps (C) and (E), but instead of this, a chemical solution may be used to dissolve and remove the photoresist film. When implanting high-dose ions, since the metal film 6 with a large ion-stopping ability exists as an upper layer, the implanted ions do not reach the photoresist bowl 5 in the lower layer, so that the photoresist film 5 is hardened. It does not become difficult to dissolve in the medicinal solution.

発明の詳細 な説明したように、本発明は、イオン阻止能・の大きな
金属膜を上層に、半導体ウェハを汚染しにくいフォトレ
ジスト膜を下層にした積層+1・冒くξ、を、イオン阻
止用マスクとして使用して尚ドーズイオン注入を行う構
成であるから、イオン注入によりフォトレジスト膜が硬
化して事後の除去が困ft +・′こ々つたシ、金属イ
オンが半導体ウェハ全汚染したシするという弊害を完全
に除去できるとBう効果を奏するものである。
As described in detail, the present invention utilizes a laminated layer +1, which has a metal film with a high ion-blocking ability as an upper layer and a photoresist film that does not easily contaminate semiconductor wafers as a lower layer, as an ion-blocking layer. Since it is configured to perform dose ion implantation while being used as a mask, the photoresist film is hardened by the ion implantation, making it difficult to remove it afterwards. It is possible to completely eliminate this negative effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来技術を説明するための工程図、第2図は本
発す」の一実施例を説明するだめの工程図膜、 3,8
・・・011口、6・・・金属膜、9・・・イオン注入
領域。 特許出願人 住友T■℃気工業株式会社代理人弁理士 
玉 蟲 久 五 部 第 1 図 第2 図 (F) 「−1旋7−)1 工−−−−1−
Fig. 1 is a process diagram for explaining the prior art, and Fig. 2 is a process diagram for explaining an embodiment of the present invention. 3, 8
011 port, 6... Metal film, 9... Ion implantation region. Patent applicant Sumitomo T■℃Kogyo Co., Ltd. Patent attorney
Tamamushi Ku Part 1 Figure 2 Figure 2 (F) ``-1 turn 7-) 1 Eng----1-

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハ上に順次フォトレジスト膜及び金属膜を積
層し、該積層膜にエツチングによ多開口を形成し、該開
口の形成された積層膜をイオン阻止用マスクとして高ド
ーズイオン注入を行うこと′fe特徴とする高ドーズイ
オンの注入法。
A photoresist film and a metal film are sequentially laminated on a semiconductor wafer, multiple openings are formed in the laminated film by etching, and high-dose ion implantation is performed using the laminated film with the openings as an ion blocking mask. A high-dose ion implantation method characterized by fe.
JP3985384A 1984-03-02 1984-03-02 Implantation of high-dose ions Pending JPS60183725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3985384A JPS60183725A (en) 1984-03-02 1984-03-02 Implantation of high-dose ions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3985384A JPS60183725A (en) 1984-03-02 1984-03-02 Implantation of high-dose ions

Publications (1)

Publication Number Publication Date
JPS60183725A true JPS60183725A (en) 1985-09-19

Family

ID=12564522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3985384A Pending JPS60183725A (en) 1984-03-02 1984-03-02 Implantation of high-dose ions

Country Status (1)

Country Link
JP (1) JPS60183725A (en)

Similar Documents

Publication Publication Date Title
EP0256030B1 (en) Double layer photoresist process for well self-align and ion implantation masking
JP3459658B2 (en) Self-aligned masking for ultra-high energy implants applicable to local buried implants and isolation structures
JPS60183725A (en) Implantation of high-dose ions
JP2000235969A (en) Manufacture of semiconductor device
JPH0950968A (en) Manufacture of semiconductor element and semiconductor element
JPS62105464A (en) Manufacture of semiconductor device
JP2009071049A (en) Method of injecting impurity into semiconductor substrate
JPH10284479A (en) Manufacture of semiconductor integrated circuit
JP2656054B2 (en) Method for manufacturing semiconductor device
JPH01204414A (en) Manufacture of semiconductor device
JPH01205552A (en) Manufacture of semiconductor device
JPH1041309A (en) Wiring formation method of semiconductor device
JPH0254526A (en) Manufacture of semiconductor device
JPS6243341B2 (en)
JPS60240131A (en) Manufacture of semiconductor device
JPS61116842A (en) Manufacture of semiconductor device
JPS61161732A (en) Manufacture of semiconductor device
JPS61174645A (en) Manufacture of semiconductor device
JPS59175137A (en) Manufacture of semiconductor device
JPS59106134A (en) Method of producing semiconductor device
JPS59108317A (en) Forming method of electrode wiring
JPS60148139A (en) Manufacture of semiconductor device
JPH05182977A (en) Manufacture of semiconductor device
JPH10284468A (en) Manufacture of semiconductor device
JPS59169172A (en) Manufacture of semiconductor memory device