JPH0254526A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0254526A
JPH0254526A JP20517888A JP20517888A JPH0254526A JP H0254526 A JPH0254526 A JP H0254526A JP 20517888 A JP20517888 A JP 20517888A JP 20517888 A JP20517888 A JP 20517888A JP H0254526 A JPH0254526 A JP H0254526A
Authority
JP
Japan
Prior art keywords
photoresist
etching
dry etching
resist
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20517888A
Other languages
Japanese (ja)
Inventor
Soichi Nishida
西田 宗一
Mariko Itou
伊藤 麻理子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP20517888A priority Critical patent/JPH0254526A/en
Publication of JPH0254526A publication Critical patent/JPH0254526A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the wear of films in a resist and afford dimensions and forms of etching which fit into resist patterns by injecting highly concentrated and low energized species of ions before performing a dry etching process, thereby setting the surface and sidewalls of a photoresist film. CONSTITUTION:A photoresist 2 is deposited to 1.0mum thickness on a silicon substrate 1 and it is patterned. Phosphorus ions are implanted into the surface of a pattern of the resist 2 by tilting ion beams at the angle of 7 deg. to the silicon substrate to form a setting layer 3. Then, the ions are implanted in accordance with the same conditions as mentioned above by tilting ion beams at the angle of 7 deg. either in the opposite or in the surrounding directions and the setting layer 3 is formed. After that, dry etching is performed to obtain dimensions and forms of etching which fit into expected photoresist patterns.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は微細パターン化に利用できる半導体装置の製造
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that can be used for fine patterning.

従来の技術 第2図(a)〜(d)は、従来の半導体基板、たとえば
シリコン基板の一主面上にフォトレジストをパターニン
グし、ドライエツチングする場合の工程順断面図を示し
ている。まず、第2図(a)のようなシリコン基板上1
上に、第2図(b)のように、フォトレジストのパター
ニングを行なう。次に、ドライエツチングを行なうと、
第2図(C)のように、フォトレジストの膜減りが生じ
、結果として、最初のフォトレジストのパターン2より
も大きな第2図(d)のようなエツチングパターンを得
る。
2. Description of the Related Art FIGS. 2(a) to 2(d) are cross-sectional views showing the steps of patterning and dry etching a photoresist on one principal surface of a conventional semiconductor substrate, such as a silicon substrate. First, on a silicon substrate as shown in Fig. 2(a),
A photoresist is patterned on top, as shown in FIG. 2(b). Next, when dry etching is performed,
As shown in FIG. 2(C), the photoresist film is thinned, and as a result, an etched pattern as shown in FIG. 2(d), which is larger than the original photoresist pattern 2, is obtained.

発明が解決しようとする課題 しかしながら、上記従来の構成ではドライエツチングの
際、フォトレジストの膜減りが生じるので、目標とする
エツチング寸法およびエツチング形状を得ることができ
ないという問題を有していた。
Problems to be Solved by the Invention However, with the above-mentioned conventional structure, the photoresist film is thinned during dry etching, so there is a problem in that the target etched dimensions and shape cannot be obtained.

本発明は上記従来の問題点を解決するもので、ドライエ
ツチングの際、フォトレジストの膜減りを防止し、かつ
、目標とするフォトレジストパターンに合ったエツチン
グ寸法およびエツチング形状を得ることができる半導体
装置の製造方法を提供することを目的としている。
The present invention solves the above-mentioned conventional problems, and it is possible to prevent photoresist film thinning during dry etching and to obtain etched dimensions and etched shapes that match the target photoresist pattern. The purpose is to provide a method for manufacturing the device.

課題を解決するための手段 本発明は、半導体基板の一主面上の被エツチング膜上に
フォトレジストをバターニングする工程と、前記一主面
に対してイオンビームを傾け、イオン種を打ち込み、前
記フォトレジストの表面および側壁に硬化層を形成する
工程と、前記一主面をドライエツチングする工程とをそ
なえた半導体装置の製造方法であり、このときのイオン
注入濃度は5 X 10 ”cn+−2〜I X 10
 ”c+a−”、注入エネルギーは30KeV〜50K
eVが適当である。
Means for Solving the Problems The present invention includes a step of patterning a photoresist on a film to be etched on one main surface of a semiconductor substrate, and implanting ion species by tilting an ion beam with respect to the one main surface. A method for manufacturing a semiconductor device comprising the steps of forming a hardened layer on the surface and sidewalls of the photoresist, and dry etching the one main surface, and the ion implantation concentration at this time is 5 x 10''cn+- 2~I x 10
"c+a-", implantation energy is 30KeV ~ 50K
eV is appropriate.

作用 この構成によって、ドライエツチングによるフォトレジ
ストの膜減りが、従来と比較して格段に改善される。こ
のため、エツチングの対レジスト選択比の向上を図るこ
とができ、目標のエツチング寸法およびエツチング形状
を実現することができる。
Effect: With this configuration, the reduction in photoresist film due to dry etching is significantly improved compared to the conventional method. Therefore, it is possible to improve the etching selectivity to resist, and it is possible to realize the target etching size and shape.

実施例 以下、本発明の一実施例について、図面を参照しながら
説明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図(a)〜(f)は、本発明の一実施例を工程順断
面図で示したものである。まず第1図(a)のように、
シリコン基板上1に、第1図(b)のようにフォトレジ
スト2を1.0μm堆積し、投影露光により垂直なパタ
ーニングを行なう。次に第1図(C)のように、フォト
レジスト2のパターン表面に30KeV、 5 X 1
0”cm−2でリンイオンをシリコン基板に対し7°傾
けて打ち込み、硬化層3を形成する。次に、第1図(d
)のように、同じ条件で反対方向ないし、四囲の方向に
各々7°傾けてリンイオンを打ち込み、硬化層3を形成
する。その後、ドライエツチングを行ない、第1図(e
)のように、目標のフォトレジストパターンに合ったエ
ツチング方法およびエツチング形状を得ることができる
FIGS. 1(a) to 1(f) are sectional views showing an embodiment of the present invention in the order of steps. First, as shown in Figure 1(a),
A photoresist 2 having a thickness of 1.0 μm is deposited on a silicon substrate 1 as shown in FIG. 1(b), and vertical patterning is performed by projection exposure. Next, as shown in FIG.
A hardened layer 3 is formed by implanting phosphorus ions at an angle of 7° with respect to the silicon substrate at 0"cm-2. Next, as shown in FIG.
), under the same conditions, phosphorus ions are implanted in opposite directions or at an angle of 7 degrees in each of the four directions to form a hardened layer 3. After that, dry etching is performed, and as shown in Fig. 1 (e)
), it is possible to obtain an etching method and etching shape that match the target photoresist pattern.

第1図(f)はフォトレジストを除去した状態である。FIG. 1(f) shows the state with the photoresist removed.

発明者の実験によると、リンイオンを加速エネルギー3
0KeV、’ドーズ量5 X 10 ”(Ml−2で7
tトレジストパターンに打ち込み、硬化させてからフレ
オンガスを用いたRIEドライエツチングを行なったと
ころ、フォトレジストの膜減りが従来方式に比べて約1
15となることがわかった。
According to the inventor's experiments, phosphorus ions are accelerated with an energy of 3
0KeV, 'dose 5 x 10'' (7 with Ml-2
When the photoresist pattern was implanted, cured, and then RIE dry etched using Freon gas, the photoresist film was reduced by about 1% compared to the conventional method.
It turned out to be 15.

また、イオン打ち込みの際、イオンビームを傾けず、半
導体基板に対して垂直方向のみの場合、フォトレジスト
の膜減りは抑えられたが、フォトレジストパターンの側
壁方向の硬化が十分でな(、目標とするエツチング寸法
、およびエツチング形状が得られなかった。
In addition, when the ion beam was not tilted during ion implantation, but only in the direction perpendicular to the semiconductor substrate, the thinning of the photoresist film was suppressed, but the hardening in the sidewall direction of the photoresist pattern was not sufficient (the target The desired etching dimensions and etching shape could not be obtained.

さらに、イオン打ち込みの際の注入エネルギーが50K
eV以上となるとイオン種がB+の場合、基板まで到達
してしまう可能性がある。また、ドーズ量が5×10口
Ca1−”未満であると、フォトレジストパターンが十
分硬化できなくなり、目標とするエツチング寸法、およ
びエツチング形状が得られなかった。注入エネルギーが
30KeV未溝の場合およびドーズ量がI X 10 
”cm−”を越える場合は、イオン注入装置の性能上の
問題から、再現性ならびに制御性が不十分であった。
Furthermore, the implantation energy during ion implantation is 50K.
When the voltage exceeds eV, if the ion species is B+, there is a possibility that it will reach the substrate. Furthermore, if the dose was less than 5×10 Ca1-'', the photoresist pattern could not be sufficiently cured, and the target etching dimensions and etching shape could not be obtained. The dose is I x 10
If it exceeds "cm-", the reproducibility and controllability are insufficient due to performance problems of the ion implanter.

発明の効果 以上のように、本発明は、ドライエツチングの工程の前
に、高濃度、低エネルギーのイオン種を打ち込み、フォ
トレジストの表面および側壁を硬化し、フォトレジスト
の膜減りを防ぐことにより、フォトレジストのパターン
に対して忠実なエツチング寸法およびエツチング形状を
与えることができる優れた半導体装置の製造方法を実現
できるものである。
Effects of the Invention As described above, the present invention implants high-concentration, low-energy ion species before the dry etching process to harden the surface and sidewalls of the photoresist, thereby preventing film thinning of the photoresist. Accordingly, it is possible to realize an excellent semiconductor device manufacturing method that can provide etching dimensions and etching shapes that are faithful to the photoresist pattern.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は、本発明の実施例の工程順断面
図、第2図(a)〜(d)は、従来例の工程順断面図で
ある。 1・・・・・・シリコン基板、2・・・・・・フォトレ
ジストパターン、3・・・・・・P+イオン注入による
硬化層。 代理人の氏名 弁理士 粟野重孝 ばか1名第 図 (α) 1−−−シリコシ基不女 ’z−−−27yレジスに イ
FIGS. 1(a) to 1(f) are sectional views in the order of steps of an embodiment of the present invention, and FIGS. 2(a) to 2(d) are sectional views in the order of steps of a conventional example. 1...Silicon substrate, 2...Photoresist pattern, 3...Hardened layer by P+ ion implantation. Name of agent: Patent attorney Shigetaka Awano Idiot 1 figure (α) 1---Sirikoshiki Fume'z---27y Regis

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板の一主面上の被エッチング膜上にフォ
トレジストをパターニングする工程と、前記一主面に対
してイオンビームを傾け、イオン種を打ち込み、前記フ
ォトレジスト表面と、同フォトレジスト側壁に硬化層を
形成する工程と、前記一主面をドライエッチングする工
程を含むことを特徴とする半導体装置の製造方法。
(1) A process of patterning a photoresist on a film to be etched on one main surface of a semiconductor substrate, and tilting an ion beam with respect to the one main surface and implanting ion species, and forming a pattern on the surface of the photoresist and the same photoresist. A method for manufacturing a semiconductor device, comprising the steps of forming a hardened layer on a side wall and dry etching the one principal surface.
(2)イオン種の注入濃度が5×10^1^4cm^−
^2〜1×10^1^6cm^−^2で、注入エネルギ
ーが30KeV〜50KeVである請求項1記載の半導
体装置の製造方法。
(2) The implantation concentration of ion species is 5 × 10^1^4 cm^-
2. The method of manufacturing a semiconductor device according to claim 1, wherein the implantation energy is 30 KeV to 50 KeV.
JP20517888A 1988-08-18 1988-08-18 Manufacture of semiconductor device Pending JPH0254526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20517888A JPH0254526A (en) 1988-08-18 1988-08-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20517888A JPH0254526A (en) 1988-08-18 1988-08-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0254526A true JPH0254526A (en) 1990-02-23

Family

ID=16502714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20517888A Pending JPH0254526A (en) 1988-08-18 1988-08-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0254526A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165435A (en) * 2013-03-14 2013-06-19 上海华力微电子有限公司 Silicon etching process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165435A (en) * 2013-03-14 2013-06-19 上海华力微电子有限公司 Silicon etching process

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