JPS60182173A - Voltage impressing circuit - Google Patents

Abstract

PURPOSE:To impress voltage without erroneous writing or erasing by a method wherein, after impressing a specified node with power supply voltage, multiple nodes are impressed with high voltage in a 5V single power supply EEPROM. CONSTITUTION:A voltage impressing circuit is composed by means of connecting an MNOS element comprising a gate 3, a drain 5 and a substrate 7 to a high voltage decoder 102 which grounds or boosts voltage up to high voltage VP (voltage of node 110) utilizing a transistor 103 impressed with power supply voltage, a boosting circuit 101 and input signals B-D. In case of writing in, firstly impress an input signal A with high voltage (VCC) (this may be performed after input signal C) and impress another input signal C with high voltage and then impress the other signal B with high voltage. The other input signal D shall be constantly grounded.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a voltage application means for preventing erroneous writing and erasing in an EEPROM.
The present invention relates to a circuit that provides suitable voltage application means in an EKPROM such as a single-voltage power supply system.

[Background of the invention]

In a gEPROM, a high voltage is applied when erasing data, but the voltages must be applied in a certain order to prevent erroneous writing or erasing.

This will be explained by taking as an example the case where an NMO8 (metal-nitride-monoxide-semiconductor) element is used as a memory element, but the gist is the same even when using other types of elements, such as floating gate type elements.

FIG. 1 shows a cross-sectional view of the MNO8 element. This element is a MOS
The gate oxide film is replaced with a silicon nitride film 1 (for example, 300 mm
It has a structure in which A) is replaced with extremely thick SiO□2 (for example, 20 layers thick), and this will be referred to by the symbol shown in Fig. 2 from now on. In Figures 1 and 2, 3 is the gate, 4 is the n-type north, 5 is the n-type drain, 6 is the n-type substrate, and 7 is the ha
This is a p-type well provided in the NOS formation region.

There are 4 ways to apply voltage when writing or erasing to this device.
Shown in Figure 3. For the write bit, as shown in FIG. 3(a), a high voltage (for example, 15 V) is applied to the gate 3, and the source 4, drain 5, and well 7 are all grounded. For a bit that shares a gate electrode with this bit and whose stored information is not desired to be changed, the drain 5 should be floating as shown in FIG. 3(b), and the source 4 should be equal to or Apply a voltage (1) higher than that.
Hereinafter, for convenience of explanation, it is assumed that ■ is the same as ■, but the gist of the present invention is exactly the same even if ■ is different from V.

On the other hand, during erasing, as shown in Figure 3 (C1), a high voltage V is applied to the well.
is applied and the gate is grounded. At this time, the drain is made floating, and V is applied to the source so that the junction between the well and the source is in the forward direction and no current flows. Furthermore, for bits that share a well with this bit and are not erased, #! As shown in FIG. 3, Vp is also applied to the gate.

Writing and erasing of this element is performed by applying the voltage as described above, but there are many problems when realizing this in an EgPROM with a 5-inch power supply. it is%
Since V and vl are generated in a booster circuit provided on the same substrate, before applying V and vl to each electrode, a predetermined voltage that is equal to the boost voltage or lower than the power supply voltage is applied. It is necessary to apply this.

FIG. 4 shows an example of a voltage application circuit used in a 5V single power supply EEPROM or the like. In the figure, reference numeral 101 denotes a booster circuit provided on the same substrate, which is controlled by signal A, and generates a high voltage (2) at node 110 during boosting. 102 is a high voltage decoder, and when the input signal (indicated by symbols such as B and C%i in this figure) is Higb (equal to the normal power supply voltage Vcc, which will be assumed as it is from now on), the voltage at the node 110 is 2 as is, output node (3,
4, 7), and if the input signal is Low (grounded), the output node is also grounded. An example of the circuit of the high voltage decoder 102 is shown in FIG.
．． 121, a capacitor 122, and a clock signal 123.

When using this circuit, the input node 124 is first set to High.
signal and pulls the output node 125 to a voltage close to Vc c
Increase the temperature to 1. When the voltage at the node 125 rises to a voltage V1 close to Vcc, the transistor 103 is cut off, the high voltage decoder 102 starts working, and the potential at the output node 125 further increases until the voltage at the input node 126 of the high voltage decoder ( That is, the booster circuit output voltage V
) rises to the same voltage as

The time it takes for the voltage of the node 125 to rise from Vl to V is usually approximately equal to the boosting time of the booster circuit 101, which is about several tens of μs to several hundred μs. , 7) have almost the same rising speed, but the time to make the node 125 change to 1 depends on the rise time of the signal applied to the input node 124 and the output node 1
Since it is determined by the stray capacitance of 25, etc., it differs depending on whether the output node is connected to the gate, source, or well of the memory element.

Therefore, depending on the timing of applying a signal to the input node 124, there is a possibility that a voltage that instantaneously causes erroneous writing or erasing to occur in the memory element connected to the output node may be applied.

[Purpose of the invention]

An object of the present invention is to provide a voltage application method that eliminates the above-mentioned drawbacks and does not cause erroneous reading or erasing in an EEPROM having a booster circuit on the same substrate, such as a 5V single power supply type EEPROM.

[Overview of the invention]

The gist of the present invention is to apply a voltage v1 equal to, or close to and lower than the power supply voltage Vcc, at a predetermined timing to a plurality of nodes to which a high voltage is to be applied, and then to The purpose is to raise the voltages of the two voltages to a predetermined high voltage V almost simultaneously.

[Embodiments of the invention]

An embodiment of the invention is shown in FIG. As before, the case of 8 MNO elements will be explained as an example. This embodiment shows the voltage application timing for a bit that shares a gate with a predetermined bit when writing is to be performed and that is not desired to be programmed.

The purpose of the present invention is to set the input signal B to High at the start of writing.
(usually vce), the input signal C is set to High. The input signal is always held at ground when writing. Input signal A is a signal that starts the booster circuit, so the timing relationship with B and C does not matter, but in this example, it is set to go high before B goes high (this (shown by line 151)
. In this case, nodes 110, 3, 4.7 in FIG.
The voltage waveforms at 110', 3', 4', and 7 in FIG.
′ is shown.

First, the voltage at node 110 begins to rise, then source node 4 rises to ve, or voltage v1 close to it,
Finally, gate node 3 rises to Vl, after which the three nodes rise together to V2 with almost zero voltage difference. When writing ends, all nodes are returned to ground in the reverse order from when writing started.

If the voltage application method of this embodiment is used, the memory element will not be subject to the voltage application condition corresponding to the write state as shown in FIG. As mentioned earlier, this figure depicts the voltage waveform for the bit that shares the gate with the bit to which writing should be performed and which does not want to be written. Then,
The source line of the memory element is always grounded, so waveform C in FIG. 6 and waveform 4' in FIG.
becomes ground.

FIG. 8 shows a voltage waveform when input signal A is applied after input signal B%C as shown by line 152 in FIG. In this case, after a voltage V1 equal to or close to vec is applied to nodes 4 and 3, the booster circuit is activated and node 110 rises, and nodes 4 and 3 are simultaneously applied with a high voltage V1.
The pressure is increased to .

FIG. 9 shows a second implementation of the invention. In this embodiment, the voltage application waveform during erasing is shown for a bit that shares a well with a bit to be erased and that is not to be erased.

When writing data, the input signal C is set to (i gh), but the input signal A (the signal that starts the booster circuit 101 in the g4 diagram) becomes the river gh, as in the case of writing. It doesn't matter whether it is before or after. Figure 10 shows 47 when the booster circuit activation signal A is first applied.
The voltage waveforms at nodes 110.4 and 3.7 in the figure are respectively 110'.

4', 3', and 7'. The order of applying voltages 110', 4', and 3' is the same as in the previous writing. When erasing, an erase signal is applied last. As a result, as shown in FIG. 10, after Vcc or a lower voltage V1 is applied to the source 4' and gate 3', Vl is applied to the well 7, and then the mate 3, 4, and 7 are applied to V at almost the same time. rises to. When lowering the voltage, the well 7 is returned to ground last, followed by the gate and then the source. If the voltage application method of this embodiment is used, the memory element at any point in time corresponds to the written state as shown in FIG. 3 (al) or the erased state as shown in FIG. 3(C). It is not subjected to voltage application conditions, so erroneous writing or erasing does not occur.

Note that this figure depicts a voltage waveform for a pit that shares a well with an erased pit and is not erased. In the pit to be erased, the gate is always grounded, so B in FIG. 9 and 3' in FIG. 10 are grounded.

, 1g11, the input signal A is connected to line 152' in FIG.
The voltage waveform when applied after the input signals B%C and D is shown as shown in FIG. In this case, ■ee on nodes 4.3 and 7
After the voltage v1 at or close to the voltage v1 is applied, the booster circuit is activated, the node 110 rises, and the nodes 4.3 and 7 are simultaneously boosted to the high voltage (2).

Note that in both the first and second embodiments, (1) When increasing the voltage from 1 to V, the nodes to which high voltage should be applied are simultaneously increased; however, when decreasing the voltage, the order in which vl is applied is reversed. The pressure must be lowered. this.

Since the voltage increase speed is very fast compared to the voltage increase speed (normally, the voltage increase time is several tens of μs and the voltage decrease time is several tens of ns in a λ matrix), the voltage is simultaneously decreased for each memory element arranged in this way. This is difficult due to the time delay caused by stray capacitance and parasitic resistance in the matrix, and therefore it is necessary to sequentially step down the voltage with a sufficient time delay so that the predetermined order will not be reversed in any case. It is.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a voltage application method that does not cause erroneous writing or erasing in a 5V single power supply EEPROM or the like.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the MNO8 element, Figure 2 is a diagram showing its abbreviations, Figure 3 is a diagram showing the voltage application method to the element, and Figures 4 and 5 are the voltage application method to the element. The circuit diagrams of FIGS. 6 to 11 are diagrams showing embodiments of the voltage application method according to the present invention. 3: Gate 4: Source 5 Drain 7: Substrate on which the element is provided Figure 1 Figure 2 Figure 3 Figure 3 (Q) (b) (C) (d) Off 0! Continuation of page 1 of 1,8 drawings, 9 drawings, 10 drawings, 11 drawings @ Inventor Shinji Nabekama Shigegami Kodaira A @ Inventor 1) Ken 3rd grade @ Inventor Norimasa Yasui Shigegami Kodaira A

Claims (1)

[Claims] 1. A first voltage source located inside the integrated circuit and higher than the power supply voltage.
A second voltage equal to or lower than the power supply voltage is first applied to the node to which the first voltage is applied, and then the first voltage is applied to the node to which the first voltage is applied. A voltage application circuit characterized by having means for applying. 2. It has a plurality of nodes to which a voltage higher than the power supply voltage is applied, and has means for applying a voltage higher than the power supply voltage that is equal to or different from each other to the plurality of nodes. A voltage application circuit according to claim 1. 3. Voltage application according to claim 2, characterized by having means for sequentially applying a second voltage lower than the power supply voltage to the plurality of nodes with a predetermined time delay. circuit. 4. The voltage higher than the power source 'Narita' is supplied from a high voltage generation circuit provided on the same substrate. Voltage application circuit. 5. The plurality of nodes are a gate and a north of a nonvolatile memory device, and the predetermined time delay is set such that the source node rises first and then the gate node rises. A voltage application circuit according to claim 4. 6. The plurality of nodes are gate, source, and well or substrate nodes of a non-volatile memory device, and the predetermined time delay is such that the source node first, then the gate node, and finally the well or substrate node. 5. The voltage application circuit according to claim 4, wherein the voltage application circuit is set so that the voltage increases.