JPS6446965A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6446965A
JPS6446965A JP20339187A JP20339187A JPS6446965A JP S6446965 A JPS6446965 A JP S6446965A JP 20339187 A JP20339187 A JP 20339187A JP 20339187 A JP20339187 A JP 20339187A JP S6446965 A JPS6446965 A JP S6446965A
Authority
JP
Japan
Prior art keywords
booster circuit
output
switch circuit
circuit
rise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20339187A
Other languages
Japanese (ja)
Other versions
JP2798921B2 (en
Inventor
Masaki Momotomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20339187A priority Critical patent/JP2798921B2/en
Publication of JPS6446965A publication Critical patent/JPS6446965A/en
Application granted granted Critical
Publication of JP2798921B2 publication Critical patent/JP2798921B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To make it possible to restrain the deterioration of characteristics caused by repeating a program operation, without decreasing the operation margin, by providing the output terminal of a booster circuit with a switch circuit to make an output of the booster circuit leak for a specified period shorter than program time. CONSTITUTION:A switch circuit 3 to make an output Vpp of a booster circuit 4 leak for a specified period shorter than program time is arranged on the output terminal of the booster circuit 4. Therefore, the waveform of booster circuit output Vpp at the time of rise-up can be smoothed by controlling the switch circuit 3. Differently from the case where the current supplying capability of the booster circuit 4 itself is decreased, it is possible that the rise-up characteristics are decreased only for a specified period by the switch circuit 3, and then the rise-up characteristics of the output electric potential can be recovered by turning off the switch circuit 3. Thereby, a program voltage having a sufficient margin can be obtained.
JP20339187A 1987-08-18 1987-08-18 Semiconductor integrated circuit device Expired - Fee Related JP2798921B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20339187A JP2798921B2 (en) 1987-08-18 1987-08-18 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20339187A JP2798921B2 (en) 1987-08-18 1987-08-18 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6446965A true JPS6446965A (en) 1989-02-21
JP2798921B2 JP2798921B2 (en) 1998-09-17

Family

ID=16473266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20339187A Expired - Fee Related JP2798921B2 (en) 1987-08-18 1987-08-18 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2798921B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182173A (en) * 1984-02-29 1985-09-17 Hitachi Ltd Voltage impressing circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182173A (en) * 1984-02-29 1985-09-17 Hitachi Ltd Voltage impressing circuit

Also Published As

Publication number Publication date
JP2798921B2 (en) 1998-09-17

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees