JPS60181793A - Matrix display addressing circuit and addressing method therefor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an addressing circuit for a 71 to RIX display incorporating a shift register consisting of a static memory, and an addressing method for the circuit. It is particularly applied to the scanning of liquid crystal displays for the display of images and/or alpha nimeric characters.

BACKGROUND OF THE INVENTION In a 71-Rix display, the scanning of the basic display dots across the rows and columns of the display is accomplished by two sets of shift registers: a "column" register and a "P-row" register, in other words a This is accomplished by a video register.

FIG. 1 shows schematically in a simple form a matrix display with an attached control circuit.

This display includes display screen 1, and this display screen 1
is the basic display 1 arranged in a matrix of In rows and 1 columns.
- It is formed by A and 2. These basic display drivers 1
2 each have a capacitor, the insulator of which consists of a liquid crystal and is controlled by a planar I-transistor.

This display also has +1 analog memory 4
1...4n, each of which is constituted by a capacitor that stores a sampling value of video signal 3. The operation of converting the video signal to the analog memory is controlled by a "row" shift 1-register having 0-stage unit registers 51...5n provided in the 8th row for l, jp, digits. Ru. This "row" shift register is of the serial input/parallel read type.

Scanning of analog memory 41...4n is column shift 1
- This is done by the signal 7 applied to the input terminal of the unit register 51 at the first stage of the registers. This signal is a high level signal, that is, a "1" level signal, and is energized by the tarok signal 9 to register the unit registers 52...5n of the next stage and below.
Transferred in order of t\. 1<i<n, the addressed analog memory 4i11, the associated unit register 51
is the memory that stores the "1" level signal.

If you look at the actual place, analog memory 41...4
n is constituted by a low capacitance capacitor, which is loaded at any moment with the current value of the video signal 3. In addition, the column-by-column register has the function of connecting the video signal 3 to the capacitor and the function of cutting them off at the exact time when the sample value is to be taken. Therefore, the analog memories 41 . . . 4n are loaded with the final value of the video signal ij before the capacitor and the video signal 3 are cut off.

Following the storage of a video signal for a complete row j of nice play display dots 2, where j is an integer between 1 and nl, the video signal is provided in units of 1 in each column A. J'r
It is possible to transfer data to the display driver 1 to 2 of the predetermined column by means of a "column" shift 1 register having one stage of intermediate registers 61 . . . 6 m. The registers in this column are also serial write/parallel read type. Transfer to 1118th register 6J
is ensured by bringing each 1-transistor associated with each display dot 2 in three columns into a conductive state.

After transferring the video signal to the three columns of the display, the analog memories 41...4n are emptied and then the next
The video signal related to the +1 column is reloaded. During this reloading, unit register 6J+1 stores each display number 1 in column j+1.
- is controlled to maintain each transistor associated with the transistor in a conductive state.

Column 1' register 6 is controlled in a similar manner to register 5. The "unit register 6" inputs the "1" level signal 8 manually. Each unit register 62 in the next stage and subsequent stages is activated by this rlJ level number signal lock signal and successively registers 62...Gn
and is transferred to unit register 6J, where 1 < j <
rn conducts each transistor associated with the five columns of display dots 2.

Figure 2 shows the conventional one-line shift 1 register (51...
・5n) is shown in more detail. What should be noted here is that
The "column" shift 1-registers (61...6n1) are effectively the same as the "row" registers.

The column register is composed of unit registers each having two dynamic memory elements or one static memory element and one dynamic memory element. Among these unit registers, the information necessary for addressing column i, for example, is stored in a static memory element S1 formed by a bistable multivibrator (two-loop gate) as shown in FIG. During the transfer of information from memory element Si to memory element Si+1, the information placed in static memory element Si is temporarily stored in a dynamic memory element Dj, which is mainly constituted by a capacitor. This dynamic memory element D1 is indispensable.

If so, the old information k stored in the memory element Si
, so that it can persist while its contents are changed.

The operation of transferring information from memory element Sj to element Sl+1 and hence from one unit register to another is performed by switches C1 and 02.

These switch-on operations are performed by clock pulses φ11 and φ having different phases formed by the transfer lock 12, respectively.
1? controlled by

Pulse ψIZ controls switch C2 to allow information to be transferred from memory element Si to memory element D1, pulse φ11 controls switch C1 to load first memory element S1 and then from memory element []1 to memory element Si+1. enable the transfer of information to.

(Problems with conventional technology) These shift registers are relatively bulky;
For some applications, such as display scanning of redundant matrices, one controller for the basic display dots can be used.
- Two or more spaces in the roll row
Placing the 1st shift register requires LJIJI1 because the space is usually less than 100 μm wide.
It is.

(Means for Solving the Problems) The 71-res circuit of the present invention is interposed between P serial 1 ( )/parallel read column or row unit shift 1-registers and column or row unit registers. The first transfer lock supplies a switch control clock signal for performing an information transfer operation from one unit register to another 111th register.

The present invention also addresses the P columns or rows of the basic display driver 1- of a matrix display using an addressing circuit.
Regarding the response method, this is accomplished by the following steps.

b. Loading a "1" level signal into the first stage unit register by being energized by the first clock signal. Other unit registers contain "0" level signals.

Input this "1" level signal into the second clock (No. 3).
The data is transferred in stages from the unit register 14 <-1 to the i1 register MI<. The "1" level signal is available from the output end of the unit register M s<-1.

From there, it is energized by the first clock signal and 4 times are sent from the unit register M<< to the fourth register M+<+1. The "1" level signal is available from the output terminal of the unit register M1(-1).The unit register M1(-1-t contains a "0" level signal.

71 Two consecutive rows of diff spray display dots
-Reply 1,? In other cases, the following additional steps may be beneficially performed.

(The first video signal to be transferred to the -L column of the D display is stored in the analog memory.

■ The first image (QI multiplication signal) is output from the analog memory to the Transfer to.

■ Store the second video signal to be transferred to the first column of Nice Press in the analog memory. And (4)
Said second? The video signal of i'ili is transferred from the analog memory to the first column by a fourth clock signal having the same frequency and phase difference as the third clock signal.

This signal controls one of the first switches iff connected to the output terminal of the JII register M<1>.

(Function) Forms a first clock signal that controls a first transfer lock or a first switch group, and the first switch group controls each switch.
The first clock signal is arranged in front of the unit register M+<-x (for IC, all even numbers between 1 and l) by -. Low 1- level compensation code to register M1 and unit register II (contents of register M
+< +1, and furthermore, the first transfer lock has the same frequency as the first tarlock signal but has a phase difference, and the second
A second clock (No. 3) is arranged in front of each unit register M+<, and the second clock signal controls the switch group of the register element M r (-1 to be transferred to the register element Mr<). Shime, and each A 4th place register M+<
-1,M+< is formed by a single static memory element and serves to address the 13 columns or P rows of the basic display dots of the matrix display.

(Embodiment) The following description relates to a 71-lix display having a Jk book display frame 1 with m rows and 11 columns.

FIG. 3 shows a "row" shift 1-register that allows address of the prefecture tree display number 1 related to the row of the display.

According to the invention, the column register has only n static memory elements M1...Mn, in other words the shift is one memory element per unit register. Each memory element is formed by a single bistable multivibrator (two-loop gate) assembled on the basis of 10S technology, where i is an integer between 1 and 11, e.g. .

Between two consecutive memory elements, switches C1 and 02
are arranged alternately. These switches [1 and 02
The control of is caused by tarlock signals .phi.1 and .phi.2, respectively, produced successively by transfer locks 13.

Tarock signal φ1 controls all switches C1 at the same time. Switch C has an even number (tube 42, 14.M
6), the memory element Mi and the subscript are the number of cylinders (Ma, Mq
.

17) is used for connecting and disconnecting pairs of memory elements Mj++.

Similarly, clock signal φ2 controls all switches C2 to 113'. The latter switch C2 selects between memory elements with odd numbers (Ml, Ml, Ms) and memory elements with even numbers (M?, , 1L+, Me).
It is used to make connections and disconnections between the two.

Clock signal φ1 supplied by transfer lock 13
The frequency of φ11 and φ2 is, for a given size column register, half of the tarlock signals φ11 and φ1z provided by the transfer lock 12 used in a conventional column register such as that shown in FIG.

r1 analog memory 41...4n (Figure 1)
The operation of this column register, which is used to sample the video signal 3, is described in detail below in connection with FIG. This figure graphically shows the state of the unit register over one cycle. As explained in FIG. 4, the tarlock signals φ1 and φ2 have a phase difference, specifically a difference of π, and have the same frequency.

In the initial state, all memory elements Mi are at "0" level. The storage operation of the first address information or rlJ level signal for the memory element Mi is the summation of the video signal 3 to the analog memory 41 (Fig. 1).
0, which is caused by the first tarok pulse ψ1.

"1" level 4n given by memory worship IMr ll'i'
The signal is transferred from S1+ to memory element 12 by the first clock pulse φ2 while the output of memory element 11 is available for sample linking of the analog memory 417\video signal. Signal φ2 simultaneously controls switch C2, but only the contents of memory element 12 are changed, Ic, other memory elements M, M4, Ms...
... is a "0" level state. I to memory element M2
The "1" level signal with l'i' gill A is
While the output of memory element t12 is also available for sampling the video signal into analog memory 42, it is transferred to memory element to1 by the second clock pulse φ2. While the "1" level signal is transferred from the memory device 12 to the memory element L:+/\, the rQJ level signal is taken into the memory device triplet 11. Signal φ controls all switches c1 at the same time, but only memory element T1.
Only the contents of 3 are changed, and elements M4, PI;, M6...
C is in the "o" level state. By this method, information is moved from one memory element to another until the end point 1. Continue until = n)
L, there is no sublinking of the video signal corresponding to complete row j to the display driver 1 of the display. However, j is an integer between engineering and Ill.

In the row shift 1 register, two consecutive memory elements Mj and M, except obviously during loading memory element M1 and sampling the video signal into memory element Mn,
There are two "1"s in i+x (Figure 4).

The simultaneous presence of rlJ in the memory elements Mi and Mi4-2 does not cause any inconvenience in sampling the video signal into the analog memory 11. as a matter of fact,
These memories are capacitors, so they are U-doped by the final value of the video signal 3 that was input before being cut off from the video signal 3.

The analog memory 41 is cut off every clock pulse φ1 or φ2 (FIG. 4), and as a result, a considerable amount of the video signal is zumbled. In the prior art (Fig. 2), the video signal is zumbled using only the tarokk signal ψ12,
No. 3 .phi.11 simply transfers information from the 1'+ registers to the other registers. Moreover, the column register according to the invention includes only 1'81' more memory elements than the prior art.

Basic display number 1-'s image 8 for column j! Signal Ili'
Following the storage, provided that the video signal is in the range from 1 to Hl, the video signal can be transferred from the display 1 to the predetermined number 1 by the column shift 1 register according to the present invention.

FIG. 5 shows a one-column shift 1-register in accordance with the present invention. This register has the same structure and function as the "row" register. Components performing the same function are indicated by the same reference numeral with an abostrophy added.

The column registers are simply m static memories or 11'.
. . . M m ', ie, one memory element per unit register. Each memory element Mj', where j is in the range between 1 and In, is 10
It consists of one bistable multivibrator manufactured by S technology.

Switch Cq' or C between two consecutive memory elements
2' are provided alternately. The switch Ct' is simultaneously controlled by the tarlock signal .phi.1', and the switch C4' is controlled by the clock signal .phi.2'.

The signal φ continuously generated by the transfer lock 13'
1' and φ2' have a phase difference of, for example, π, as shown in FIG. 6, and have the same frequency.

As in the case of the row register, the first pulse of signal φ1' is used to store a "1" level signal in memory element 11', and the following other pulses store said "1" level signal in memory element 11'. It is used to transfer data from M 2', M4', M a'. to memory elements M r+', M s', M 7', .

Similarly, the tarok pulse φ2' sends a "1" level signal to the memory elements J'M1', M3', M,'...
It is used for transferring data from the memory elements Hz', M4', MC, / .

As mentioned above, while the signal φ1' or φ2' is applied, the contents of only one memory element 1j' are changed.
L.

As in the row shift 1-register, there are two rlJ levels in two consecutive memory elements old' and to1'j+1 as shown in FIG.
level condition. The presence of these two rlJ levels is detrimental in the column registers, unlike in the row registers. Therefore, the transfer of the video signal to the display driver 1- of the display not only requires intervening for the column (11-) of the display toso 1-, but also requires the transfer of the video signal to the two columns of the display driver 1-. It must not be a thing.

In order to use only the "1" level of qt- contained in the column register, switches C:] or C4 are arranged alternately at the output of each memory element T-Mj', and therefore of the unit register.

This A and the other switches C: I and C4 are each transfer lock 1
It is controlled by clock signals .phi.3 and .phi.4 successively generated by the clock signal .phi.4. The signals φyo and φ4 have a phase difference and have the same frequency.

A signal .phi.3 which simultaneously controls all the switches C3 is used to transfer video signals corresponding to columns 1, 3, 5 and 7 of the display dots on the display.

Similarly, a signal φ that controls all switches C4 simultaneously
4 is used to transfer video signals corresponding to 2, 4°, 6 columns, etc. of the display dots on the display.

In order to transfer the video signal related to column j to a predetermined column, different clock pulses cause different switches C1'
Cz′, C: must be applied to i and C4 in the following order. They are φ1', φ3'', φ2, and φ4.

The column shift 1-register according to the invention has half the number of memory elements compared to the conventional one.

(Effects) The addressing circuit according to the present invention provides row and/or column shift 1-1 with half the number of memory elements compared to the prior art.
Contains registers. This allows the overall dimensions of these registers to be halved, thereby simplifying the circuit. The same applies to the circuit that uses the frequency of the first transfer lock to control the switch. This is more specifically based on the use of static memory elements only.

[Brief explanation of the drawing]

FIG. 1 shows the prior art as described above;
FIG. 7 is a schematic diagram showing a roll circuit 71 helix display in a simplified form. As mentioned above, FIG. 2 is a schematic IA of a conventional column shift 1 register. FIG. 3 is a schematic diagram 1) showing a row shift register according to the invention. FIG. 4 is a diagram illustrating the states of the row unit registers along the time axis. FIG. 5 is a schematic diagram illustrating a column shift register according to the present invention. FIG. 6 is a chart illustrating the states of the column shift registers along the time axis. 2... System book display dot 4... Analog memory, 5, 6... Unit register,
1, 3. 13'...First transfer lock, CI,
Cl', C7. '...Switch, φ1, φ1'...
First clock signal, φ2, φ2'...Second tally signal, φY, φ3'...Third clock signal, Ml, M1
'...First stage unit register, L<-t...First unit register, t11 (...Second unit register, M I< +1...Third unit register, Mi, M
Static memory of j...Ql, -. FIG, 3 FIG, 4

Claims (4)

[Claims] (1) I] serial write/parallel read type row or column unit registers constituting the basic display dot means of the P column or P row display and a switch interposed between the row or column unit registers; a first transfer lock that supplies a switch control clock signal for moving information from one unit register to another; the first transfer lock includes a first clock signal that controls a first switch group; make,
Each of the first switches 1 (J'L) is arranged one at a time before the first unit register among the P series unit registers, and the first clock signal outputs a high level signal to the first unit. loading a register and causing the contents of a second unit register following the first unit register to be transferred to a third unit register following the second unit register; A second clock signal is generated to control a second switch group having the same frequency as the first grotter signal and a phase difference, and each switch of the second switch group is placed one at a time before the second entitlement register.
+,, the second clock (No. 11) causes the contents of the first unit register to be transferred to the second unit register, and each node 1 and the second unit register are formed by a single static memory element. 71 characterized by being
-Refstayspray address circuit 6 (2) The basic display dot means of the P column display includes third and fourth switch groups used to transfer the sampled video signal to one basic display dot of the P rows, and the third switch group is arranged at the output end of the first register, the fourth switch group is arranged at the output end of the register, and further includes a third clock signal that controls the third switch group and a clock signal having the same frequency as the third clock signal. 2. The address circuit for a matrix station brake according to claim 1, further comprising a second clock having a phase difference between the clocks and the second clock for producing a fourth clock signal for controlling said fourth switch group. (3) Loading a high-level signal into the first-stage unit register among the P serial unit registers and loading a low-level signal into the other succeeding unit registers by being powered by the first clock signal; , the second clock signal causes the previous iL! The high level signal obtained from the output terminal of the first unit register is transferred stepwise from the first unit register of the p series registers to the second unit register following the register, and then the first is energized by the clock signal of the second unit register to transfer the high level signal from the second unit register to the third unit register following the unit register, and transmit the low level signal to the other unit registers. and loading the P column or P
71-less circuit addressing method for matrix display, characterized in that it is applied to the basic dot display of row nice play. (4) storing in an analog memory a first video signal to be transferred to the first of the two consecutive columns of display basic dots among the P columns; and coupling to the output terminal of the first coronation register; transferring a first video signal from the analog memory to the first column by being activated by a third clock signal that controls a third switch a fourth unit register connected to the output terminal of the second unit register;
controls the switches of the switch group, and controls the third clock 4f.
3. Transferring the second video signal from the analog memory to the second column energized by a fourth clock signal having the same frequency as J7'7 and having a different phase. How to address the addressing circuit of the matrix display described.