US4758996A - Address translator - Google Patents
Address translator Download PDFInfo
- Publication number
- US4758996A US4758996A US07/008,848 US884887A US4758996A US 4758996 A US4758996 A US 4758996A US 884887 A US884887 A US 884887A US 4758996 A US4758996 A US 4758996A
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- US
- United States
- Prior art keywords
- address
- map
- bits
- locations
- field
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
Definitions
- the present invention relates generally to devices for and methods of more efficiently storing data in a storage memory device and, more particularly, to a device for and method of translating address signals representative of specific locations of a first address map to address signals representative of more efficient locations of a second address map.
- Various devices for processing graphic data typically generate signals representative of both the content of each pictorial segment of the original pictorial representation (typically referred to as a "pixel"), and the location of each pixel in the original pictorial representation.
- the reproduction image of the original pictorial representation is thought of as a matrix array or map of multiple columns and rows of pixels, reproduced, for example, on a predetermined surface in the case of printers or on a screen in the case of cathode ray tube (CRT) monitors.
- the reproduction image is typically reproduced by scanning the surface or screen with a "writing” instrument such as a laser (in the case of a printer) or an electron gun (in the case of a CRT screen).
- the scanning area, upon which the images are provided is dimensioned so as to accommodate various standard sized paper.
- one commercially available laser printer has a drum approximately 11 inches long and 17 inches around its circumference so as to accommodate B-sized metric paper having those dimensions.
- the printer by switching the laser on and off as the beam scans the drum, is capable of providing an image approximately as large as 11 by 17 inches by printing the pixel array on a sheet mounted on the drum.
- the pixel array is shown generally in FIG. 1 as a two-dimensional image having precisely 1152 rows, numbered consecutively from 0 to 1151, and 1792 columns, numbered consecutively from 0 to 1791.
- a data signal represents the information contained in the pixel
- an address signal represents the spatial location of the pixel (e.g., by row and column) relative to the other pixels.
- storage memory comprising a large enough storage capacity to store all of the data signals in a manner so as to preserve the relative spatial relationship among the pixels so that the image can be reproduced.
- each location in memory, adapted to store a data signal must be responsive to a corresponding unique address signal so that the data signal associated with that address signal can be read into and written out of that storage location in response to the unique address signal.
- an image containing a 1152 by 1792 array of pixels is represented by 1152*1792 data signals and 1152*1792 address signals.
- the digital format of each address signal for a 1152 by 1792 array must contain at least 11 binary bits corresponding to the row location of the pixel (since 10 binary bits can represent the numbers 0 through 1023 and 11 binary bits can represent the numbers 0 through 2047) and at least 11 binary bits corresponding to the column location of the pixel.
- the address signal should contain 22 binary bits in the address field, which can be represented by:
- the field defined by the bits Y 10 . . . Y 0 provides a binary number representative of the row location with Y 10 being the most significant bit and Y 0 being the least significant bit
- the field defined by the bits X 10 . . . X 0 provides a binary number representative of the column location with X 10 being the most significant bit, and X 0 being the least significant bit. Since commercial memory devices typically come in sizes which are powers of 2, given a 22 bit address signal, the smallest amount of conventional storage memory that can be used is 2 22 , or 4 megabytes, since it includes 2 11 ⁇ 2 11 or 2048*2048 (4,194,304) memory locations.
- this approach requires additional memory logic for storing the look up tables for converting each 22 bit address signal to a unique 21 bit address signal before the corresponding data signal can be stored.
- additional memory logic to store the lookup table does not necessarily result in any substantial savings with respect to the overall expense of manufacturing nor physical space in a commercialized system employing the lookup tables.
- Another object of the present invention is to provide a device for use with storage memory for storing data representative of an image in a more efficient manner, without the necessity of additional memory logic, complicated look up tables or signal multipliers.
- Yet another object of the present invention is to provide a device, responsive to at least one bit of the address signal representative of any one of a number of select locations of pixels of a pixel map of an image, for storing data contained in the pixel map in a minimum amount of storage memory, without requiring additional memory logic, complicated look up tables, or signal multipliers.
- the device comprises:
- sensing means for sensing said at least one bit of said first address field representative of addresses of said first address map where m is equal to or greater than 2 a +b-c;
- said second address field represents the same address locations of said second address map as said first address map
- said second address field represents unique address locations of that portion of said second address map where q exceeds 2 d +e respectively corresponding to address locations of that porton of said first address map where m equals or exceeds 2 a +b-c.
- a device for translating a first address signal including a first address field representative of the address locations of a pixel map, into a second address signal including a second address field representative of the address locations of a storage map wherein the pixel map and address map have corresponding address locations which are in the same relative positions, the pixel map includes address locations which do not directly correspond to locations in the storage map, and the storage map includes address locations which do not directly correspond to locations in the pixel map.
- the device comprises:
- the means for generating the second address signal including
- FIG. 1 is a 2-dimensional representation of the maximum 1792 by 1152 pixel map of an image of the type provided on the largest permissible paper by a laser printer of the type described above;
- FIG. 2 is a 2-dimensional representation of a map of a standard two megabytes of memory, drawn to include 2048 unique column addresses and 1024 row addresses, which according to the principles of the present invention provides more efficient use of storage capacity for the addresses corresponding to the 1792 by 1152 pixel map of the image size shown in FIG. 1; and
- FIG. 3 is the preferred embodiment of the device for translating at least some of the bits of the address signals representative of a pictorial representation provided in the data of the matrix of FIG. 1 for storage in the storage matrix of FIG. 2.
- a maximum-sized image can be printed on paper positioned on the drum of the type of laser printer described above in a by 1792 by 1152 pixel array, (a 2-dimensional map X m by Y n of which is shown in FIG. 1) with each array element of the matrix being a pixel of the image.
- Each pixel can be represented by a data signal containing the informational content represented by each pixel.
- the exact informational content of each pixel, represented by the corresponding data signal, can vary and is not of importance with respect to an understanding of the present invention.
- each pixel in the pixel map is also represented by an address signal unique to each row and column position so that the image can be easily reconstructed, when printing the image on paper supported by the drum.
- each data signal of the image formed by the 1792 by 1152 pixel map prior to printing the image so that the pixel information corresponding to each address location of the pixel map can be retrieved from a separate memory location, and subsequently printed in the proper position on a piece of paper mounted on the drum of the printer.
- the storage capacity of conventional storage memory is only provided in select sizes, typically in powers of 2.
- the size of the storage memory must be selected so that it is large enough to be responsive to all of the possible address signals corresponding to all of the pixel locations of the pixel map, and therefore capable of storing all of the pixel information.
- the size of storage memory is therefore dependent on the number of bits of the address field used for the address signal format.
- each the address field includes sufficient bits to provide a binary representation of all of the columns Y plus a binary representation of all of the rows X represented by the address signal.
- a 22 bit address signal appears to be required to represent all 1152 by 1792 address locations, where 11 bits are required to represent all of the 1152 rows (since 10 binary bits only can represent the integers 0 through 1023, while 11 binary bits can represent the integers 0 through 2047) of the pixel map, and similarly 11 bits are required to represent all of the 1792 columns of the pixel map.
- the memory capacity required to store the data signals corresponding to the 22 bit address signal therefore would be 4 megabytes. While a 22 bit address signal appears to be necessary to represent the addresses of all of the pixels of image, very clearly there are not 2 22 (4 megabytes) of information to be stored. Use of 4 megabytes of storage memory in the example given clearly will provide excess storage.
- an improved but simple device is provided, without the need of look up tables, multipliers or other complicated logic, for converting the address signal of a predetermined number of bits, representive of all of the pixel locations of the pixel map, to an address signal compatible with conventionally sized storage memory of the smallest permissible capacity which can be illustrated by the memory map X p by Y q shown in FIG. 2.
- the capacity of the storage memory required can actually be reduced. In the example given above since the number of data signals to be stored is less than 2 megabytes the minimum memory storage capacity can be reduced in half.
- the foregoing is preferably accomplished by using (A) the same address signals representative of the positions of the storage memory map which directly correspond to and represent the same address positions in the pixel map, respectively shown unshaded in FIGS. 1 and 2, and (B) the address signals representative of the locations of the "holes" in the map of storage array (shown shaded in FIG. 2) to store the pixel information at address locations of the pixel map which do not directly correspond to any locations of the storage array (shown shaded in FIG. 1).
- the holes located in a particular memory map must be equal to or greater than the number of locations of the pixel map which do not directly correspond to positions in the memory map.
- the maximum number of rows of the pixel map (1152) can be represented by the number 2 a +b
- the maximum number of columns of the pixel map (1792) can be expressed by the number 2 d +e, wherein a, b, d and e are whole integers.
- 1024*256 (264,444) locations (of holes) provided by the additional columns of the memory map exceeds the additional 128*1792 (229,376) locations provided by the additional rows of the pixel map (shown shaded in FIG. 1).
- the memory map of FIG. 2 (as chosen) is provided with more columns and fewer rows than that of the pixel map (instead of fewer columns and more rows) has to do with the nature of the state of the bits in the address field of the address signal representative of all of the locations of the pixel map.
- the most significant bit of the X field will be a binary 1 when the column number equals or exceeds 1023 and similarly the most significant bit of the Y field will be a binary 1 when the row number equals or exceeds 1023. Accordingly, therefore, when the most significant bit in the Y field is a binary 1, the address will necessarily have to correspond to the shaded area of FIG. 1.
- the bit(s) in the address field which are in a binary 1 state when designating all of the pixel positions of the pixel map not having direct corresponding positions in storage map chosen are used to indicate that fact, and for the purposes herein, can be termed the "switching" bit(s).
- the switching bit(s) Whether the highest order bit(s) of the address field representative of the rows of the pixel map or the highest order bit(s) of the address field representative of the columns of the pixel map are chosen as the switching bit(s) is dependent upon which field has a greater potential for missing terms (i.e., bits which are always in a binary zero state) when the corresponding switching bit(s) are in binary 1 state.
- the address locations of the pixel map where Y n exceeds 1023 are preferably mapped into the area of the memory map where X p exceeds 1791, as shown in FIGS. 1 and 2. It will be evident that in mapping the address in this manner the 22 bit signal used to represent the locations in the pixel map of FIG. 1 can be translated to a 21 bit address signal to represent locations in the memory map of FIG. 2.
- the first 11 bits of the input address signal, X 0 . . . X 10 represent the position of the column X m , i.e., 0 to 1791, of the pixel map shown in FIG. 1.
- the second 11 bits of the input address signal, Y 0 . . . Y 10 represent the position of the row Y n , i.e., 0 to 1151, of the pixel map shown in FIG. 1.
- the signal is typically provided over a bus in a manner well known in the art.
- the total input address signal corresponding to the pixel map X m by Y n therefore contains 22 bits.
- the system shown in FIG. 3 is connected to provide the 21 bit RAM address signal, corresponding to the X p by Y q map of FIG. 2, wherein the first 11 bits represent the 2048 rows of Y q and the last 10 bits represent the 1024 X p columns.
- the multiplexor 30 is connected to provide the remaining 9th through 11th and the 19th through the 21st bits of the 21 RAM address signal to the RAM 20 as a function of the state of the switching bit Y 10 .
- the multiplexor 30 is shown as a 2 to 1 multiplexor, which, for example, may be a pair of quad 2 to 1 multiplexors designated as 74157 such as those manufactured and sold by Texas Instrument Corporation, of Dallas, Tex., although it should be appreciated that other devices, such as a single Field Programmable Logic Device, can be used. As shown in FIG.
- the inputs for the 8th through 10th bits of the address field (X 8 , X 9 and X 10 ) are respectively connected to the 1A, 2A, and 3A inputs of multiplexor 30.
- the X 8 , X 9 and X 10 bit inputs are also provided to the respective 4B, 5B and 6B inputs of the multiplexor 30.
- Inputs 1B, 2B, and 3B are connected through resistor 40 to a voltage source so as to provide a binary logic one signal to those input terminals.
- the inputs for the 18th through 20th bits of the address field (Y 7 , Y 8 , Y 9 ) are connected respectively to the 4A, 5A and 6A input terminals of multiplexor 30.
- the 22nd bit of the field, (Y 10 ) is provided to the select input of the mu device 30.
- the 1C, 2C, 3C, 4C, 5C and 6C outputs of the device 30 are connected to the 8th, 9th and 10th, 18th, 19th and 20th inputs (respectively the three most significant bits, the 9th, 10th and 11th bits of the pattern of the address field representative of Xp of the RAM address, and the three most significant bits, the 8th, 9th and 10th bits of the portion of the field representative of Yq of the RAM address) of the RAM 20.
- the select input of multiplexor is a binary 0
- the 1A-6A inputs of the device are connected respectively to the 1C-6C outputs of the device
- the select input of the multiplexer is a binary 1
- the 1B-6B inputs of the device are connected respectively to the 1C-6C outputs of the device.
- the device will carry out the conditions described for the two address fields (4) and (5) above, as a function of the state of the switching bit Y 10 .
- the first eight address bits of X p are the same as the first eight address bits of X m and the first seven address bits of Y q are the same as the first seven address bits of Y n .
- the A inputs of the multiplexor are connected to the output of the device so that the 8th, 9th, 10th, 19th, 20th and 21st bits of the address signal applied to the RAM 20 are the X 8 , X 9 , X 10 , Y 7 , Y 8 and Y 9 bits, respectively, of the pixel map as required by the field (4), above.
- the input signals at the 1B, 2B and 3B inputs of the multiplexor 30 will be provided through the 1C, 2C and 3C outputs of the device to the 8th, 9th and 10th bit address inputs of the RAM 20, i.e., the 8th, 9th and 10th bits of the address input of RAM 20 are all forced to a binary one.
- the 8th-10th X m bits will be provided through the multiplexor to the 19th, 20th and 21st bits of the RAM address, all as required by the address field (5) above.
- the 22 bit X m by Y n address is effectively transformed into a 21 RAM address representative of the 2 11 by 2 10 , i.e., 2048 by 1024 (X p by Y q ), storage map.
- the storage capacity required to store the pixel infomation of the map shown in FIG. 1 is therefore reduced from 4 megabytes to 2 megabytes with the use of a simple multiplexor.
- the present invention can be easily used with other maps and address fields so long as a sufficient number of holes exists in the map of the storage memory used to store that information corresponding to positions in the pixel map which do not directly correspond to positions in the memory map.
- X and Y can be represented as follows:
- the address locations of the pixel map are therefore represented by a 10 bit number for X and a 9 bit number for Y so as to provide a 19 bit address field.
- the present invention can be utilized with the most significant bit of X, i.e., X 9 , being used as the switching bit.
- the translated 18 bit address field therefore becomes:
- Both fields (6) and (7) provide an 18 bit address field from a 19 bit address field.
- the total hardware requirements to carry out the translation from the 19 bit address to the 18 bit address will be a multiplexor for four 2:1 multiplexed bits, in a manner similar to that shown in FIG. 3.
- pixel map which is commonly used provides a 1152 by 896 array.
- the pixel map has X values which vary from 0 to 1151 and Y values which vary from 0 to 895.
- the maximum value of X and Y can be represented as follows:
- the address locations of the pixel map are therefore represented by an 11 bit number for X and a 10 bit number for Y so as to provide a 21 bit address field.
- the present invention can be utilized with the most significant bit of X, i.e., the X 10 bit, being used as the switching bit.
- the translated 20 bit address field therefore becomes:
- X 10 is one, it is clear that the X 9 , X 8 and X 7 bits will always be zero since they contain no needed information to express the numbers between 1024 and 1151. Accordingly, these numbers will correspond to the position of holes in memory storage and can be used to store data provided from positions not having a direct one to one correspondence. This is accomplished by forcing the bits in the field positions of Y 9 , Y 8 and Y 7 to binary 1, and transposing the original Y 9 , Y 8 and Y 7 bits into the original X 9 , X 8 and X 7 bit field positions of the address field applied to the RAM when the switching bit X 10 is one.
- the address field for the 20 bit address becomes:
- Both fields (8) and (9) provide a 20 bit address field from a 21 bit address field.
- the total hardware requirements to carry out the translation from the 21 bit address to the 20 bit address will be a multiplexor for six 2:1 multiplexed bits, in a manner similar to that shown in FIG. 3.
- the invention provides an inexpensive technique of translating address signals for graphic data in a simple, inexpensive way, without resorting to expensive memory devices for storing translation lookup tables.
- the objects of the invention require a simple device, such as a multiplexor, to minimize the use of logic circuitry.
- the device further minimizes the amount of memory capacity necessary to store data resulting in the economic use of space on the logic card in the device with which the invention is employed.
Abstract
Description
Claims (8)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/008,848 US4758996A (en) | 1987-01-30 | 1987-01-30 | Address translator |
AU12952/88A AU1295288A (en) | 1987-01-30 | 1988-01-29 | Address translator |
PCT/US1988/000274 WO1988005956A1 (en) | 1987-01-30 | 1988-01-29 | Address translator |
JP63501764A JPH02502047A (en) | 1987-01-30 | 1988-01-29 | address translator |
CA000557798A CA1299766C (en) | 1987-01-30 | 1988-02-01 | Address translator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/008,848 US4758996A (en) | 1987-01-30 | 1987-01-30 | Address translator |
Publications (1)
Publication Number | Publication Date |
---|---|
US4758996A true US4758996A (en) | 1988-07-19 |
Family
ID=21734042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/008,848 Expired - Lifetime US4758996A (en) | 1987-01-30 | 1987-01-30 | Address translator |
Country Status (5)
Country | Link |
---|---|
US (1) | US4758996A (en) |
JP (1) | JPH02502047A (en) |
AU (1) | AU1295288A (en) |
CA (1) | CA1299766C (en) |
WO (1) | WO1988005956A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4899272A (en) * | 1987-10-23 | 1990-02-06 | Chips & Technologies, Inc. | Addressing multiple types of memory devices |
US4985871A (en) * | 1989-11-13 | 1991-01-15 | Chips And Technologies, Inc. | Memory controller for using reserved dram addresses for expanded memory space |
US5040153A (en) * | 1987-10-23 | 1991-08-13 | Chips And Technologies, Incorporated | Addressing multiple types of memory devices |
US5051889A (en) * | 1987-10-23 | 1991-09-24 | Chips And Technologies, Incorporated | Page interleaved memory access |
US5247655A (en) * | 1989-11-07 | 1993-09-21 | Chips And Technologies, Inc. | Sleep mode refresh apparatus |
US5412611A (en) * | 1992-03-17 | 1995-05-02 | Fujitsu, Limited | FIFO memory device capable of writing contiguous data into rows |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0379778A3 (en) * | 1989-01-23 | 1990-10-31 | Eastman Kodak Company | Virtual memory management arrangement for addressing multi-dimensional arrays in a digital data processing system and method therefor |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4677594A (en) * | 1984-01-31 | 1987-06-30 | Commissariat A L'energie Atomique | Addressing circuit for a matrix display incorporating shift registers formed from static memories and addressing process using such a circuit |
US4701886A (en) * | 1984-08-22 | 1987-10-20 | Hitachi, Ltd. | Semiconductor integrated circuit device |
-
1987
- 1987-01-30 US US07/008,848 patent/US4758996A/en not_active Expired - Lifetime
-
1988
- 1988-01-29 WO PCT/US1988/000274 patent/WO1988005956A1/en unknown
- 1988-01-29 JP JP63501764A patent/JPH02502047A/en active Pending
- 1988-01-29 AU AU12952/88A patent/AU1295288A/en not_active Abandoned
- 1988-02-01 CA CA000557798A patent/CA1299766C/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4677594A (en) * | 1984-01-31 | 1987-06-30 | Commissariat A L'energie Atomique | Addressing circuit for a matrix display incorporating shift registers formed from static memories and addressing process using such a circuit |
US4701886A (en) * | 1984-08-22 | 1987-10-20 | Hitachi, Ltd. | Semiconductor integrated circuit device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4899272A (en) * | 1987-10-23 | 1990-02-06 | Chips & Technologies, Inc. | Addressing multiple types of memory devices |
US5040153A (en) * | 1987-10-23 | 1991-08-13 | Chips And Technologies, Incorporated | Addressing multiple types of memory devices |
US5051889A (en) * | 1987-10-23 | 1991-09-24 | Chips And Technologies, Incorporated | Page interleaved memory access |
US5247655A (en) * | 1989-11-07 | 1993-09-21 | Chips And Technologies, Inc. | Sleep mode refresh apparatus |
US4985871A (en) * | 1989-11-13 | 1991-01-15 | Chips And Technologies, Inc. | Memory controller for using reserved dram addresses for expanded memory space |
US5412611A (en) * | 1992-03-17 | 1995-05-02 | Fujitsu, Limited | FIFO memory device capable of writing contiguous data into rows |
Also Published As
Publication number | Publication date |
---|---|
WO1988005956A1 (en) | 1988-08-11 |
CA1299766C (en) | 1992-04-28 |
JPH02502047A (en) | 1990-07-05 |
AU1295288A (en) | 1988-08-24 |
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