JPS60181034U - semiconductor wafer - Google Patents

semiconductor wafer

Info

Publication number
JPS60181034U
JPS60181034U JP6886384U JP6886384U JPS60181034U JP S60181034 U JPS60181034 U JP S60181034U JP 6886384 U JP6886384 U JP 6886384U JP 6886384 U JP6886384 U JP 6886384U JP S60181034 U JPS60181034 U JP S60181034U
Authority
JP
Japan
Prior art keywords
semiconductor wafer
view
alignment mark
scribe line
recorded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6886384U
Other languages
Japanese (ja)
Inventor
望月 泉
Original Assignee
クラリオン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クラリオン株式会社 filed Critical クラリオン株式会社
Priority to JP6886384U priority Critical patent/JPS60181034U/en
Publication of JPS60181034U publication Critical patent/JPS60181034U/en
Pending legal-status Critical Current

Links

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案による半導体ウェーハの平面図、第2図
は第1図に示すウェーハの一部の拡大平面図、第3図は
従来の半導体ウェーハの平面図、第4図および第5図は
アライメント作業を説明するための顕微鏡の視野を示す
図、第6図は誤ってアライメントされた半導体ウェーハ
の平面図、第7図は第6図に示すようにアライメントさ
れたときの顕微鏡の視野を示す図である。 1・・・半導体ウェーハ、2・・・ペレット、3・・・
スクライブ・ライン、4a、4b・・・顕微鏡の視野位
置、5・・・ヘアライン、6・・・アライメント・マー
ク位置、7・・・アライメント・マーク。
FIG. 1 is a plan view of a semiconductor wafer according to the present invention, FIG. 2 is an enlarged plan view of a part of the wafer shown in FIG. 1, FIG. 3 is a plan view of a conventional semiconductor wafer, and FIGS. 4 and 5. is a diagram showing the field of view of a microscope to explain the alignment work, Figure 6 is a plan view of an incorrectly aligned semiconductor wafer, and Figure 7 is a view of the field of view of a microscope when aligned as shown in Figure 6. FIG. 1... Semiconductor wafer, 2... Pellet, 3...
Scribe line, 4a, 4b...Field position of the microscope, 5...Hairline, 6...Alignment mark position, 7...Alignment mark.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体ウェーハ・スクライブ・ライン上にダイシング用
のアライメント会マークを具備することを特徴とする半
導体ウェーハ。
A semiconductor wafer characterized by having an alignment mark for dicing on a semiconductor wafer scribe line.
JP6886384U 1984-05-11 1984-05-11 semiconductor wafer Pending JPS60181034U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6886384U JPS60181034U (en) 1984-05-11 1984-05-11 semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6886384U JPS60181034U (en) 1984-05-11 1984-05-11 semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS60181034U true JPS60181034U (en) 1985-12-02

Family

ID=30604001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6886384U Pending JPS60181034U (en) 1984-05-11 1984-05-11 semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS60181034U (en)

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