JPS60180334A - Signal selection circuit - Google Patents

Abstract

PURPOSE:To attain function without malfunction even at a frequency where the phase shift between a signal to be switched and a control signal is large by using the signals to be switched in opposite phase with each other so as to apply switching timing and using a pulse erasure circuit. CONSTITUTION:A very thin pulse is caused at an output 137 of a selector from the variation of characteristics of a device due to variation in the manufacture process, this might be a cause to malfunction and the yield reduction of products. Then a pulse erasure circuit 108 is provided and the thin pulse is erased as shown in an output 141 of a signal selection circuit. That is, an output 139 as the result of delay by DELTAT from an output 137 of the selector through inverters 133, 134, and an output 137 are inputted to an NAND gate 124 and a pulse having a pulse width within the DELTAT is eliminated. Said pulse is erased from the output 141 of the signal selection circuit and correct operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to PLL (Phase Locked)
Signal selection circuits used in (Loop) circuits etc., especially (2
This invention relates to a signal switching device for a two-coefficient frequency divider of 1/2N (N is an integer) divided by N+1).

Structure of the conventional example and its problems FIG. 1 shows the structure of the conventional example. In the figure, 1 is a first % counter, 2 is a 20% counter, 3 is a counter, 4 is a signal selection circuit, 5 to 8 are inverters, 9 to 16
．． 31 is Nanto Game 1, 17゜18 is And Gate,
19 is Noah Gate.

Outputs of the first mechanical counter 1 having opposite phases to each other are connected to a popular belief selection circuit 4, the selected output is connected to a second % counter 2, and the output of the second % counter 2 is connected to a % counter 3 and a selected output is connected to a second % counter 2. , are connected to one input of the Nantes gate 9, respectively, and the output of the % counter 3 is connected to the other input of the Nantes gate 9. The output of the Nandt gate 9 is provided as one of the switching control inputs of the signal selection circuit 4 via the inverter 6. 26 is another switching control input.

The configuration of the signal selection circuit 4 will be explained below.

The three-person canant gates 15 and 16 form a reset flip-flop, a set of timing control manual inputs. A7, 17, 18 and 19 gates form a selector. The switching control input signal 26 is connected to the Nandts gate 11 and to the Nandts gate 10 via the inverter 6. The outputs of the inverter 5 are connected to the NAND games 1 and 10.11, respectively. The outputs of Nant gates 10 and 11 are connected to Nant gates 13 and 31 via inverters 7 and 8, respectively. The outputs of the Nant gates 13 and 31 are connected to the three-person Nant gate 15 forming a flip-flop.
and 16 input terminals, respectively. The positive and negative U' forces of this flip-frog are such that the output 29 of the NAND gate 15 is connected to the AND gate 17, and the output 28 of the NAND gate 16 is connected to the AND gate 18. And Gate 1 Ryo, 18 and Noah Gate 1
The output of the selector 9, that is, the output of the NOR gate 19, is connected to the Nandt gates 13 and 31 as an output signal 30 via the inverter 7.

Two output signals 2 of mutually opposite phases of the first % counter 1
1 and 22 are connected to AND gates 17 and 1B forming a selector.

an external switching control input signal 26 and an internal switching control input;
That is, at both outputs of inverter 5, % counter 1
The signal selection circuit 4 selects and outputs one of the outputs.

In total, this conventional example constitutes a counter that performs coefficient switching of 1/40 and 1/41.

Next, the operation of the conventional example will be explained using a timing chart.

FIG. 2 is a timing chart showing the timing of the main parts. In addition, each number waveform in this figure shows the signal waveform of each line part in FIG. 1, and 20 is the first%.
The input pulses of the counters, 21 and 22 are outputs with mutually opposite phases, 23 is the output of the signal selection circuit 4, 30 is the output of the inverter 7, 24 is the output of the 20% counter 2, 26
is the output of % counter 3, 26.27 is the switching control input collar 2
8 and 29 are the outputs of a flip-flop composed of 15 and 16 (3-person canand game).

7 l) Nofuriro knob output 28 is at “low” level,
When 29 is at the "high" level, the signal selection circuit's "U"
For the force, one of the first %carantuffs, the U'' force 21, is selected, and the output 23 has an opposite phase thereof.

At timing t4, the output 25 of % counter 3 becomes ``''
When the output 24 of the second white counter reaches the "high" level at timing t2,
At timing t3 when the output 30 of the impark 7 becomes high ``'', the input 27 of the flip-flop becomes ``low'' level due to the AND of the output signals 24, 25, and 30. At this time, the input 27 of the flip-flop becomes ``low'' level. The output 28 of is the power output 28. Furthermore, the output pulse width f of the first 54 counter 1 is delayed, and the other output 29 of the flip-flop reaches the 10'' level at timing t4. The output to the output 23 of the 10% counter 1 is switched from the output signal 21 of the 10% counter 1 to its opposite phase output signal 22.

That is, in the period T1 in FIG. 2, one output signal 21 of the first % counter 1 is selected and its inverted signal is output to the controller output 23, and the intercostal interval T2 is the same as that of the other output signal 21. Output signal 22 is selected and its inverted signal is output to selector output 23.

During the T3 period, the 23rd floor was at a "low" level.

Paying attention to the output signal 23 of the selector, the output selection of the first % counter 1 is switched from output 21 to output 22 at timing t4, and as a result, the "low" level continues twice, and the first The output 23 of the selector is shifted by one pulse of the input 2Q of the % counter. In addition, in the circuit shown in FIG. 1, the total count number of the system is 41, and a frequency division ratio of 1/41 is obtained.

The constraints on the operation of the conventional circuit are that the output signal 23 of the signal selection circuit 4 is delayed by the delay of the second % counter or the delay of the % counter, and by the delay of the Nant's gate 9, the inverter 5, the Nand's gate 11, or the Nand's gate. 10, Inverter 8 or Inverter Y and Nantes Gate 3
1 or even if it is delayed while passing through the Nantes gate 13, the total delay time is the output 21 of the first % counter.
, 22 periods or less. From this point of view,
Comparatively, such as CMO3 (bi-complementary field effect transistor),
High-speed operation becomes difficult for low-speed devices.

The disadvantages of the conventional example when the delay time described above becomes large will be described.

FIG. 3 shows a timing chart when the frequency becomes higher. The timing indicates the same points and uses the same numbers as in FIG. When the frequency increases and the phase of the output of the second % counter 2 changes at the timing t6 of the trailing edge of the °...I level of the output 3Q of the inverter 7, the output 27 of the Nant gate 31 changes at the timing t6 Parow”
′, and from this point the output 28 of 7 lithops becomes ′
At this time, the signal selection circuit 4
The output 23 of is already at the "high" level,
When the output 28 of the flip-flop becomes ``low'' and the output 29 becomes ``low'', 23 is ``low'', so it becomes ``low'' level at timing t6. Then, the output of the 10% counter 1 is switched from the output signal 21 to the output signal 22, and the output of the signal selection circuit 4 is pulsed at the timing 1..16 as shown in FIG. This may cause malfunction.

FIG. 4 shows a timing chart when the frequency becomes higher and the phase of the second % counter 2 is located at the trailing edge of the 'NO' level of the output 30 of the inverter 7. As in FIG. 3, the timing indicates the same points and uses the same numbers as in FIG. Since the flip-flop cannot be inverted, the outputs 28 and 29 of the flip-flop do not change, making it inoperable and making it impossible to switch signals.

As mentioned above, the conventional signal selection circuit is 0MO8.
If the speed of the device itself is slow, it will not be able to operate at high frequencies, and at high frequencies it will malfunction and eventually stop working.

FIG. 6 shows the frequency characteristics of a conventional signal selection circuit made of a CMO8 integrated circuit. In the figure, 32 is the frequency characteristic of the minimum operating power source, and the diagonally shaded area 33 is the malfunction area.

As mentioned above, conventional signal selection circuits are made of integrated circuits.
If so, the high frequency characteristics will be poor and malfunction will occur.

OBJECTS OF THE INVENTION The present invention provides a signal selection circuit suitable for integrated circuits, which eliminates these drawbacks of the prior art.

The present invention basically consists of an input terminal to which pulses of opposite phases are applied, first and second AND circuits, set/reset/flip-flow software with a timing control input, and the same. It includes a timing control means for controlling the output timing of the flip-flop, and a circuit having a selector and a pulse erasing means, and the outputs of the first and second AND circuits are connected to the set and reset inputs of the flip-flop. and connecting the output of the flip-flop to the timing control means, and connecting the forward and reverse outputs of the flip-flop to each control input terminal of the selector, and a pair of switched signal input terminals of the selector. , connect each of the pulse inputs having opposite phases to each other,
The output of the selector is transmitted to the first . This is a signal selection circuit connected to each input of the second AND circuit, thereby realizing a stable signal selection circuit that does not cause malfunctions during high-speed operation.

DESCRIPTION OF THE EMBODIMENT FIG. 6 shows the configuration of an embodiment of the present invention. In the same figure,
10Q is a first % counter, 1o1 is a second % counter, 102 is a % counter, and 103 is a signal selection circuit.

1, 104 is a first AND circuit, 105 is a second AND circuit, 106 is a flip-flop, 107 is a selector, and 108 is a pulse erasing circuit. In addition, 109-1
16 is an inverter, 116 to 124 are Nantes gates, 1
26.126 is an AND gate, and 127 is a NOR gate.

The output 131 of the % counter 102 becomes the switching control input of the signal selection circuit 103 together with 132, and the output 131 of the % counter 102 becomes the switching control input of the signal selection circuit 103
Connected to 6. The output of the Nandts gate 116 is connected via an inverter 110 to the Nandts gate 118. The other input of the Nandts gate 118 is the output 129 of the first % counter. The Nant gates 116 and 118 and the inverter 110 constitute the first AND circuit 104.

The switching control human power 131 is connected to the Nantes gate 117 together with the switching control human power 132 via the inverter 109, and the output is connected to the Nantes gate 117 via the inverter 111.
Connected to 19. Other inputs of Nantes Gate 119 are:
is the output 130 of the first % counter 100. The Nandt gates 117 and 119 and the inverter 111 constitute a second AND circuit 106.

Three-input Nant gates 122 and 123, seven flip-flops with timing control inputs.
06, the output 133 of the first AND circuit is connected to the Nant gate 122, and the output 134 of the second AND circuit is connected to the Nant gate 123.

The Nant gates 120 and 121 are timing control means and determine the timing at which the output of the flip-flop 106 changes.

The output of AND gates 125 and 126 is the NOR gate 127
The input of the AND gate 126 is connected to the output 1 of the flip-flop 106, and the AND gates 125', 126, and the NOR gate 127 constitute the selector 107.
36 and the output 130 of the first % counter 100, and the input of the AND gate 126 is the flip-flop 1o
6 output 134 and the first % counter 100 output 129
That is.

Output 137 of selector 107 is connected to inverter 113 .
114 to the Nantes gate 124. The output 4o of the Nant gate 124 is connected to the inverter 1
16, it becomes the output 141 of the signal selection circuit 103. Inverters 113, 114, 116 and NAND games 1-124 constitute a pulse erasing circuit 108. The output 141 of the signal selection circuit 103 is connected to the second % counter 101 and to the counter 102 .

Reference numeral 128 is an input of the 10% counter 100, and outputs 129 and 130 are respective outputs of the first % counter 100, which are pulses with opposite phases to each other.

The overall system shown in Figure 6 has a frequency division ratio of 1/40 and 1/40.
This constitutes a counter that performs 41 switchings.

Next, the operation of this embodiment will be explained using a timing chart.

FIG. 7 shows a timing chart of this embodiment.

128 is the input of the first % counter I), 129
.degree.130 are outputs having mutually opposite phases. 137 is the output of the selector 107, and 139 is the output of 107 delayed by the inverters 113 and 114. 140 is the output 10γ of the selector and the NAND output of 139. 14
1 is the output of the signal selection circuit. 131 is the output of the counter 102, which together with 132 is a switching control input of the signal selection circuit.

At this timing, the control human power 132 is at the Noi'' level,
This shows the timing of switching between pulses 129 and 130, which are in phase opposite to each other.

133 is the output of the first AND circuit 1Q4. 13
5 and 136 are the outputs of the flip-flop 106.

When the switching control power 131 reaches the 01 ``high'' level at the timing t, the output 129 of the first % counter 100 takes the timing, and the output 133 of the first fault 1 product circuit 104 reaches the timing t1. At ゜2, it becomes a ``low'' level. tl. At timing 2, one output 136 of the flip-flop 106 goes to the ``high'' level, and the Nant gate 121, which controls the output timing of the flip-flop 70 described above, outputs the output timing of the flip-flop 70 at timing tl.3. The other output 136 of the chip 106 goes to the "low" level.

During the period of T101 until t1o2, the Norinobu flop is 10
When one output 136 of 6 is at the "low" level and the other output 136 is at the "no" level, the output 129 of the first % counter is selected and output to the output 137 of the selector 107, and the tl. During the period T103 from 2 to t103, the outputs of the flip-flop 106 are both at the "high" level, and the output 137 of the selector 107 is at the "low" level.

When the output 136 of the flip-flop 106 becomes a low level at timing t103, the period of TlO2 is as follows.
The output 129 of the first % counter is switched to 130 and output to the output 137 of the selector 107.

Output 137 of selector 107 is connected to inverter 113 .
114, the output of the NAND gate) 124 and the inverter 116 is delayed by ΔT, and the ΔT signal selection circuit 103
Focusing on the output of tl. After the timing of 3, the "low level" continues and the first % counter reaches 100.
The input 128 is shifted by one pulse, and the count number of the system body becomes 41, obtaining a frequency division ratio of 1/41.

The above has described the timing of switching from signals 129 to signals 130 having mutually opposite phases when the switching control human power 132 is at the NO.I'' level.

When the switching control input 132 is at the "low" level, the signals 130 with mutually opposite phases are switched to 129. The output 136 of the flip-flop becomes the "high" level, and from this point on, the signals 130 with opposite phases are switched to the signals 129 with opposite phases. , 129, 13
By combing by one pulse of 0, the output of the Norinobu flop is 13
6 becomes the °°low'' level, which, like the switching output described above, is left by one pulse of the input 128 of the first % counter 100, obtaining a frequency division ratio of 1/41 as described above.

Next, the operation of this embodiment at high frequencies will be explained using a timing chart.

FIG. 8 shows a timing chart when the frequency increases and the timing at which the switching control input 131 reaches the "high" level is located at the trailing edge of the level of the output 129 of the first % counter. The points of interest are the same as in Figure 7, and the same numbers are used.

At a timing of 11°4, when the switching control power 131 is at the NO level and the output 133 of the first AND circuit 104 is at the low level, from this point on, the flip-flop The output 136 of the pull-up 106 is
At this timing, the first AND circuit 1 uses the output 129 of the first % counter.
The timing of 04 is controlled, and then 129 is output to the output 13 of the selector circuit 107. However, due to variations in device characteristics due to variations in the manufacturing process, the selector output 13
7. Extremely thin pulses as shown in FIG. 8 may be generated, which may cause malfunctions and reduce product yield.

Therefore, in the present invention, the pulse erasing circuit 10B shown in FIG.
The output 141 of the signal selection circuit shown in FIG. 8 eliminates this thin pulse.

The output 137 of the selector is passed through inverters 133 and 134, and the output 139 delayed by ΔT and 137 are input to the Nandt gate 124 to eliminate pulses with a pulse width of 41 or less. At the output 141 of the signal selection circuit, the above-mentioned pulses are eliminated and correct operation is performed.

The timing at which the frequency further increases and the switching control human power 131 reaches the "high" level is determined by the first % counter 100.
FIG. 9 shows a timing chart for the case where the output 129 is located at the further trailing edge of the 1° high" level. The timing is at the same point of interest as in FIG. 7, and the same numbers are used.

In this case, the pulse width of the output 133 of the first AND circuit 104 becomes very small, and at timing t1.5,
The output 136 of flip-flop 106 cannot be changed.

However, the pulse width of the switching control human power 131 is equal to two cycles of the output 129°130 of the first % counter 100, and t
At the timing 1o6, the output 133 of the second AND circuit IQ4 goes to the "low" level again. At this timing, one output 136 of the flip-flop 106 goes to the "high" level, and the output 133 of the second AND circuit IQ4 becomes the "high" level. At 7, the other output 136 goes to the low level. The output of the selector 107 becomes the output 1 of the first % counter 100 at timing t107.
It is switched from 29 to 130 and output, and the pulse cancellation circuit 1
08 and becomes the output of the signal selection circuit 103.

The signal selection circuit of the present invention operates well even at high frequencies, as described above.

Effects of the Invention According to the present invention, by controlling the switching timing using switched signals having mutually opposite phases and using a pulse cancellation circuit, even at frequencies where the phase shift between the switched signal and the control signal becomes large, Products that function without malfunction can be provided with a high yield, and even at frequencies where the phase shift becomes large, the pulse width of the switching control input can be made at least twice the period of the signals to be switched that are in opposite phases to each other. , it is possible to provide a signal selection circuit that operates well and exhibits good high frequency characteristics even when using a relatively slow device such as 0.times.08.

[Brief explanation of drawings]

Fig. 1 is a conventional configuration diagram, Fig. 2 is a timing diagram of the conventional configuration, Fig. 3 is a timing diagram of high frequency operation in the conventional configuration, and Fig. 4 is a timing diagram explaining the operating limits of the conventional configuration. , FIG. 5 is a frequency characteristic diagram of the conventional configuration, FIG. 6 is a configuration diagram of the embodiment of the present invention, FIG. 7 is a timing diagram of the configuration of the embodiment of the present invention, and FIG. 8 is a high frequency operation of the configuration of the embodiment of the present invention. FIG. 9 is a timing diagram illustrating an example of high frequency operation of the configuration of the embodiment of the present invention. 1. 2, 100, 101...% counter, 3°102... counter, 4, 103...-
...Signal selection circuit, 1o4...First AND circuit, 106...-Second AND circuit, 106...
...Set with timing control input, reset flip-flop, 107 ...Selector, 108
...Pulse erasure circuit. Figure 1 Figure 2? 7t T3. T2 Figure 3 11 d6 Figure 4 Figure 5, ? 3th / /h kakunta input m wave number (pa jh) Fig. 6 1ρ, ? Fig. 7 fJ2 116/ 1qr2 1μJ 2 ! /64

Claims (1)

[Claims] an input terminal to which pulses having mutually opposite phases are applied;
, and a second AND circuit, a cent, reset flip-flop with a timing control input, and a second AND circuit with a timing control input;
It is equipped with a timing control means for controlling the output timing of the 0-tube, and a circuit having a selector and a pulse erasing means, and each output of the first and second AND circuits is set and reset for the flip 70-tube. The output of the flip-flop is connected to the timing control means, and the forward and reverse outputs of the flip-flop are connected to each control input terminal of the selector, and the output of the flip-flop is connected to the control input terminal of the selector. The respective pulse inputs having mutually opposite phases are connected to the signal input terminal, and the output of the selector is connected to the first... A signal selection circuit connected to each input of the second AND circuit.