JPS6017961A - Manufacture of semiconductor controlled rectifier - Google Patents
Manufacture of semiconductor controlled rectifierInfo
- Publication number
- JPS6017961A JPS6017961A JP12745783A JP12745783A JPS6017961A JP S6017961 A JPS6017961 A JP S6017961A JP 12745783 A JP12745783 A JP 12745783A JP 12745783 A JP12745783 A JP 12745783A JP S6017961 A JPS6017961 A JP S6017961A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor layer
- gold
- layer
- lifetime killer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000010931 gold Substances 0.000 claims abstract description 19
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052737 gold Inorganic materials 0.000 claims abstract description 18
- 230000001681 protective effect Effects 0.000 claims abstract description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 7
- 239000011574 phosphorus Substances 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 229910052681 coesite Inorganic materials 0.000 claims abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract 2
- 229910052682 stishovite Inorganic materials 0.000 claims abstract 2
- 229910052905 tridymite Inorganic materials 0.000 claims abstract 2
- 239000000126 substance Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000010408 film Substances 0.000 claims 7
- 239000000758 substrate Substances 0.000 claims 3
- 239000010409 thin film Substances 0.000 claims 2
- 230000004888 barrier function Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229960001231 choline Drugs 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000009826 distribution Methods 0.000 abstract description 6
- 238000009827 uniform distribution Methods 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 239000006104 solid solution Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 19
- 239000007787 solid Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体制御整流素子の製造方法に係り、特に
そのギヤリヤのライフタイムキラーの導入方法の改良に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor-controlled rectifying element, and particularly to an improvement in a method for introducing a lifetime killer into a gear.
第１図はここで対象とする半導体制御整流素子の一例の
構造を示す断面図で、（１）はｎ形ベース（ｎＢ）層、
（２）はｐ形ベース（ｐＩり層、（３）はｐ形エミッタ
（ｐ、） Ｎ 、 （４＋はｎ形エミッタ（ｎ８）層、
（６）にカソード電極、（６）はアノード電極、（７）
はゲート電極、Ｊｌはｎ２層（４）とｐＢ層（２）との
接合、Ｊ２はｐＢ層（２）とｎＢＢｉ１２との接合、Ｊ
３はｎＢ層（１）とｐＥ Ｎ（：ｌ）との接合である。FIG. 1 is a cross-sectional view showing the structure of an example of the semiconductor-controlled rectifying element targeted here, in which (1) is an n-type base (nB) layer;
(2) is p-type base (pI layer), (3) is p-type emitter (p, ) N, (4+ is n-type emitter (n8) layer,
(6) is a cathode electrode, (6) is an anode electrode, (7)
is the gate electrode, Jl is the junction between the n2 layer (4) and the pB layer (2), J2 is the junction between the pB layer (2) and nBBi12, and J
3 is a junction between the nB layer (1) and pE N (:l).
この半導体制御整流素子の構成および動作は周知で、こ
れ以上の説明は必要ｔｒいであろう。The structure and operation of this semiconductor controlled rectifier are well known and no further explanation is necessary.
サテ、シリコンを用いた制御整流素子にオイテそのキャ
リヤーライフタイム（以下単に「ライフタイム」という
。）を制御するために金（Ａｕ）などのライフタイムキ
ラーをドープすることが広く行なわれている。そして、
その従来のドープの方法はライフタイムキラーをシリコ
ンの表面に付着させた後、１回の熱処理で素子にライフ
タイムキラーを拡散させるものであった。It is widely practiced to dope a controlled rectifying element using silicon with a lifetime killer such as gold (Au) in order to control its carrier lifetime (hereinafter simply referred to as "lifetime"). and,
The conventional doping method was to attach the lifetime killer to the silicon surface and then diffuse the lifetime killer into the device through a single heat treatment.
このような従来の方法では、素子中の各半導体層におけ
るライフタイムキラー物質の拡散速度や固溶度を考慮せ
ずに拡散していたので、結果として拡散後のライフタイ
ムキラーの分布は不均一なものとなる。In this conventional method, the lifetime killer substance was diffused without considering the diffusion rate or solid solubility of each semiconductor layer in the device, and as a result, the distribution of the lifetime killer substance after diffusion was uneven. Become something.
例えば、シリコン制御整流素子にライフタイムキラーと
して金を利用した場合、ｎ０層（４）の不純物にリンを
用いていると、ｎ２層（４）の近傍には金はリンのゲ／
ター効果によって、その濃度は低くなり、逆に、ｎＴＡ
層（４）から離れた領域、例えばｐＢ層（２）やｐ。Ｎ
（３）の近傍でその濃度が高くなる。その結果、ライフ
タイムキラーとしての金の分布は第２図に示すように極
めて不均一なものとなり、オン電圧の過度の上昇、高温
での電圧印加時のリーク電流の過度の上昇をまねくこと
になる。For example, when gold is used as a lifetime killer in a silicon-controlled rectifying element, if phosphorus is used as an impurity in the n0 layer (4), the gold is in the vicinity of the n2 layer (4).
Due to the TA effect, its concentration decreases, and conversely, nTA
Regions away from layer (4), such as pB layer (2) or p. N
The concentration increases near (3). As a result, the distribution of gold, which acts as a lifetime killer, becomes extremely uneven as shown in Figure 2, leading to an excessive increase in on-voltage and an excessive increase in leakage current when voltage is applied at high temperatures. Become.
この発明は以上のような点に鑑みてなされたもので、ラ
イフタイムキラーのドーピングに際１７てドーピング速
度、固溶度が小さくなる部分以外に保護膜を形成してド
ーピングをした後に、この保護膜を除いて他の部分より
低温でドーピングを行うことによって素子全体として、
均一なライフタイムキラーのドーピングプロファイルを
得て、特性のよい半導体制御整流素子を実現する方法を
提供するものである。This invention was made in view of the above-mentioned points. When doping a lifetime killer, a protective film is formed in areas other than the areas where the doping rate and solid solubility are reduced. By performing doping at a lower temperature than other parts except for the film, the entire device is
The present invention provides a method for obtaining a uniform lifetime killer doping profile and realizing a semiconductor-controlled rectifier with good characteristics.
第３図Ａ〜０はこの発明の一実施例を説明するための各
段階における状態を示す断面図、第４図はその各段階で
のライフタイムキラーとしての金のドーピングプロファ
イルを示す図である。オす、第３図Ａに示すようにリン
が使用されているシリコン制御整流素子のｎ１１Ｍ（４
）の表面を除いて、りンケツタ一層またはシリコン酸化
（８１０２）膜のようなライフタイムキラーに対する保
護膜（８）を設けた状態で、高温で０１層（４１の近傍
領域（９）に金をドーピングする。これによって、第４
図に破線で示す曲線（イ）のような金の濃度分布を得る
。次に第３図Ｂに示すように保護膜（８）を除去した後
に上記温度より低い温度で第３図Ｃに示すように他の領
域（１０）に金をドーピングする。このときドーピング
される金の濃度分布は第４図に一点鎖線で示す曲線（ロ
）のようになる。従って、上記２回のドーピングによる
金の濃度は第４図の両凸線（イ）、（ロ）の和で、実線
で示す曲線（ハ）のようになり、均一な分布が得られる
。FIGS. 3A to 3A-0 are cross-sectional views showing the state at each stage for explaining an embodiment of the present invention, and FIG. 4 is a diagram showing the doping profile of gold as a lifetime killer at each stage. . As shown in Figure 3A, the silicon-controlled rectifier using phosphorus is
) with a protective film (8) against lifetime killers such as a single layer of linker or a silicon oxide (8102) film, gold was applied to the region (9) near the 01 layer (41) at high temperature. doping.This makes the fourth
A gold concentration distribution as shown by the broken line in the figure (A) is obtained. Next, as shown in FIG. 3B, after removing the protective film (8), gold is doped into another region (10) as shown in FIG. 3C at a temperature lower than the above temperature. The concentration distribution of the doped gold at this time becomes a curve (b) shown by a dashed line in FIG. Therefore, the gold concentration resulting from the two doping steps described above is the sum of the double convex lines (A) and (B) in FIG. 4, and becomes as shown by the solid curve (C), resulting in a uniform distribution.
なお、以上ｐゲート素子を対象として説明１〜だが、ｎ
ゲート素子についてもこの発明を適用できることは勿論
である。Note that although the explanations above have been made with reference to p-gate devices, n
Of course, the present invention can also be applied to gate elements.
以上説明したように、この発明では半導体制御整流素子
のリンを不純物として用いているｎ影領域以外の部分の
表面にライフタイムキラー物質の拡散を防止する膜を形
成したのち、所要の温度でライフタイムキラー物質全拡
散し、その後に上記膜を除去して素子全体に上記温度よ
り低い温度でライフタイムキラー物質を拡散するように
したので、素子全体Ｇこわたってライフタイムキラー物
質の均一な分布が得られ、特性のよい半導体制御整流素
子が得られる。As explained above, in the present invention, a film is formed on the surface of the semiconductor-controlled rectifying element other than the n-shaded area where phosphorus is used as an impurity to prevent the diffusion of the lifetime killer substance, and then the life-time killer substance is dried at the required temperature. The time killer substance is fully diffused, and then the film is removed to diffuse the lifetime killer substance throughout the device at a temperature lower than the above temperature, so that the lifetime killer substance is uniformly distributed throughout the device. Thus, a semiconductor-controlled rectifying element with good characteristics can be obtained.
第１１図はここで対象とする半導体制御整流素子の一例
の構造を示す断面図、第２図は従来方法によって、ライ
フタイムキラーとしての金をドーピングしたときのドー
ピングプロファイルを示す図、第３図はこの発明の一実
施例を説明するだめの各段階における状態を示す断面図
、第４図はこの実施例における各段階０こおける金のド
ーピングプロファイルを示す図である。
図において、（１）はｎｎ層（第１半導体層）、（２）
はｐＢｆ￥１＜第２半導体層） 、（３）はｐ、層（第
３半導体層）、（４）はｎ、 Ｍ （第４半導体層）、
（５）はカソード電極（主電極） 、［６１はアノード
電極（主電極）、（７）はゲート１に極、（８）は保股
膜である。
なお、図中同一符号は同一またけ相当部分を示す０
代理人 大岩増雄
第１図
厚さ方向の位置
（〕
２７９−
一勺誌・峡Fig. 11 is a cross-sectional view showing the structure of an example of the semiconductor-controlled rectifier element targeted here, Fig. 2 is a view showing the doping profile when gold is doped as a lifetime killer by the conventional method, and Fig. 3 4 is a sectional view showing the state at each stage for explaining an embodiment of the present invention, and FIG. 4 is a diagram showing the doping profile of gold at each stage 0 in this embodiment. In the figure, (1) is the nn layer (first semiconductor layer), (2)
is pBf\1<second semiconductor layer), (3) is p layer (third semiconductor layer), (4) is n, M (fourth semiconductor layer),
(5) is a cathode electrode (main electrode), 61 is an anode electrode (main electrode), (7) is an electrode for gate 1, and (8) is a protective film. In addition, the same reference numerals in the figures indicate parts corresponding to the same straddle. Agent Masuo Oiwa Figure 1 Position in the thickness direction
Claims (1)
の半導体層の両王面にそれぞれ接して形成されたｐ（ま
たはｎ）形の第２半導体層および第３半導体層と、」二
記１ｊｌＴ、２半導体層の玉表面部の一部に形成された
ｎ（ｉたはｐ）形の第４半導体層とからなる半導体制御
整流素子基体の」二記各半導体層のｐ形の部分の表面上
にライフタイムキラー物質の拡散を妨げる保誰膜を形成
した後に、上記ライフタイムキラー物質を−に記保護膜
で侍われない部分に所要の第１の温度で熱拡散し、その
後に上記保護膜を除去し、上記素子基体の全表面から上
記ライフタイムキラー物質を上記第１の温度」；り低い
第２の温度で熱拡散し、その後に上記第３半導体層およ
び第４半導体層の主表面にそれぞれ圧電極を、上記第２
半導体層の露出主表面にゲート電極を形成することを特
徴とする半導体制御整流素子の製造方法。 （２）素子基体がシリコンからなり、ｎ形の半導体層の
導電形を形成する不純物がリンであることを特徴とする
特許請求の範囲第１項記載の半導体制御整流素子の製造
方法。 （３） ライフタイムキラー物質として金を用いること
を特徴とする特許請求の範囲第１項または第２項記載の
半導体制御整流素子の製造方法。 （４）保護膜に酸化シリコン（Ｓ１０２）膜を用いるこ
とを特徴とする特許請求の範囲第１項、第２項または第
３項記載の半導体制御整流素子の製造方法０ （５）保護膜に高濃度Ｇこリンを含む半導体薄膜を用い
ることを特徴とする特許請求の範囲第１項。 第２項または第３項記載の半導体制御整流素子の製造方
法。 （６）保護膜に高濃度にリンを含む半導体薄膜と酸化シ
リコン膜とを併用することを特徴とする特許請求の範囲
第１項、第２項または第３項記載の半導体制御整流素子
の製造方法。[Claims] (lln (i or p) type), a semiconductor layer,
a p (or n) type second semiconductor layer and a third semiconductor layer formed in contact with both royal surfaces of the semiconductor layer, respectively; A barrier film that prevents the diffusion of the lifetime killer substance is provided on the surface of the p-type portion of each semiconductor layer of the semiconductor control rectifier substrate comprising a fourth semiconductor layer of the n (i or p) type. After the formation, the lifetime killer substance is thermally diffused at a required first temperature to the areas not covered by the protective film, and then the protective film is removed and the lifetime killer substance is removed from the entire surface of the element substrate. The time killer substance is thermally diffused at a second temperature lower than the first temperature, and then piezoelectrodes are provided on the main surfaces of the third semiconductor layer and the fourth semiconductor layer, respectively.
1. A method of manufacturing a semiconductor-controlled rectifying element, comprising forming a gate electrode on an exposed main surface of a semiconductor layer. (2) The method for manufacturing a semiconductor-controlled rectifying element according to claim 1, wherein the element substrate is made of silicon and the impurity forming the conductivity type of the n-type semiconductor layer is phosphorus. (3) A method for manufacturing a semiconductor-controlled rectifying element according to claim 1 or 2, characterized in that gold is used as the lifetime killer substance. (4) Method 0 for manufacturing a semiconductor-controlled rectifying element according to claim 1, 2 or 3, characterized in that a silicon oxide (S102) film is used as the protective film. Claim 1, characterized in that a semiconductor thin film containing a high concentration of G-choline is used. A method for manufacturing a semiconductor-controlled rectifier according to item 2 or 3. (6) Manufacturing a semiconductor-controlled rectifying element according to claim 1, 2, or 3, characterized in that a semiconductor thin film containing a high concentration of phosphorus and a silicon oxide film are used together as a protective film. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12745783A JPS6017961A (en) | 1983-07-11 | 1983-07-11 | Manufacture of semiconductor controlled rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12745783A JPS6017961A (en) | 1983-07-11 | 1983-07-11 | Manufacture of semiconductor controlled rectifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6017961A true JPS6017961A (en) | 1985-01-29 |
Family
ID=14960398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12745783A Pending JPS6017961A (en) | 1983-07-11 | 1983-07-11 | Manufacture of semiconductor controlled rectifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6017961A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0628991A1 (en) * | 1993-06-08 | 1994-12-14 | Kabushiki Kaisha Toshiba | Semiconductor device having reduced carrier lifetime and method of manufacturing the same |
| DE102004047626A1 (en) * | 2004-09-30 | 2006-04-13 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Thyristor, has semiconductor body with external area that is adjacent to internal area, where charge carrier rating life monotonically decreases within external area with increased separation distance of internal area |
-
1983
- 1983-07-11 JP JP12745783A patent/JPS6017961A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0628991A1 (en) * | 1993-06-08 | 1994-12-14 | Kabushiki Kaisha Toshiba | Semiconductor device having reduced carrier lifetime and method of manufacturing the same |
| DE102004047626A1 (en) * | 2004-09-30 | 2006-04-13 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Thyristor, has semiconductor body with external area that is adjacent to internal area, where charge carrier rating life monotonically decreases within external area with increased separation distance of internal area |
| DE102004047626B4 (en) * | 2004-09-30 | 2009-06-25 | Infineon Technologies Ag | Thyristors with integrated freewheel protection |
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