US3028663A - Method for applying a gold-silver contact onto silicon and germanium semiconductors and article - Google Patents
Method for applying a gold-silver contact onto silicon and germanium semiconductors and article Download PDFInfo
- Publication number
- US3028663A US3028663A US712804A US71280458A US3028663A US 3028663 A US3028663 A US 3028663A US 712804 A US712804 A US 712804A US 71280458 A US71280458 A US 71280458A US 3028663 A US3028663 A US 3028663A
- Authority
- US
- United States
- Prior art keywords
- gold
- silver
- layer
- silicon
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 24
- 239000010703 silicon Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title abstract description 21
- 229910052732 germanium Inorganic materials 0.000 title abstract description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title abstract description 15
- 239000004065 semiconductor Substances 0.000 title description 18
- PQTCMBYFWMFIGM-UHFFFAOYSA-N gold silver Chemical compound [Ag].[Au] PQTCMBYFWMFIGM-UHFFFAOYSA-N 0.000 title description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 abstract description 67
- 239000010931 gold Substances 0.000 abstract description 67
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 65
- 229910052709 silver Inorganic materials 0.000 abstract description 48
- 239000004332 silver Substances 0.000 abstract description 48
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 46
- 238000001704 evaporation Methods 0.000 abstract description 9
- 230000008020 evaporation Effects 0.000 abstract description 8
- 230000008021 deposition Effects 0.000 abstract description 7
- 229910052787 antimony Inorganic materials 0.000 abstract description 6
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005137 deposition process Methods 0.000 abstract description 3
- 229910001245 Sb alloy Inorganic materials 0.000 abstract 1
- KAPYVWKEUSXLKC-UHFFFAOYSA-N [Sb].[Au] Chemical compound [Sb].[Au] KAPYVWKEUSXLKC-UHFFFAOYSA-N 0.000 abstract 1
- 239000002140 antimony alloy Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 33
- 239000000463 material Substances 0.000 description 15
- 238000000151 deposition Methods 0.000 description 14
- 239000002184 metal Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 11
- 230000005496 eutectics Effects 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 238000005275 alloying Methods 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000006835 compression Effects 0.000 description 4
- 238000007906 compression Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000001771 vacuum deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 150000003378 silver Chemical class 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000136 polysorbate Polymers 0.000 description 1
- BALXUFOVQVENIU-KXNXZCPBSA-N pseudoephedrine hydrochloride Chemical compound [H+].[Cl-].CN[C@@H](C)[C@@H](O)C1=CC=CC=C1 BALXUFOVQVENIU-KXNXZCPBSA-N 0.000 description 1
- 238000003303 reheating Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S228/00—Metal fusion bonding
- Y10S228/903—Metal to nonmetal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/922—Static electricity metal bleed-off metallic stock
- Y10S428/923—Physical dimension
- Y10S428/924—Composite
- Y10S428/926—Thickness of individual layer specified
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/922—Static electricity metal bleed-off metallic stock
- Y10S428/9265—Special properties
- Y10S428/929—Electrical contact feature
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/922—Static electricity metal bleed-off metallic stock
- Y10S428/9335—Product by special process
- Y10S428/938—Vapor deposition or gas diffusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12528—Semiconductor component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12771—Transition metal-base component
- Y10T428/12861—Group VIII or IB metal-base component
- Y10T428/12889—Au-base component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12771—Transition metal-base component
- Y10T428/12861—Group VIII or IB metal-base component
- Y10T428/12896—Ag-base component
Definitions
- This invention relates to semiconductive devices and, more particularly, to low resistance contacts to thin semiconductive regions and to methods for fabricating such contacts.
- a novel technique for applying an ohmic contact to a thin diffused region of germanium or silicon involves the use of a second metal immediately following the initial deposit of a metal film, which second metal provides an alloy system with the semiconductive material having a higher eutectic than that of the semiconductive material with the metal of the initial film.
- This enables a continuous deposition process witbout the necessity of lowering the temperature during the fabrication of the contact and further enables subsequent assembly operations to be accomplished on the device using the same metal as that used in the initial film for bonding operations at a temperature below that which would affect either the ohmic contact structure or diffused junctions within the semiconductive material.
- a further object of the present invention is to produce an ohmic connection to thin diffused regions of semiconductor'deviccs which are stable'to higher temperatures and form high conductivity and high mechanical strength connections.
- a diffused junction silicon device of the type disclosed in the aforementioned application of Fuller and Tanenbaum, wherein the ohmic or low resistance connections to the thin diffused base region and an even thinner emitter region are provided in the form of rectangular stripes deposited on the top of the mesa structure of the device.
- These metallic electrodes are fabricated by the vacuum deposition through a perforated plate mask of first, a very thin film of gold containing a trace of a significant impurity, in this case antimony, to insure particularly the retention of the low resistance character of the base connection.
- This initial film typically is about 200 or 300 Angstroms thick and provides a quantity of gold suificient to produce a good electrical and mechanical connection to the silicon but without the danger of having so large a quantity that alloying might occur through the diffused region.
- this silver layer may have a thickness of the order of five microns. This silver layer provides the high conductivity required for an ohmic contact in a device of the kind described. In general, the thickness of the silver is determined by the mass required to provide the desired lateral conductivity but without applying so great a quantity as to result in spreading beyond the limits of the initial gold film.
- the silver layer serves to bind together the gold film which has some tendency to segregate or ball-up when deposited in thin layers.
- gold it has been found important to use gold as the initial contact layer from both an electrical and mechanical standpoint with the silver layer bonding to the gold and providing a similar high conductivity.
- the silver-semiconductor eutectic is sufiiciently high to enable the carrying out of subsequent gold-bonding operations without subjecting the structure to the possibility of alloying of the silver into the semiconductor substrate.
- germanium its eutectic with gold is about 356 degrees centigrade and with silver about 409 degrees can tigrade.
- silicon its eutectic with gold is about 377 degrees centigrade and with silver about 830 degrees centigrade.
- the above-noted temperature differentials thus enable, in the case of both systems, the accomplishment of the entire vacuum deposition of the metallic contact structure at a temperature slightly above the gold-semiconductor eutectic and below the silver-semiconductor eutectic, thus avoiding the danger of producing an alloy region entirely through the thin diffused region and without the necessity of interrupting the evaporation process with consequent possible contamination. Furthermore, subsequent fabrication operations using gold bonds may be accomplished without the risk of degrading the ohmic contact or adjacent diffused regions.
- One feature of the invention therefore, resides in initially plating a very thin film of a lower eutectic point metal with the semiconductor to provide the desired intimate electrical and mechanical bond. Another feature is the subsequent deposition of a second metal having a higher eutectic point with the semiconductor over the initial film without interruption of the evaporation process.
- the compression bonding techniques such as are disclosed in the applications of O. L. Anderson and H. C. Christensen, Serial No. 619,639, filed October 31, 1956, and O. L. Anderson, P. Andreatch, Jr., and H. C. Christensen, Serial No. 647,886, filed March 22, 1957, have been found most advantageous for the attachment of wire leads to plated electrodes.
- a gold layer as a substrate. It is, therefore, a further feature of this invention to apply, conveniently by vacuum deposition, a final layer of gold on top of the silver layer, described above, to facilitate the making of compression bonds to the plated electrode.
- FIG. 1 is a schematic plan view of a diffused junction semiconductor device having contact electrodes in accordance with this invention
- FIG. 2 is a cross-section of the device of FIG. 1;
- FIG. 3 is a partial view in perspective of one type of diffused junction semiconductor device including the contact electrodes in accordance with this invention and showing a typical lead structure;
- FIG. 4 shows in the form of a block diagram flow chart the basic steps of the method of this invention.
- FIG. 4 sets forth in the form of a fiow chart the fabrication steps associated with one method of this invention.
- the diffused junction devices to which this method is particularly applicable are fabricated from relatively large thin slices of monocrystalline semiconductive material, such as germanium and silicon.
- Such a slice may represent a crosssection of a single crystal and have a thickness of about 10 to 20 mils.
- mils and microns as measurements of length, it being understood that one mil is .001 inch and equal to about 25.4 microns.
- the above-described slice may be approximately circular and have a radius of about .50 inch.
- the semiconductor slice of near intrinsic P-type material having a hole concentration of about X10 per cubic centimeter, is first mechanically polished using Linde A abrasive and is then subjected to a solid state diffusion process using boron as the significant impurity to produce P-type conductivity layers having a carrier concentration of about per cubic centimeter to a depth of about 1.6 mils from both faces of the slice.
- the slice is then lapped and polished mechanically on both faces. On one face from 0.2 to 0.4 mil of the surface material which contains a high concentration of boron is removed to avoid uncontrolled rediffusion of boron in subsequent diffusion steps.
- a much greater amount of material is removed from the opposite face of the slice so as to leave a layer of about one mil thickness of the original near intrinsic material contiguous with the layer of boron diffused material, leaving the slice with a total thickness of 2.5 mils or thereabouts.
- the slice is again subjected to a solid state diffusion treatment using antimony as the significant impurity to produce an N-type base region by converting a portion of the near intrinsic region to a depth of about 0.2 mil. Because of the relative concentrations used, the antimony does not materially affect the conductivity type of the boron diffused layer on the op posite face.
- the electron concentration of the antimony diffused N-type conductivity region is about 10 per cubic centimeter.
- the final diffusion step comprises producing a P-type emitter layer in the form of a rectangular stripe approximately 5X60 mils in area and having a depth of about .12 mil.
- the limitation on the depth of the emitter layer is determined by the requirement of a spacing of .06 mil between the emitter-tobase junction and the base-tocollector junction.
- These diffused emitter regions are formed at spaced intervals on the N-type face of the slice by depositing boron oxide through a mask or otherwise restricting the deposition to the limited area of the emitter region, and subsequently heating at diffusion temperatures to cause the boron to diffuse into the silicon substrate from the oxide layer.
- the carrier concentration of the P-type emitter regions is about the same as the concentration in the P-type collector region.
- FIG. 4 a slice of silicon is produced having a P-type layer on the bottom surface, an intermediate intrinsic layer and an N-type base layer on the upper surface interspersed with restricted area P-type emitter regions at uniform intervals on the upper surface.
- formation of the initial metal layer for the ohmic electrode connection to the emitter and base regions is the next step in the fabrication of these devices.
- a mask similar to the type of mask used in connection with the diffusion of the emitter region, but having perforations or slots so as to enable deposition therethrough of three close spaced parallel stripes, is positioned in close proximity to the face of the slice having the multiple diffused emitter regions.
- the mask enables the formation of an electrode 11 slightly smaller than and concentric with the emitter region 12.
- the base resistance is lowered by provision of two base electrode stripes 13 and 14, one on each side of the emitter region. This results in a substantial improvement in the power gain of the device.
- the assembly With the perforated mask in place on the surface of the slice, the assembly is enclosed in a vacuum chamber with heater-type filaments, one loaded with gold containing 0.1 percent antimony and another loaded with silver.
- the chamber is evacuated to a pressure of about 2 l0 millimeters of mercury and the slice is raised to a temperature of about 500 degrees centigrade.
- the filament carrying the gold is energized and sufficient gold is evaporated to produce a layer of be tween and 300 Angstroms thickness.
- the factors determining the thickness of the gold film relate to the avoidance of a coating so light as to be ineffective as a mechanical and electrical bond or so heavy as to permit formation of an alloy region through the diffused layer.
- a film as thin as 20 Angstroms or as thick as 2,000 Angstroms may be desirable.
- a layer of about 200 Angstroms thickness of gold is readily determined by observing the moment at which the film becomes opaque, as observed through a microscope slide positioned in the vacuum chamber with the slice. Typically, this film should be deposited in about one minute.
- the silver-loaded filament is energized.
- the gold-loaded filament may be turned off. It is generally advantageous for optimum results that the deposition process be continuous with no interruption in the flow of metal vapor.
- Sufficient silver is evaporated to provide a layer of about five microns thickness.
- the thickness of the silver layer may vary depending upon the electrical characteristics of the device and the requirement for stopping the pile-up of silver before it spreads beyond the area of the initial gold film. It appears that as little as about 0.5 micron thickness of silver achieves the purpose of preventing alloying of an outer gold layer therethrough and into the silicon.
- certain applications may require a layer of silver as heavy as microns to provide the requisite high lateral conductivity.
- the thickness is readily controlled by provid ing a limited amount of silver sufiicient to produce such a coating and evaporating it entirely.
- the gold-loaded lament is reenergized and a final layer or coating of gold is appliedon top of the silver.
- the assembly is removed from the vacuum chamber and the slice is divided into a plurality of separate Wafers of about 100x45 mils size, each having the electrodes and diffused emitter region centrally disposed on one face thereof, as illustrated in FIGS. 1 and 2.
- a mesa portion 15 is produced by etching away portions of the wafer 10, as disclosed in the aforementioned applications of Dacey-Lee-Shockley and Fuller-Tanenbaum. Atop the mesa portion 15 are the emitter electrode 11 and base electrodes 13 and 14. As shown in FIG. 2, the semiconductive wafer comprises the P-type emitter region 12,, the N-type base region 16 defined by the PN junctions 18 and 19, and the collector region 17.
- the broken line 20 indicates the region of transition from the original near intrinsic portion 21 to the higher conductivity P-type collector region 17. The change from the one region to the other is gradual.
- the dilfused layers shown in the cross-section of FIG. 2 are of extreme thinness.
- the near intrinsic layer 21 has a thickness of about 0.4 mil and the base region 16 is about 0.2 mil or less in thickness.
- the boron-diffused emitter region 12 penetrates into the base region 16 to a depth of about .12 mil.
- the electrode structures in accordance with this invention may be regarded as multilayer elements.
- the base electrode 14 comprises the initial film 22 of gold.
- This film 22 will be alloyed, to some extent at least, with the underlying semiconductive material and, having a thickness of perhaps 200 Angstroms, would be virtually indistinguishable when viewed in section even with high magnification.
- the next and heaviest layer 23 is of silver, providing the major portion of the metallic electrode.
- the semiconductive wafer Upon completion of mesa etching, the semiconductive wafer is further processed in accordance with cleaning and etching techniques well known in the art. Referring to the partial view of FIG. 3, the wafer 10 is mounted on a mounting platform or header 31, preferably by gold bonding which may be accomplished faciley at a temperature of about 400 degrees centigrade without danger of affecting the Wafer structure.
- Wire leads are attached to the base and emitter electrodes by compression bonding to the gold surfaces of the electrodes.
- such wire leads may be gold.
- Two of the leads 33 and 34 are attached to one stem member 40 which functions as the base connection for the transistor, while the lead 32 to the middle emitter electrode 11 is attached to another stem 41 to provide the emitter connection.
- the mounting platform or header 31 functions as the collector electrode and may comprise the metallic shell or housing of the transistor.
- the stem members 40 and 41 are insulated from the header by glass inserts 42 and 43.
- An element for integration with a semiconductive body selected from the group consisting of silicon and germanium by alloying to form a conductive connection thereto comprising a thin gold film bonded to said semiconductive body, a layer predominately of silver bonded to said gold film, and a third metallic conductive member bonded to said silver layer.
- a substantially ohmic connection to a semiconductive body selected from the group consisting of silicon and germanium comprising a thin gold film of the order of 200 Angstroms thickness bonded to said semiconductive body, a layer predominately of silver having a thickness of from 0.5 to 15 microns bonded to said gold film, and a metallic conductive member bonded to said predominately silver layer.
- a substantially ohmic connection to a semiconductive body selected from the group consisting of silicon and germanium comprising a thin gold film of the order of 200 Angstroms thickness bonded to said semiconduc tive body, a layer predominately of silver having a thickness of from 0.5 to 15 microns bonded to said gold film, and a layer substantially of gold bonded to said silver layer.
- the method of making a low resistance connection to a semiconductive body selected from the group c0nsisting of silicon and germanium comprising vapor depositing a film of gold having a thickness in the range between 200 and 1,000 Angstroms and simultaneously bonding said film to said semiconductive material by heating to a temperature above the gold to semiconductor eutectic, and below the silver to semiconductor eutectic, continuously thereafter, vapor depositing on said gold film a layer predominately of silver having a thickness of from 0.5 to 15 microns.
- the method of making a low resistance substantially ohmic connection to a silicon semiconductive body including therein thin diffused conductivity-type regions comprising the steps of continuously vapor depositing on discrete portions of said body first, a film of gold of a thickness of about 200 Angstroms, simultaneously alloy bonding said film to said silicon by maintaining a temperature of about 500 degrees centigrade, and second a heavier layer predominately of silver having a thickness of from 0.5 to 15 microns and maintaining the temperature at about 500 degrees centigrade.
- the method of making a low resistance substantially ohmic connection to a germanium semiconductive body including thin difiused conductivity-type regions comprising the steps of continuously vapor depositing on discrete portions of said body first, a film of gold of a thickness of about 200 Angstroms, simultaneously alloy bonding said film to said silicon by maintaining a temperature of about 400 degrees centigrade, second, a heavier layer predominately of silver having a thickness of from 0.5 to 15 microns and maintaining the temperature at about 400 degrees centigrade.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Mechanical Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
Abstract
Superposed layers of gold and silver (or predominantly silver) are deposited on germanium or silicon bodies in the following manner to provide ohmic contacts thereto. A silicon body comprising zones of different conductivity types so disposed as to make it suitable as a transistor (see Group XXXVI) is masked, enclosed in a vacuum chamber provided with heater filaments loaded with silver and a gold antimony alloy (0.1% by weight antimony) respectively and heated to 500 DEG C. The gold loaded filament is first energised to evaporate gold on to the wafer through the mask to provide a series of groups of three parallel elongated gold layers. When the layers are about 200 thick the silver loaded filament is energized and the other switched off as soon as silver begins to deposit. The amount of silver is limited so that its complete evaporation results in layers 5 m thick. A further layer of gold is provided by re-energizing the gold loaded filament. In an alternative method, after deposition of the first gold layer the silver and gold are evaporated simultaneously, the evaporation of the measured amount of silver being so much more rapid that while it lasts the layer is essentially of silver. When the silver is exhausted the gold continues to evaporate to provide the outer layer. When germanium is used instead of silicon it is maintained at a temperature of only 390-400 DEG C. during the deposition process. Specifications 809,642, 809,643, 821,832 and 821,834 are referred to.
Description
Ap 1962 J. E. IWERSEN ETAL 3,023,663
METHOD FOR APPLYING A GOLD-SILVER CONTAC NTO SILICON 1958AND GERMANIUM SEMICONDUCTORS AND A ICL a,
E 2 Sheets-Sheet 1 Filed Feb.
lNl ENTORS:
BVI
ATYURNEV Apnl 10, 1962 J. E. IWERSEN ETAL 3,028,663
METHOD FOR APPLYING A GOLD-SILVER CONTACT ONTO SILICON AND GERMANIUM SEMICONDUCTORS AND ARTICLE Flled Feb. 5, 1958 2 Sheets-Sheet 2 FIG. 4
lMPUR/TY-D/FFUSE SILICON SL/CE I TO PRODUCE COLLECTOR, BASE AND EM/TTER REG/OMS.
EVAPORATE rm/v FILM {200-300 A) .22 GOLD STRIPES o/v EMITTER Alva BASE REG/0N5 A7 500 "c.
EVAPORATE HEA W LAYER /0.5 -/5 122' M/cRo/vs) 0F S/Ll/ER ON TOP OF cow STRIPES A7 4/ 500 0.
HZ- E VAPOR/J TE GOLD FILM ON TOP OF SIL l/ER LA YE R ao/vo WIRE LEADS To Z TOP GOLD LAYER.
J. E. IWERSEN INVENTORS J. NELSON ATTORNEY United States Patent York Filed Feb. 3, 1958, Ser. No. 712,864 6 Claims. (Cl. 29-195) This invention relates to semiconductive devices and, more particularly, to low resistance contacts to thin semiconductive regions and to methods for fabricating such contacts.
It is important in certain types of semiconductive devices to make contact to the semiconductive body in a manner which is advantageous both electrically and mechanically. This is particularly so in the case of devices having thin regions of alternate conductivity type, such as, for example, those produced wholly or in part by diffusion techniques as disclosed in the application of G. C. Dacey, C. A. Lee and W. Shockley, Serial No. 496,202, filed March 23, 1955, and C. S. Fuller and M. Tanenbaum, Serial No. 516,674, filed June 20, 1955, now Patent No. 2,861,018. In devices of this type it is a requisite to provide a contact having good conductivity from the underlying semiconductive material and, particularly, in devices having a relatively high power handling capability in relation to their physical size, the contact must have high lateral conductivity.
In the past it has been difiicult to achieve these re quisites and at the same time enable the facile assembly of the entire device by convenient methods. It has been found that gold is the most satisfactory metal from the standpoint of electrical conductivity and mechanical bonding for makin electrodes on semiconductive material, such as germanium and silicon. However, when an ohmic electrode is fabricated on very thin diffused regions which, for example, may have a thickness of about .0001 inch, the deposition of a sufficiently heavy layer of gold to provide the desired high lateral conductivity results in an alloying of the gold and semiconductive material, thereby producing a molten region which penetrates the diffused region and, in effect, destroys the diffused junction structure. Some success has been achieved in applying the gold electrode in two distinct steps, permitting the assembly to cool after first depositing and alloying a very thin gold film and then reheating to a lower temperature than that previously used and depositing a final heavy layer of gold. This technique has resulted in generally poor structural contacts from the standpoint of the bond between the initial film and the heavier gold layer.
in order to overcome these and other disadvantages, a novel technique for applying an ohmic contact to a thin diffused region of germanium or silicon is provided by the applicants. This technique involves the use of a second metal immediately following the initial deposit of a metal film, which second metal provides an alloy system with the semiconductive material having a higher eutectic than that of the semiconductive material with the metal of the initial film. This enables a continuous deposition process witbout the necessity of lowering the temperature during the fabrication of the contact and further enables subsequent assembly operations to be accomplished on the device using the same metal as that used in the initial film for bonding operations at a temperature below that which would affect either the ohmic contact structure or diffused junctions within the semiconductive material.
it is therefore an object of this invention to produce improved electrical contacts to semiconductive bodies.
3,028,663 Patented Apr. 10, 1962 Another object is to facilitate the production of loW resistance ohmic connections to thin conductivity type regions of semiconductors.
A further object of the present invention is to produce an ohmic connection to thin diffused regions of semiconductor'deviccs which are stable'to higher temperatures and form high conductivity and high mechanical strength connections.
These and other objects of the invention are achieved in one specific embodiment in a diffused junction silicon device of the type disclosed in the aforementioned application of Fuller and Tanenbaum, wherein the ohmic or low resistance connections to the thin diffused base region and an even thinner emitter region are provided in the form of rectangular stripes deposited on the top of the mesa structure of the device. These metallic electrodes are fabricated by the vacuum deposition through a perforated plate mask of first, a very thin film of gold containing a trace of a significant impurity, in this case antimony, to insure particularly the retention of the low resistance character of the base connection. This initial film typically is about 200 or 300 Angstroms thick and provides a quantity of gold suificient to produce a good electrical and mechanical connection to the silicon but without the danger of having so large a quantity that alloying might occur through the diffused region.
immediately following this initial deposition of gold, and without interrupting the evaporation process and thereby exposing the material to contamination, a comparatively heavy layer of silver is vacuum deposited through the same mask on top of the initial gold film. When the evaporation process is interrupted for a significant time it has been found that an intermediate layer of contamination forms which substantially degrades the mechanical structure. Typically, this silver layer may have a thickness of the order of five microns. This silver layer provides the high conductivity required for an ohmic contact in a device of the kind described. In general, the thickness of the silver is determined by the mass required to provide the desired lateral conductivity but without applying so great a quantity as to result in spreading beyond the limits of the initial gold film. Furthermore, the silver layer serves to bind together the gold film which has some tendency to segregate or ball-up when deposited in thin layers. However, it has been found important to use gold as the initial contact layer from both an electrical and mechanical standpoint with the silver layer bonding to the gold and providing a similar high conductivity. Furthermore, the silver-semiconductor eutectic is sufiiciently high to enable the carrying out of subsequent gold-bonding operations without subjecting the structure to the possibility of alloying of the silver into the semiconductor substrate. For example, in the case of germanium, its eutectic with gold is about 356 degrees centigrade and with silver about 409 degrees can tigrade. In the case of silicon, its eutectic with gold is about 377 degrees centigrade and with silver about 830 degrees centigrade.
The above-noted temperature differentials thus enable, in the case of both systems, the accomplishment of the entire vacuum deposition of the metallic contact structure at a temperature slightly above the gold-semiconductor eutectic and below the silver-semiconductor eutectic, thus avoiding the danger of producing an alloy region entirely through the thin diffused region and without the necessity of interrupting the evaporation process with consequent possible contamination. Furthermore, subsequent fabrication operations using gold bonds may be accomplished without the risk of degrading the ohmic contact or adjacent diffused regions.
One feature of the invention, therefore, resides in initially plating a very thin film of a lower eutectic point metal with the semiconductor to provide the desired intimate electrical and mechanical bond. Another feature is the subsequent deposition of a second metal having a higher eutectic point with the semiconductor over the initial film without interruption of the evaporation process.
Additionally, in structures of the diffused junction type, the compression bonding techniques, such as are disclosed in the applications of O. L. Anderson and H. C. Christensen, Serial No. 619,639, filed October 31, 1956, and O. L. Anderson, P. Andreatch, Jr., and H. C. Christensen, Serial No. 647,886, filed March 22, 1957, have been found most advantageous for the attachment of wire leads to plated electrodes. In the use of such bonds it has been found desirable to use a gold layer as a substrate. It is, therefore, a further feature of this invention to apply, conveniently by vacuum deposition, a final layer of gold on top of the silver layer, described above, to facilitate the making of compression bonds to the plated electrode.
More specifically, it is a feature of this invention to employ alternate layers of gold and silver comprising an initial very thin layer of gold, followed successively by relatively heavier layers of silver and gold, to produce ohmic or low resistance contact electrodes for semiconductor devices having thin diffused conductivity-type regions.
The invention and its additional objects and features will be understood more clearly and fully from the following description considered in conjunction with the accompanying drawing in which:
FIG. 1 is a schematic plan view of a diffused junction semiconductor device having contact electrodes in accordance with this invention;
FIG. 2 is a cross-section of the device of FIG. 1;
FIG. 3 is a partial view in perspective of one type of diffused junction semiconductor device including the contact electrodes in accordance with this invention and showing a typical lead structure;
FIG. 4 shows in the form of a block diagram flow chart the basic steps of the method of this invention.
Referring to the drawing, FIG. 4 sets forth in the form of a fiow chart the fabrication steps associated with one method of this invention. Typically, the diffused junction devices to which this method is particularly applicable are fabricated from relatively large thin slices of monocrystalline semiconductive material, such as germanium and silicon. Such a slice may represent a crosssection of a single crystal and have a thickness of about 10 to 20 mils. In this disclosure use will be made of the terms mils and microns as measurements of length, it being understood that one mil is .001 inch and equal to about 25.4 microns. The above-described slice may be approximately circular and have a radius of about .50 inch.
The semiconductor slice, of near intrinsic P-type material having a hole concentration of about X10 per cubic centimeter, is first mechanically polished using Linde A abrasive and is then subjected to a solid state diffusion process using boron as the significant impurity to produce P-type conductivity layers having a carrier concentration of about per cubic centimeter to a depth of about 1.6 mils from both faces of the slice. The slice is then lapped and polished mechanically on both faces. On one face from 0.2 to 0.4 mil of the surface material which contains a high concentration of boron is removed to avoid uncontrolled rediffusion of boron in subsequent diffusion steps. A much greater amount of material is removed from the opposite face of the slice so as to leave a layer of about one mil thickness of the original near intrinsic material contiguous with the layer of boron diffused material, leaving the slice with a total thickness of 2.5 mils or thereabouts. The slice is again subjected to a solid state diffusion treatment using antimony as the significant impurity to produce an N-type base region by converting a portion of the near intrinsic region to a depth of about 0.2 mil. Because of the relative concentrations used, the antimony does not materially affect the conductivity type of the boron diffused layer on the op posite face. The electron concentration of the antimony diffused N-type conductivity region is about 10 per cubic centimeter.
The final diffusion step comprises producing a P-type emitter layer in the form of a rectangular stripe approximately 5X60 mils in area and having a depth of about .12 mil. In the particular semiconductor device herein described, the limitation on the depth of the emitter layer is determined by the requirement of a spacing of .06 mil between the emitter-tobase junction and the base-tocollector junction. These diffused emitter regions are formed at spaced intervals on the N-type face of the slice by depositing boron oxide through a mask or otherwise restricting the deposition to the limited area of the emitter region, and subsequently heating at diffusion temperatures to cause the boron to diffuse into the silicon substrate from the oxide layer. The carrier concentration of the P-type emitter regions is about the same as the concentration in the P-type collector region.
Thus, as a result of the fabrication procedure repre sented by block I, FIG. 4, a slice of silicon is produced having a P-type layer on the bottom surface, an intermediate intrinsic layer and an N-type base layer on the upper surface interspersed with restricted area P-type emitter regions at uniform intervals on the upper surface.
As indicated by the block II of FIG. 4, formation of the initial metal layer for the ohmic electrode connection to the emitter and base regions is the next step in the fabrication of these devices. A mask similar to the type of mask used in connection with the diffusion of the emitter region, but having perforations or slots so as to enable deposition therethrough of three close spaced parallel stripes, is positioned in close proximity to the face of the slice having the multiple diffused emitter regions. As best seen in FIG. 1, the mask enables the formation of an electrode 11 slightly smaller than and concentric with the emitter region 12. In this particular transistor the base resistance is lowered by provision of two base electrode stripes 13 and 14, one on each side of the emitter region. This results in a substantial improvement in the power gain of the device. With the perforated mask in place on the surface of the slice, the assembly is enclosed in a vacuum chamber with heater-type filaments, one loaded with gold containing 0.1 percent antimony and another loaded with silver. The chamber is evacuated to a pressure of about 2 l0 millimeters of mercury and the slice is raised to a temperature of about 500 degrees centigrade. The filament carrying the gold is energized and sufficient gold is evaporated to produce a layer of be tween and 300 Angstroms thickness. The factors determining the thickness of the gold film relate to the avoidance of a coating so light as to be ineffective as a mechanical and electrical bond or so heavy as to permit formation of an alloy region through the diffused layer. Under some conditions a film as thin as 20 Angstroms or as thick as 2,000 Angstroms may be desirable. A layer of about 200 Angstroms thickness of gold is readily determined by observing the moment at which the film becomes opaque, as observed through a microscope slide positioned in the vacuum chamber with the slice. Typically, this film should be deposited in about one minute.
As soon as the desired thickness of gold film is approached, the silver-loaded filament is energized. When an appreciable flow of silver is observed the gold-loaded filament may be turned off. It is generally advantageous for optimum results that the deposition process be continuous with no interruption in the flow of metal vapor. Sufficient silver is evaporated to provide a layer of about five microns thickness. As indicated hereinbefore, the thickness of the silver layer may vary depending upon the electrical characteristics of the device and the requirement for stopping the pile-up of silver before it spreads beyond the area of the initial gold film. It appears that as little as about 0.5 micron thickness of silver achieves the purpose of preventing alloying of an outer gold layer therethrough and into the silicon. On the other hand, certain applications may require a layer of silver as heavy as microns to provide the requisite high lateral conductivity. The thickness is readily controlled by provid ing a limited amount of silver sufiicient to produce such a coating and evaporating it entirely. When all, or nearly all, of the silver has been evaporated, the gold-loaded lament is reenergized and a final layer or coating of gold is appliedon top of the silver. These steps are set forth by the blocks marked III and IV of FIG. 4. In some applications it will be found advantageous after the initial gold deposition to evaporate the silver and gold simultaneously. Because of the higher evaporation rate of silver, it will deposit much more rapidly than the gold and by properly proportioning the amount of the two metals loaded on the filaments, there will be deposited a middle layer predominately of silver with anouter coating of gold. It will be apparent that under certain circumstances more than two heater filaments might be provided for controllably depositing the gold and silver layers.
After completion of the evaporation steps, the assembly is removed from the vacuum chamber and the slice is divided into a plurality of separate Wafers of about 100x45 mils size, each having the electrodes and diffused emitter region centrally disposed on one face thereof, as illustrated in FIGS. 1 and 2.
Considering the fabrication in terms of a single wafer from this point, a mesa portion 15 is produced by etching away portions of the wafer 10, as disclosed in the aforementioned applications of Dacey-Lee-Shockley and Fuller-Tanenbaum. Atop the mesa portion 15 are the emitter electrode 11 and base electrodes 13 and 14. As shown in FIG. 2, the semiconductive wafer comprises the P-type emitter region 12,, the N-type base region 16 defined by the PN junctions 18 and 19, and the collector region 17. The broken line 20 indicates the region of transition from the original near intrinsic portion 21 to the higher conductivity P-type collector region 17. The change from the one region to the other is gradual.
As indicated hereinabove, the dilfused layers shown in the cross-section of FIG. 2 are of extreme thinness. The collector region 17, which is shown broken with a portion omitted to enable use of a larger scale, may have a thickness of about 1.6 mils. The near intrinsic layer 21 has a thickness of about 0.4 mil and the base region 16 is about 0.2 mil or less in thickness. The boron-diffused emitter region 12 penetrates into the base region 16 to a depth of about .12 mil.
It is apparent that the thin emitter and base regions of the foregoing described structure present diiticulties in making low resistance connections thereto. As depicted in schematic form and not to scale, the electrode structures in accordance with this invention may be regarded as multilayer elements. Considering the base electrode 14, it comprises the initial film 22 of gold. This film 22 will be alloyed, to some extent at least, with the underlying semiconductive material and, having a thickness of perhaps 200 Angstroms, would be virtually indistinguishable when viewed in section even with high magnification. The next and heaviest layer 23 is of silver, providing the major portion of the metallic electrode. As suggested hereinbefore, an outer layer 24, again of gold, advantageously is provided to facilitate attaching compression bonded wire leads. Upon completion of mesa etching, the semiconductive wafer is further processed in accordance with cleaning and etching techniques well known in the art. Referring to the partial view of FIG. 3, the wafer 10 is mounted on a mounting platform or header 31, preferably by gold bonding which may be accomplished faciley at a temperature of about 400 degrees centigrade without danger of affecting the Wafer structure.
Wire leads are attached to the base and emitter electrodes by compression bonding to the gold surfaces of the electrodes. Advantageously, such wire leads may be gold. Two of the leads 33 and 34 are attached to one stem member 40 which functions as the base connection for the transistor, while the lead 32 to the middle emitter electrode 11 is attached to another stem 41 to provide the emitter connection. The mounting platform or header 31 functions as the collector electrode and may comprise the metallic shell or housing of the transistor. The stem members 40 and 41 are insulated from the header by glass inserts 42 and 43.
The particular advantages of the contact structure in accordance with this invention will be appreciated from the fact that a device of the configuration described above has been constructed having a capability of delivering five watts power at a frequency of 10 megacycles per secend at a relatively high efiiciency. At a frequency of megacycles per second the device is still capable of de livering one Watt power at about 15 percent efiiciency. The efiicacy of the ohmic electrodes produced in accordance with this invention in providing a highly satisfactory low resistance and high current carrying capacity is apparent from the foregoing figures.
Substantially the same fabrication technique is employed for the making of similar contact electrodes on germanium with the difference that a lower temperature of between 390 and 400 degrees centigrade is advantageously used.
While specific embodiments of the invention have been disclosed herein, it will be understood that variations may be devised by those skilled in the art which are within the scope and spirit of the invention.
What is claimed is:
1. An element for integration with a semiconductive body selected from the group consisting of silicon and germanium by alloying to form a conductive connection thereto comprising a thin gold film bonded to said semiconductive body, a layer predominately of silver bonded to said gold film, and a third metallic conductive member bonded to said silver layer.
2. A substantially ohmic connection to a semiconductive body selected from the group consisting of silicon and germanium comprising a thin gold film of the order of 200 Angstroms thickness bonded to said semiconductive body, a layer predominately of silver having a thickness of from 0.5 to 15 microns bonded to said gold film, and a metallic conductive member bonded to said predominately silver layer. I
3. A substantially ohmic connection to a semiconductive body selected from the group consisting of silicon and germanium comprising a thin gold film of the order of 200 Angstroms thickness bonded to said semiconduc tive body, a layer predominately of silver having a thickness of from 0.5 to 15 microns bonded to said gold film, and a layer substantially of gold bonded to said silver layer.
4. The method of making a low resistance connection to a semiconductive body selected from the group c0nsisting of silicon and germanium, comprising vapor depositing a film of gold having a thickness in the range between 200 and 1,000 Angstroms and simultaneously bonding said film to said semiconductive material by heating to a temperature above the gold to semiconductor eutectic, and below the silver to semiconductor eutectic, continuously thereafter, vapor depositing on said gold film a layer predominately of silver having a thickness of from 0.5 to 15 microns.
5. The method of making a low resistance substantially ohmic connection to a silicon semiconductive body including therein thin diffused conductivity-type regions comprising the steps of continuously vapor depositing on discrete portions of said body first, a film of gold of a thickness of about 200 Angstroms, simultaneously alloy bonding said film to said silicon by maintaining a temperature of about 500 degrees centigrade, and second a heavier layer predominately of silver having a thickness of from 0.5 to 15 microns and maintaining the temperature at about 500 degrees centigrade.
6. The method of making a low resistance substantially ohmic connection to a germanium semiconductive body including thin difiused conductivity-type regions comprising the steps of continuously vapor depositing on discrete portions of said body first, a film of gold of a thickness of about 200 Angstroms, simultaneously alloy bonding said film to said silicon by maintaining a temperature of about 400 degrees centigrade, second, a heavier layer predominately of silver having a thickness of from 0.5 to 15 microns and maintaining the temperature at about 400 degrees centigrade.
References (Zited in the file of this patent UNITED STATES PATENTS 2,446,254 Van Amstel Aug. 3, 1948 2,531,660 Ziegler Nov. 28, 1950 2,763,822 Frola et al. Sept. 18, 1956 2,782,492 Frost Feb. 26, 1957 2,793,420 Johnston et al May 28, 1957 2,820,932 Looney Jan. 21, 1958 2,824,269 Ohl Feb. 18, 1958 2,922,092 Gazzara et a1 J an. 19, 1960 OTHER REFERENCES Kelly: Pressure Welding," The Welding Journal, Au-
gust 1951, pages 728-736.
Claims (1)
- 5. THE METHOD OF MAKING A LOW RESISTANCE SUBSTANTIALLY OHMIC CONNECTION IN A SILICON SEMICONDUCTIVE BODY INCLUDING THEREIN THIN DIFFUSED CONDUCTIVELY-TYPE REGIONS COMPRISING THE STEPS OF CONTINUOUSLY VAPOR DEPOSTING ON DISCRETE PORTIONS OF SAID BODY FIRST, A FILM OF GOLD OF A THICKNESS OF ABOUT 200 ANGSTROMS, SIMULTANEOUSLY ALLOY
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
BE575275D BE575275A (en) | 1958-02-03 | ||
NL235742D NL235742A (en) | 1958-02-03 | ||
US712804A US3028663A (en) | 1958-02-03 | 1958-02-03 | Method for applying a gold-silver contact onto silicon and germanium semiconductors and article |
DEW24913A DE1127488B (en) | 1958-02-03 | 1959-01-27 | Semiconductor device made of silicon or germanium and process for their manufacture |
GB3368/59A GB911667A (en) | 1958-02-03 | 1959-01-30 | Connections to semiconductor bodies and methods of making such connections |
FR785474A FR1226492A (en) | 1958-02-03 | 1959-01-31 | Alloy formed conductive bond semiconductors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US712804A US3028663A (en) | 1958-02-03 | 1958-02-03 | Method for applying a gold-silver contact onto silicon and germanium semiconductors and article |
Publications (1)
Publication Number | Publication Date |
---|---|
US3028663A true US3028663A (en) | 1962-04-10 |
Family
ID=24863620
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US712804A Expired - Lifetime US3028663A (en) | 1958-02-03 | 1958-02-03 | Method for applying a gold-silver contact onto silicon and germanium semiconductors and article |
Country Status (6)
Country | Link |
---|---|
US (1) | US3028663A (en) |
BE (1) | BE575275A (en) |
DE (1) | DE1127488B (en) |
FR (1) | FR1226492A (en) |
GB (1) | GB911667A (en) |
NL (1) | NL235742A (en) |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3108209A (en) * | 1959-05-21 | 1963-10-22 | Motorola Inc | Transistor device and method of manufacture |
US3155936A (en) * | 1958-04-24 | 1964-11-03 | Motorola Inc | Transistor device with self-jigging construction |
US3158504A (en) * | 1960-10-07 | 1964-11-24 | Texas Instruments Inc | Method of alloying an ohmic contact to a semiconductor |
US3165714A (en) * | 1961-09-04 | 1965-01-12 | Electronique & Automatisme Sa | Resistive layer track potentiometers |
US3184831A (en) * | 1960-11-16 | 1965-05-25 | Siemens Ag | Method of producing an electric contact with a semiconductor device |
US3186084A (en) * | 1960-06-24 | 1965-06-01 | Int Nickel Co | Process for securing a conductor to a semiconductor |
US3190954A (en) * | 1962-02-06 | 1965-06-22 | Clevite Corp | Semiconductor device |
US3233309A (en) * | 1961-07-14 | 1966-02-08 | Siemens Ag | Method of producing electrically asymmetrical semiconductor device of symmetrical mechanical design |
US3261089A (en) * | 1962-01-09 | 1966-07-19 | Bosch Gmbh Robert | Method of treating lead-in wires of electrode tubes |
US3266137A (en) * | 1962-06-07 | 1966-08-16 | Hughes Aircraft Co | Metal ball connection to crystals |
US3271636A (en) * | 1962-10-23 | 1966-09-06 | Bell Telephone Labor Inc | Gallium arsenide semiconductor diode and method |
US3290570A (en) * | 1964-04-28 | 1966-12-06 | Texas Instruments Inc | Multilevel expanded metallic contacts for semiconductor devices |
US3300340A (en) * | 1963-02-06 | 1967-01-24 | Itt | Bonded contacts for gold-impregnated semiconductor devices |
US3325704A (en) * | 1964-07-31 | 1967-06-13 | Texas Instruments Inc | High frequency coaxial transistor package |
US3349476A (en) * | 1963-11-26 | 1967-10-31 | Ibm | Formation of large area contacts to semiconductor devices |
US3361592A (en) * | 1964-03-16 | 1968-01-02 | Hughes Aircraft Co | Semiconductor device manufacture |
US3370207A (en) * | 1964-02-24 | 1968-02-20 | Gen Electric | Multilayer contact system for semiconductor devices including gold and copper layers |
US3654694A (en) * | 1969-04-28 | 1972-04-11 | Hughes Aircraft Co | Method for bonding contacts to and forming alloy sites on silicone carbide |
US3733685A (en) * | 1968-11-25 | 1973-05-22 | Gen Motors Corp | Method of making a passivated wire bonded semiconductor device |
US3751293A (en) * | 1969-04-04 | 1973-08-07 | Bell Telephone Labor Inc | Method for reducing interdiffusion rates between thin film components |
US3869260A (en) * | 1971-08-04 | 1975-03-04 | Ferranti Ltd | Manufacture of supports for use with semiconductor devices |
EP0127089A1 (en) * | 1983-05-18 | 1984-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having first and second electrodes and method of producing the same |
US4702941A (en) * | 1984-03-27 | 1987-10-27 | Motorola Inc. | Gold metallization process |
US4753897A (en) * | 1986-03-14 | 1988-06-28 | Motorola Inc. | Method for providing contact separation in silicided devices using false gate |
US4822641A (en) * | 1985-04-30 | 1989-04-18 | Inovan Gmbh & Co. Kg | Method of manufacturing a contact construction material structure |
US4998158A (en) * | 1987-06-01 | 1991-03-05 | Motorola, Inc. | Hypoeutectic ohmic contact to N-type gallium arsenide with diffusion barrier |
RU2564685C1 (en) * | 2014-08-25 | 2015-10-10 | Олег Петрович Ксенофонтов | Heat fusion method |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1131811B (en) * | 1961-05-17 | 1962-06-20 | Intermetall | Method for non-blocking contacting of the collector of germanium transistors |
NL296608A (en) * | 1962-08-15 | |||
GB1025453A (en) * | 1964-01-29 | 1966-04-06 | Standard Telephones Cables Ltd | Improvements in or relating to semiconductor devices |
US3268309A (en) * | 1964-03-30 | 1966-08-23 | Gen Electric | Semiconductor contact means |
DE1274735B (en) * | 1964-08-21 | 1968-08-08 | Ibm Deutschland | Method for producing alloy contacts on semiconductor bodies |
DE1514806B1 (en) * | 1965-04-10 | 1970-04-23 | Telefunken Patent | Method for producing a blocking or non-blocking electrode on a semiconductor body and an interconnect contacting this electrode |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2446254A (en) * | 1942-12-07 | 1948-08-03 | Hartford Nat Bank & Trust Co | Blocking-layer cell |
US2531660A (en) * | 1949-08-27 | 1950-11-28 | Bell Telephone Labor Inc | Fabrication of piezoelectric crystal units |
US2763822A (en) * | 1955-05-10 | 1956-09-18 | Westinghouse Electric Corp | Silicon semiconductor devices |
US2782492A (en) * | 1954-02-11 | 1957-02-26 | Atlas Powder Co | Method of bonding fine wires to copper or copper alloys |
US2793420A (en) * | 1955-04-22 | 1957-05-28 | Bell Telephone Labor Inc | Electrical contacts to silicon |
US2820932A (en) * | 1956-03-07 | 1958-01-21 | Bell Telephone Labor Inc | Contact structure |
US2824269A (en) * | 1956-01-17 | 1958-02-18 | Bell Telephone Labor Inc | Silicon translating devices and silicon alloys therefor |
US2922092A (en) * | 1957-05-09 | 1960-01-19 | Westinghouse Electric Corp | Base contact members for semiconductor devices |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2695852A (en) * | 1952-02-15 | 1954-11-30 | Bell Telephone Labor Inc | Fabrication of semiconductors for signal translating devices |
NL98125C (en) * | 1954-08-26 | 1900-01-01 |
-
0
- BE BE575275D patent/BE575275A/xx unknown
- NL NL235742D patent/NL235742A/xx unknown
-
1958
- 1958-02-03 US US712804A patent/US3028663A/en not_active Expired - Lifetime
-
1959
- 1959-01-27 DE DEW24913A patent/DE1127488B/en active Pending
- 1959-01-30 GB GB3368/59A patent/GB911667A/en not_active Expired
- 1959-01-31 FR FR785474A patent/FR1226492A/en not_active Expired
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2446254A (en) * | 1942-12-07 | 1948-08-03 | Hartford Nat Bank & Trust Co | Blocking-layer cell |
US2531660A (en) * | 1949-08-27 | 1950-11-28 | Bell Telephone Labor Inc | Fabrication of piezoelectric crystal units |
US2782492A (en) * | 1954-02-11 | 1957-02-26 | Atlas Powder Co | Method of bonding fine wires to copper or copper alloys |
US2793420A (en) * | 1955-04-22 | 1957-05-28 | Bell Telephone Labor Inc | Electrical contacts to silicon |
US2763822A (en) * | 1955-05-10 | 1956-09-18 | Westinghouse Electric Corp | Silicon semiconductor devices |
US2824269A (en) * | 1956-01-17 | 1958-02-18 | Bell Telephone Labor Inc | Silicon translating devices and silicon alloys therefor |
US2820932A (en) * | 1956-03-07 | 1958-01-21 | Bell Telephone Labor Inc | Contact structure |
US2922092A (en) * | 1957-05-09 | 1960-01-19 | Westinghouse Electric Corp | Base contact members for semiconductor devices |
Cited By (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3155936A (en) * | 1958-04-24 | 1964-11-03 | Motorola Inc | Transistor device with self-jigging construction |
US3108209A (en) * | 1959-05-21 | 1963-10-22 | Motorola Inc | Transistor device and method of manufacture |
US3186084A (en) * | 1960-06-24 | 1965-06-01 | Int Nickel Co | Process for securing a conductor to a semiconductor |
US3158504A (en) * | 1960-10-07 | 1964-11-24 | Texas Instruments Inc | Method of alloying an ohmic contact to a semiconductor |
US3184831A (en) * | 1960-11-16 | 1965-05-25 | Siemens Ag | Method of producing an electric contact with a semiconductor device |
US3233309A (en) * | 1961-07-14 | 1966-02-08 | Siemens Ag | Method of producing electrically asymmetrical semiconductor device of symmetrical mechanical design |
US3165714A (en) * | 1961-09-04 | 1965-01-12 | Electronique & Automatisme Sa | Resistive layer track potentiometers |
US3261089A (en) * | 1962-01-09 | 1966-07-19 | Bosch Gmbh Robert | Method of treating lead-in wires of electrode tubes |
US3190954A (en) * | 1962-02-06 | 1965-06-22 | Clevite Corp | Semiconductor device |
US3266137A (en) * | 1962-06-07 | 1966-08-16 | Hughes Aircraft Co | Metal ball connection to crystals |
US3271636A (en) * | 1962-10-23 | 1966-09-06 | Bell Telephone Labor Inc | Gallium arsenide semiconductor diode and method |
US3300340A (en) * | 1963-02-06 | 1967-01-24 | Itt | Bonded contacts for gold-impregnated semiconductor devices |
US3349476A (en) * | 1963-11-26 | 1967-10-31 | Ibm | Formation of large area contacts to semiconductor devices |
US3370207A (en) * | 1964-02-24 | 1968-02-20 | Gen Electric | Multilayer contact system for semiconductor devices including gold and copper layers |
US3361592A (en) * | 1964-03-16 | 1968-01-02 | Hughes Aircraft Co | Semiconductor device manufacture |
US3290570A (en) * | 1964-04-28 | 1966-12-06 | Texas Instruments Inc | Multilevel expanded metallic contacts for semiconductor devices |
US3325704A (en) * | 1964-07-31 | 1967-06-13 | Texas Instruments Inc | High frequency coaxial transistor package |
US3733685A (en) * | 1968-11-25 | 1973-05-22 | Gen Motors Corp | Method of making a passivated wire bonded semiconductor device |
US3751293A (en) * | 1969-04-04 | 1973-08-07 | Bell Telephone Labor Inc | Method for reducing interdiffusion rates between thin film components |
US3654694A (en) * | 1969-04-28 | 1972-04-11 | Hughes Aircraft Co | Method for bonding contacts to and forming alloy sites on silicone carbide |
US3869260A (en) * | 1971-08-04 | 1975-03-04 | Ferranti Ltd | Manufacture of supports for use with semiconductor devices |
EP0127089A1 (en) * | 1983-05-18 | 1984-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having first and second electrodes and method of producing the same |
US4914054A (en) * | 1983-05-18 | 1990-04-03 | Kabushiki Kaisha Toshiba | Method of producing a semiconductor device provided with front and back surface electrodes |
US4702941A (en) * | 1984-03-27 | 1987-10-27 | Motorola Inc. | Gold metallization process |
US4822641A (en) * | 1985-04-30 | 1989-04-18 | Inovan Gmbh & Co. Kg | Method of manufacturing a contact construction material structure |
US4753897A (en) * | 1986-03-14 | 1988-06-28 | Motorola Inc. | Method for providing contact separation in silicided devices using false gate |
US4998158A (en) * | 1987-06-01 | 1991-03-05 | Motorola, Inc. | Hypoeutectic ohmic contact to N-type gallium arsenide with diffusion barrier |
RU2564685C1 (en) * | 2014-08-25 | 2015-10-10 | Олег Петрович Ксенофонтов | Heat fusion method |
Also Published As
Publication number | Publication date |
---|---|
FR1226492A (en) | 1960-07-13 |
BE575275A (en) | 1900-01-01 |
DE1127488B (en) | 1962-04-12 |
NL235742A (en) | 1900-01-01 |
GB911667A (en) | 1962-11-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3028663A (en) | Method for applying a gold-silver contact onto silicon and germanium semiconductors and article | |
US2861018A (en) | Fabrication of semiconductive devices | |
US2842831A (en) | Manufacture of semiconductor devices | |
US2879188A (en) | Processes for making transistors | |
US3067485A (en) | Semiconductor diode | |
US2789068A (en) | Evaporation-fused junction semiconductor devices | |
US3339274A (en) | Top contact for surface protected semiconductor devices | |
US3200490A (en) | Method of forming ohmic bonds to a germanium-coated silicon body with eutectic alloyforming materials | |
US3503125A (en) | Method of making a semiconductor multi-stack for regulating charging of current producing cells | |
US2790940A (en) | Silicon rectifier and method of manufacture | |
US2804581A (en) | Semiconductor device and method of manufacture thereof | |
US3165811A (en) | Process of epitaxial vapor deposition with subsequent diffusion into the epitaxial layer | |
US3013955A (en) | Method of transistor manufacture | |
US2802759A (en) | Method for producing evaporation fused junction semiconductor devices | |
US3065391A (en) | Semiconductor devices | |
US3356543A (en) | Method of decreasing the minority carrier lifetime by diffusion | |
US2836523A (en) | Manufacture of semiconductive devices | |
US3988762A (en) | Minority carrier isolation barriers for semiconductor devices | |
US2947924A (en) | Semiconductor devices and methods of making the same | |
US3629782A (en) | Resistor with means for decreasing current density | |
US3214654A (en) | Ohmic contacts to iii-v semiconductive compound bodies | |
US3863334A (en) | Aluminum-zinc metallization | |
US3082127A (en) | Fabrication of pn junction devices | |
US3280392A (en) | Electronic semiconductor device of the four-layer junction type | |
US3768151A (en) | Method of forming ohmic contacts to semiconductors |