JPS59132665A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59132665A JPS59132665A JP827183A JP827183A JPS59132665A JP S59132665 A JPS59132665 A JP S59132665A JP 827183 A JP827183 A JP 827183A JP 827183 A JP827183 A JP 827183A JP S59132665 A JPS59132665 A JP S59132665A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- semiconductor
- emitter region
- type emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000000465 moulding Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 230000006378 damage Effects 0.000 abstract description 3
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 241000218645 Cedrus Species 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に関し、荷にグートタンオフサイリ
スク（以下ＧＴＯと称する）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and relates to a goods container (hereinafter referred to as GTO).
ＧＴＯはゲート・カソード間を逆バイアスし、順方向電
流（アノード電流）を遮断することができ、通常のサイ
リスクに比べると伝流可成が不安であり、且つ小型＠瀘
にでき、更にゲート条件を適切に選べばスイッチング時
間を著しく小さくできるので高周波動作が出来るという
利点をゼしている。またもう一つのスイッチング素子で
あるトランジスタと比較すると、ＧＴＯはノ一方向１且
止電圧、サージ電流耐量を通常のサイリスク程度に大き
くできる点で優れている。即ちＧｉ′Ｏは通常のサイリ
スクとトランジスタの長所を兼ね備えたスイッチング素
子である。最近、ＧＴＯは省エネルギーを目的とするモ
ータコントロール用として使用されその生産は急激に壇
加することが予想されている。特にＧＴＯは中小容重か
ら大答重と適用範囲が広く、将来のスイッチングデバイ
スの主力製品になりつつある。ここでは時に中小谷ｆｆ
１２０Ａから太番＝ ３００ＡクラスのＧＴＯについて
説明する。GTO can reverse bias between the gate and cathode and cut off forward current (anode current).Compared to normal SIRISK, GTO is less stable in terms of conduction, can be made smaller, and has a lower gate condition. If selected appropriately, the switching time can be significantly reduced, giving the advantage of high frequency operation. In addition, compared to a transistor, which is another switching element, the GTO is superior in that the one-way stop voltage and surge current withstand capacity can be increased to about the same level as normal silicate. That is, Gi'O is a switching element that has both the usual silicon risk and the advantages of a transistor. Recently, GTO has been used for motor control for the purpose of energy saving, and its production is expected to rapidly increase. In particular, GTO has a wide range of applications, ranging from small and medium capacity to large capacity, and is becoming the main product of future switching devices. Here sometimes Nakakotani ff
GTOs of the 120A to 300A class will be explained.
ＧＴＯのオンオフ機構はゲートに逆バイアスを印那する
ことによって、ゲート電極の方にアノード電流を引き抜
くことができ、オン電流はカソード電極近傍かり次第に
除去される。その除去される一定４１ｍ１中カソードの
中央部に一退したアノード電流が導通を続ける、かかる
導通領域の面積が極端に小さく、且つターンオフ時間が
長い’５Ｊ合、その領域への電流集中により素子の熱破
壊が生じる欠点を有している。またＧＴＯけｎ 形ベー
スＩＡ域とＰ形ベース領域に蓄積されたキャリアを１０
μ８程度の速い時間でゲート電極から排出しなければな
らないためにキャリアの再結合を利用する方法として、
高濃度のライフタイムキラーである金拡散を実施するこ
とが行なわれる。しかしライフタイムキラーの拡散はＧ
ＴＯのゲートターンオフは促進するが、同時に保持電流
を太きくシ、且つ順方向電圧降下（ＶＴＭ）を大きくす
る欠点を有している。ターンオフタイムとＶＴＭにはト
レードオフの関係があるので順方向電圧降下を犬さくし
ない程度の範囲で制御する必要があ／、：） ０従来の
ＧＴＯとしてＰｎＰｎ構造のものについて説明する第１
図（ａ）〜（ｇ）は従来型のＧＴＯの拡散プロセスを示
す工程別所面図である。第１図（ａ）に示す高比抵抗ｎ
形シリコン基板（１０）に第１図（ｂ）に示すように両
面よりＰ形不純物を拡散することによって高濃度のＰ形
エミッタ領域（１１）及びＰ形ベース碩域（１２）を形
成する。次に第１図（Ｃ）に示すように前記シリコン基
板を熱酸化し、前記熱酸化により生成した酸化シリコン
ノｍ （１３）を周知の写真製版技術でもって窓（１４
）を形成し、次にｎ形不純物たきえばリン等を拡散して
ｎ形エミッタ領域（１４）を形成する。前記ｎ形エミッ
タ領域（１４）を形成すると同時に酸化シリコン（１３
）を２〜３μｍ形我する。第１図（（１）は前記拡散上
１呈が完了したｆｎＰｎ構造を示す。つき′に第１図Ｌ
８）に示すように前記酸化シリコン（１３）を公知の写
真製版技術もってチップ周辺部に窓をあけシリコン而を
露出させ、次に硝酸系のシリコンエツチング液でＰ杉ベ
ース領域（１２）及びｎ形ペース領域（１０）の内領域
により形成されるＰｎ接合より深くエツチングしメサ溝
（１５）を形成する。さらにＰ形エミッタ領域（１２）
側よりライフタイムキラーとして、金拡散を施す。次
に第１図（ｆ）に示すように、メサ溝（１５）の内壁ニ
パッシベーションガラスを塗布し、このパッシベーショ
ンガラスを焼成炉に入れてガラスパッシベーション膜（
１６）を形成する。次に公知の写真製版技術でｎ形エミ
ッタ領域（１４） 、及びＰ形ペース領域（１２）の表
面の酸化シリコン膜（１３）を選択的に除去すると共に
Ｐ形エミッタ領域（１１）の表面の酸化シリコン膜（１
３）も除去する。次に第１図（ｇ）に示すようにシリコ
ンが露出したｎ形エミッタ領域（１４）及びＰ形ペース
領域（１２）上に公知の蒸着法で全面に金属電極たとえ
ばＡｌを蒸着し、公知の写真製版技術テパターンニング
してカソード電４ｉ（１８）、ケート電極（１７）を形
成する。次に裏面についても同様の蒸着法でアノード電
！ （１９）を形成する。次に４００〜５００℃の加熱
炉に入れシンク−を行ない）’ｎｆ’ｎ四層構造からな
る第１図（ｇ）のＧ ’１’ Ｏを完成する。The on-off mechanism of the GTO can draw an anode current toward the gate electrode by applying a reverse bias to the gate, and the on-current is gradually removed near the cathode electrode. The anode current that has receded to the center of the cathode in the constant 41 m1 removed continues to conduct.If the area of this conductive region is extremely small and the turn-off time is long, the current concentration in that region will cause the device to It has the disadvantage of thermal destruction. In addition, the carriers accumulated in the GTO n-type base IA region and the P-type base region are
Since carriers must be discharged from the gate electrode in a fast time of about μ8, carrier recombination is used as a method.
A high concentration lifetime killer gold diffusion is carried out. However, the spread of lifetime killer is G.
Although this accelerates gate turn-off of TO, it also has the disadvantage of increasing the holding current and increasing the forward voltage drop (VTM). There is a trade-off relationship between turn-off time and VTM, so it is necessary to control the forward voltage drop within a range that does not cause it to become too narrow.:) 0First part to explain the PnPn structure as a conventional GTO
Figures (a) to (g) are step-by-step views showing the conventional GTO diffusion process. High specific resistance n shown in Figure 1(a)
As shown in FIG. 1(b), a highly concentrated P-type emitter region (11) and a P-type base region (12) are formed in a silicon substrate (10) by diffusing P-type impurities from both sides. Next, as shown in FIG. 1(C), the silicon substrate is thermally oxidized, and the silicon oxide layer (13) produced by the thermal oxidation is applied to the window (14) using a well-known photolithography technique.
), and then an n-type impurity such as phosphorus is diffused to form an n-type emitter region (14). At the same time as forming the n-type emitter region (14), silicon oxide (13) is formed.
) in the shape of 2 to 3 μm. Figure 1 ((1) shows the fnPn structure in which the above diffusion process has been completed.
As shown in 8), the silicon oxide (13) is etched using a known photolithography technique to open a window around the chip to expose the silicon layer, and then etched with a nitric acid-based silicon etching solution for the Pcedar base region (12) and n. A mesa groove (15) is formed by etching deeper than the Pn junction formed by the inner region of the shaped space region (10). Furthermore, the P-type emitter region (12)
Apply gold diffusion from the side as a lifetime killer. Next, as shown in FIG. 1(f), a passivation glass is applied to the inner wall of the mesa groove (15), and this passivation glass is placed in a firing furnace to form a glass passivation film (
16). Next, the silicon oxide film (13) on the surfaces of the n-type emitter region (14) and the P-type space region (12) is selectively removed using a known photolithography technique, and the silicon oxide film (13) on the surface of the P-type emitter region (11) is removed. Silicon oxide film (1
3) is also removed. Next, as shown in FIG. 1(g), a metal electrode such as Al is deposited on the entire surface of the n-type emitter region (14) and the P-type space region (12) where silicon is exposed by a known vapor deposition method. A cathode electrode 4i (18) and a cathode electrode (17) are formed by photolithography and patterning. Next, apply the same vapor deposition method to the back side to create an anode! (19) is formed. Next, it is placed in a heating furnace at 400 to 500 DEG C. and subjected to sinking to complete G'1'O of FIG. 1(g), which has a 'nf'n four-layer structure.
このような従来のＧＴＯに於ては、オン電流はＰ形エミ
ッタ領域（１１）からカソード電極（１８）へと流れる
。このオン状態からオフ状態に移行する１余、ｎ型エミ
ッタ領域（１４）のＰ型ベース領域（１２）の近傍から
オン直流が除去されるが、ｎ型エミッタ領域（１４）の
中央部では導通を続け、その結果、導通領域の面積がｆ
ｌｉ端に小さく、且つターンオフ時間が長い為電流集中
によって素子の熱１波壊が生じると言った欠点をＭして
いる。In such a conventional GTO, on-current flows from the P-type emitter region (11) to the cathode electrode (18). During this transition from the on state to the off state, on-direct current is removed from the vicinity of the P-type base region (12) of the n-type emitter region (14), but conduction occurs in the central part of the n-type emitter region (14). As a result, the area of the conducting region becomes f
The drawback is that the li end is small and the turn-off time is long, so one wave of heat damage to the element occurs due to current concentration.
不発明は上記従来のＧＴＯの欠点を取除くためになされ
たものであり、前記［１の半辱体領域と第２の半導体碩
との間Ｑ４の半等体碩域に対応して第２４電型の高濃度
の領域を形成し、第１の半導体領域からのキャリアの住
人を再結合しｆＪ４の半導体領域中央部へのキャリアの
注入を少なくして、ターンオフ時間を短縮することを目
的とする。The invention was made in order to eliminate the drawbacks of the conventional GTO, and there is a The purpose is to shorten the turn-off time by forming a region with high concentration of the electric type and recombining the carrier residents from the first semiconductor region to reduce the injection of carriers into the central part of the semiconductor region of fJ4. do.
第２図（ａ）〜（ｊ）は不発明の一芙流側のＧＴＯの製
造方法を示す工程別所面図である。′第２図（ａ）に示
す高地抵抗ｎ形シリコン基板（１０）に第２図（ｂ）に
示すように両面よりＰ形不純物を拡散することによって
高濃度のＰ形ベース領域（１２）、Ｐ形・領域（１２’
）を形成する。次に第２図（Ｃ）に示すように前記Ｐ形
碩域（１２’）をラッピングして途去する。次に第２図
（Ｃ）に示すようにＦＩＩＪ記シリコン基板を熱酸化し
て、酸化シリコン絶縁膜（１３）を形成する。久に第２
図（ｄ）に示すように酸化シリコン絶縁ノ漠（１３）を
周知の写真製版技術により窓を形成し、ｎ形不純物、た
とえばリン等を拡散して島状のｎ−）７杉高濃度領域（
２０）を形成する。次に第２図（ｉｌｌ）に示すように
前記ｎ十形高濃度領域（２０）を深く拡散し、且つ前記
拡散で形成された酸化シリコン絶縁膜（１３）の片面を
除去し、前記酸化シリコン絶縁膜（１３）が除去された
表向にボロン弄を拡散してＰ形エミッタ領域（１１）を
形成する。次に前記Ｐ形エミッタ領域を深く拡散する。FIGS. 2(a) to 2(j) are process-by-step diagrams showing a method of manufacturing GTO according to one aspect of the invention. 'By diffusing P-type impurities from both sides of the high resistance n-type silicon substrate (10) shown in FIG. 2(a) as shown in FIG. 2(b), a highly concentrated P-type base region (12), P type/area (12'
) to form. Next, as shown in FIG. 2(C), the P-shaped area (12') is wrapped and removed. Next, as shown in FIG. 2C, the FIIJ silicon substrate is thermally oxidized to form a silicon oxide insulating film (13). Second time in a while
As shown in Figure (d), a window is formed in the silicon oxide insulating layer (13) using a well-known photolithography technique, and an n-type impurity such as phosphorus is diffused into an island-like n-)7 cedar high concentration region. (
20). Next, as shown in FIG. 2 (ill), the nx type high concentration region (20) is deeply diffused, and one side of the silicon oxide insulating film (13) formed by the diffusion is removed, and the silicon oxide A P-type emitter region (11) is formed by diffusing boron on the surface from which the insulating film (13) has been removed. The P-type emitter region is then deeply diffused.
欠に、第２図（ｆ）に示すように熱酸化ノ漠（１３）を
周知の写真製版技術でもって窓を形成し、次にｎ形不純
物たとえばリン等を拡散してｎ形エミッタ領域（１４）
を形成する。、、Ｉｊ記ｎ形エミッタ領域（１４）を形
成すると同時に酸化シリコンｒｇ （１３）が２〜３μ
ｍ形成される。第２図（ｇ） Ｐｉ曲前払散工程が光丁
したＰｎＰｎ四層構造を示す。なお、島状のｎ−１−４
杉高濃度領域（２０）を回帰する８士領域（２１）はＧ
ＴＯの耐圧を床つために設けられる。！ｇ２図（ｈ）か
ら（ｊ）の工程は前記従来のＧＴＯの製造工程と同様の
ため説１ツＪを省１＠する。First, as shown in FIG. 2(f), a window is formed using a thermal oxidation layer (13) using a well-known photolithography technique, and then an n-type impurity such as phosphorus is diffused to form an n-type emitter region (13). 14)
form. ,, At the same time as forming the n-type emitter region (14) in Ij, the silicon oxide rg (13) is
m is formed. FIG. 2(g) shows a PnPn four-layer structure in which the Pi pre-dispersion process is completed. In addition, island-like n-1-4
The 8-year-old area (21) that regresses the cedar high concentration area (20) is G
It is provided to increase the pressure resistance of TO. ! g2 The processes shown in Figures (h) to (j) are similar to the manufacturing process of the conventional GTO, so explanation 1J will be omitted.
本発明の一実施例は第２図（ｊ）で明らかのようにｎ形
ペース領域とＰ形エミッタ領域間にこれらをまたぐよう
に部分的にｎ十形高一度領域全形成し、且つｎ十型高譲
度−領域がｎ型エミッタ領域（１４）に対応してニニ＝
れるため、従来のもののようなｎ型′エミツク領域中央
部への電流果中が少なくなりＧＴＯが熱破壊しなくなっ
た。As is clear from FIG. 2(j), one embodiment of the present invention is to partially form an n-type high-height region between an n-type pace region and a p-type emitter region so as to straddle them, and Type high yield-region corresponds to n-type emitter region (14) =
As a result, the current flow to the central part of the n-type emitter region, unlike in the conventional case, is reduced, and the GTO is no longer subject to thermal breakdown.
なお、ｎ形エミッタ領域（１４）は複数のストライプ状
に形成されその幅は１５０〜３（）０μＩｎ１長さは１
ｍｍ〜２ｖａｍＸ深さは２０μｍである。またＰ形ベ
ース領域（１２）の深さ４０μｆｎＸｎ形ペース追域（
１０）の深さは２００μｍである。島状のｎ十形高濃度
領域（２０）の厚さは３ Ｑ ｆｉｍ 、 １１ｉは１
００〜３００／ｉｎ１長さば１． ｍｇ 〜２ ｍｒｘ
である。Ｐ形エミッタ領域（１１）の深さに１２Ｌｌμ
Ｉ１１である。The n-type emitter region (14) is formed in a plurality of stripes, the width of which is 150~3()0μIn1, and the length is 1
mm~2vam×depth is 20 μm. In addition, the depth of the P-type base region (12) is 40μfnXn-type pace tracking area (
The depth of 10) is 200 μm. The thickness of the island-shaped n-domain high concentration region (20) is 3 Q fim , and 11i is 1
00-300/in1 length bar 1. mg ~ 2 mrx
It is. 12Llμ to the depth of the P-type emitter region (11)
It is I11.
ｎ形エミッタ領域（１４）は上記ストライプ状のものだ
けに限定されるものではなく、例えば枝状であってもよ
い。The n-type emitter region (14) is not limited to the above-mentioned stripe shape, but may be branch-like, for example.
以上説明のように、本発す１ｉｌ−を第１の半導体領域
と第２の半導体領域との間の第４の半導体領域に対応す
る位置に第２４電形の晶譲度島状領域を設けたので、タ
ーンオフ時に電流東中による熱破壊が生じない優れた半
導体装置を得ることができるという幼果を有する。As explained above, the presently produced 1il- is provided with a crystal yield island-like region of the 24th electric type at a position corresponding to the fourth semiconductor region between the first semiconductor region and the second semiconductor region. Therefore, it is possible to obtain an excellent semiconductor device that does not suffer from thermal damage due to current flow during turn-off.
第１図（ａ）〜（ｇ）は従来のＣ）Ｔｏの製造方法を示
す工程別所面図、第２図（ａ）〜（ｊ）は本発明の一実
施例の製造方法を示す工程別所面図である。
（１０）はｎ形ベース領域、（１１）はＰ形エミッタ領
域、（１２）はＰ形ベース碩域、（１４）はｎ形エミッ
タ領域、（２０）は島状のｎ十形高濃度領域を示す。
図中同−付″８は同一または相当部分を示す。
代理人葛野 偵−
第１図FIGS. 1(a) to (g) are step-by-step views showing a conventional manufacturing method for C)To, and FIGS. 2(a) to (j) are process-by-step views showing a manufacturing method according to an embodiment of the present invention. It is a front view. (10) is an n-type base region, (11) is a p-type emitter region, (12) is a p-type base rectangular region, (14) is an n-type emitter region, and (20) is an island-like n-type high concentration region. shows. Reference numeral ``8'' in the figure indicates the same or equivalent part. Agent Kazuno Rei - Figure 1
Claims (1)
体領域とＰｎ接合をなし第２の尋電戯の第２の半導体領
域と、該第２の半導体領域とＰｎ接合をなし第１の導電
型の第３の半導体領域と、前記第３の半導体領域とＰｎ
接合をなし第２の導電型の第４の半導体領域とを１えた
ものにおいて、前記第１の半導体領域と前記第２の半導
体領域との間の前記第４の半導体領域に対応する位置に
第２４成形の高濃度島状領域を設けたこと金荷徴とする
半導体装置。A semiconductor region of fJl of a first conductivity type, a second semiconductor region forming a Pn junction with the %1 semiconductor region, and a second semiconductor region forming a Pn junction with the second semiconductor region; a third semiconductor region having a conductivity type of Pn
a fourth semiconductor region of a second conductivity type that forms a junction, and a fourth semiconductor region that is located between the first semiconductor region and the second semiconductor region and corresponds to the fourth semiconductor region; A semiconductor device characterized by the provision of a high concentration island-like region of 24 molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP827183A JPS59132665A (en) | 1983-01-19 | 1983-01-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP827183A JPS59132665A (en) | 1983-01-19 | 1983-01-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59132665A true JPS59132665A (en) | 1984-07-30 |
Family
ID=11688499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP827183A Pending JPS59132665A (en) | 1983-01-19 | 1983-01-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59132665A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0241662A2 (en) * | 1986-04-12 | 1987-10-21 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Turn-off thyristor |
| JPH02214161A (en) * | 1989-02-15 | 1990-08-27 | Hitachi Ltd | Gate turn-off thyristor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5081290A (en) * | 1973-11-16 | 1975-07-01 | ||
| JPS5610970A (en) * | 1979-07-09 | 1981-02-03 | Mitsubishi Electric Corp | Thyristor |
-
1983
- 1983-01-19 JP JP827183A patent/JPS59132665A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5081290A (en) * | 1973-11-16 | 1975-07-01 | ||
| JPS5610970A (en) * | 1979-07-09 | 1981-02-03 | Mitsubishi Electric Corp | Thyristor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0241662A2 (en) * | 1986-04-12 | 1987-10-21 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Turn-off thyristor |
| JPH02214161A (en) * | 1989-02-15 | 1990-08-27 | Hitachi Ltd | Gate turn-off thyristor |
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