JPS6017935A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6017935A
JPS6017935A JP58125305A JP12530583A JPS6017935A JP S6017935 A JPS6017935 A JP S6017935A JP 58125305 A JP58125305 A JP 58125305A JP 12530583 A JP12530583 A JP 12530583A JP S6017935 A JPS6017935 A JP S6017935A
Authority
JP
Japan
Prior art keywords
electrodes
carrier
recess
chip carrier
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58125305A
Other languages
Japanese (ja)
Inventor
Kenji Tominaga
健司 富永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58125305A priority Critical patent/JPS6017935A/en
Publication of JPS6017935A publication Critical patent/JPS6017935A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67138—Apparatus for wiring semiconductor or solid state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To facilitate high density mounting and prealignment by wiring both upper and lower surfaces of a chip carrier with wiring conductor terminals, and conductively securing the terminals to a mother board. CONSTITUTION:Electrodes 2 and 6 are respectively arranged on the lower and upper surfaces of a chip carrier 1. The carrier 1 can be readily inserted into a mother board 3, a recess 7 having a gap within a self-alignment limit due to the surface tension of solder is provided, an electrode 8 is formed on the bottom of the recess 7, and an electrode 9 is formed on the front surface. The electrodes are connected by solder 5 between the opposed electrodes in the vicinity. Thus, the electrodes 2, 6 of the carrier 1 are respectively connected to the electrodes 8, 9 in the recess 7 and on the front surface, thereby performing high density of electrodes by a stereoscopic array. When the carrier 1 is disposed in the recess 7, both can be readily positioned, a prealignment can be suitably facilitated, and the self-alignment by solder can be reliably performed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置のパッケージの一種として広く用
いられるチップキャリアおよびマザーボードの実装体に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a package of a chip carrier and a motherboard that are widely used as a type of package for semiconductor devices.

従来例の構成とその問題点 チップキャリア（イ？１造の半導体装置は、その配線形
態として、マザーボードに直接はんだ付けされる。第１
図は従来例の断面図であり、セラミック・チップキャリ
ア１が、その電極２を、マザーボード３側の電極４に、
ばんだ５を介して接続されている。ところで、チップキ
ャリアでは、電極数の増加と共に、マザーボードとの接
触側面積を拡大しなければ々らず、実装密度が上がらな
い。Conventional configuration and its problems Chip carrier (I) One-manufactured semiconductor devices are directly soldered to the motherboard as their wiring form.
The figure is a cross-sectional view of a conventional example, in which a ceramic chip carrier 1 connects its electrode 2 to an electrode 4 on the motherboard 3 side.
They are connected via a bander 5. By the way, in a chip carrier, as the number of electrodes increases, it is necessary to increase the surface area of contact with the motherboard, and the packaging density cannot be increased.

寸だ、チップキャリア１とマザーボード３とのアライメ
ントは、プリアラインが十分になされている状態であれ
ば、はんだの表面張力に」二って５着実にセルファライ
ンされるが、プリアラインが不十分であれば、はんだ接
続が不十分になることから、プリアラインの確実に行な
われる構造であることも好ましいことである。The alignment between the chip carrier 1 and the motherboard 3 will be steadily self-aligned due to the surface tension of the solder if the pre-alignment is sufficient, but if the pre-alignment is insufficient. If this is the case, the solder connection will be insufficient, so it is also preferable to have a structure in which pre-alignment can be performed reliably.

発明の目的 本発明は、従来例にみられた問題点をことごとく解消す
るものであり、高密度実装ならびにプリアラインの容易
な構造のチップキャリア型半導体装置を提供するもので
ある。OBJECTS OF THE INVENTION The present invention solves all the problems seen in the conventional example, and provides a chip carrier type semiconductor device having a structure that facilitates high-density packaging and pre-alignment.

発明の構成 ３　、　、 本発明は、要約するに、半導体チップを封有するチップ
キャリアの上面および下面の両面に配線用導体端子部を
配設し、前記配線用導体端子部をマザーボードに勇電固
着した半導体装置であり、これに１こり、千ノブキャリ
アの導体端子の配列が、同じチップキャリアサイズのも
ので、最大２倍の電極数で可能であり、寸だ、各電極間
の間隔を十分に確保できるので、電極接続も容易である
。Structure 3 of the Invention In summary, the present invention provides wiring conductor terminal portions on both the upper and lower surfaces of a chip carrier that encapsulates a semiconductor chip, and the wiring conductor terminal portions are electrically fixed to a motherboard. This is a semiconductor device with a chip carrier of the same size, and the arrangement of conductor terminals on a 1,000-knob carrier is possible with up to twice the number of electrodes, and the spacing between each electrode is sufficient. electrode connection is also easy.

実施例の説明 第２図は本発明の一実施例断面図であり、セラミック・
チップキャリア１には、下面の電極２のほかに、」二面
にも電極６が配設されている。そして、マザーボード３
には、チップキャリア１が楽に入り、かつ、ににんだの
表面張力によるセルファラインメン１−眼Ｗ以内の隙間
を有する凹陥部７を有し、その凹陥部７の底に電１？ｊ
ｊｓを形成し、１だ、表部にも、電極９を有する。各電
極の接続は、近接して対向する電（Ｔ間をはんだ６によ
って行表う。DESCRIPTION OF EMBODIMENTS FIG. 2 is a sectional view of an embodiment of the present invention.
In addition to the electrodes 2 on the lower surface, the chip carrier 1 is provided with electrodes 6 on its second surface. And motherboard 3
has a recess 7 into which the chip carrier 1 can be easily inserted and has a gap of less than 1 - 1 W due to the surface tension of the resin. j
1, and also has an electrode 9 on its surface. Connection of each electrode is performed by solder 6 between adjacent electrodes (T).

この１１？１造によれば、チップキャリア１の電極２お
よび同６がそれぞれ、マザーボード３の凹陥部７内の電
極８および表面の電極９と接続され、立体的配列による
電極の高密度化が達成される。According to this 11-1 structure, the electrodes 2 and 6 of the chip carrier 1 are connected to the electrodes 8 in the recess 7 of the motherboard 3 and the electrodes 9 on the surface, respectively, and the three-dimensional arrangement of the electrodes increases the density of the electrodes. achieved.

寸だ、チップキャリア１をマザーボード３に形成されだ
凹陥部７に配設すると、両者間の位置合せが容易であり
、これによって、プリアラインも適切、十分に行なわれ
、はんだによるセルフアライメントも確実に行なうこと
ができる。By placing the chip carrier 1 in the recess 7 formed on the motherboard 3, alignment between the two is easy, and as a result, pre-alignment is properly and sufficiently performed, and self-alignment by solder is also ensured. can be done.

２ｒＩ；３図は、本発明の別の実施例断面図であり、セ
ラミック・チップギヤリア１の側面をテーバ状に々し、
これに対応して、マザーボード３の凹陥部７も、その側
面をテーパ状に外したものである。2rI; 3 is a sectional view of another embodiment of the present invention, in which the side surface of the ceramic chip gear 1 is tapered,
Correspondingly, the concave portion 7 of the motherboard 3 also has its side surfaces tapered off.

とれによれば、マザーボード３への千ノブキャリア１の
配置、いわゆる、プリアラインが容易になり、作業性の
向−にがはかられ、生産コヌトの低減にもなる。According to Tore, the placement of the 1000-knob carrier 1 on the motherboard 3, so-called pre-alignment, becomes easier, which improves workability and reduces production costs.

なお、従来例、各実施例とも、半導体チップ１０は、チ
ップキャリア１の所定載置面に置かれ、金属細線１１で
結線されており、上面の蓋１２でおおわれた構造である
。In both the conventional example and each of the embodiments, the semiconductor chip 10 is placed on a predetermined mounting surface of the chip carrier 1, connected with thin metal wires 11, and covered with a lid 12 on the top surface.

発明の効果 ５　・　−・ 本発明に」これば、チップキャリアの上面および下面に
電極を配列することにより、同一面積のチップギヤリア
で最大２倍の電極配設が可能であり高密度実装を容易に
する。Effect of the invention 5 - According to the present invention, by arranging the electrodes on the upper and lower surfaces of the chip carrier, it is possible to arrange up to twice as many electrodes in the same area of the chip gear carrier, facilitating high-density mounting. do.

寸だ、マザーボード面に凹陥部を設けて、との凹陥部に
前記チップキャリアを配置することにより、電極接続の
立体化が可能であり、チップキャリアとマザーボードと
の電極間接続のだめのプリアラインならびにセルファラ
インメン１゛の処理が容易になり、生産性の向」二をも
達成し得る。By providing a recess on the surface of the motherboard and placing the chip carrier in the recess, three-dimensional electrode connection is possible. Processing of the self-aligned line 1 is facilitated, and productivity improvements can also be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例の断面図、第２図ならびに第３図は本発
明の各実施例断面図である。 １・・・・・・チップキャリア、２，４，６，８．９・
・・・・・電極、３・・・・・・マザーボード、５・・
・・・・はんだ、７・・・・・・凹陥部、１０・・・・
・・半導体チップ、１１・・・・・・金属′細線、１２
・・・・・・蓋。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第１
図FIG. 1 is a sectional view of a conventional example, and FIGS. 2 and 3 are sectional views of each embodiment of the present invention. 1... Chip carrier, 2, 4, 6, 8.9.
...Electrode, 3...Motherboard, 5...
... Solder, 7 ... Concave portion, 10 ...
...Semiconductor chip, 11...Metal' thin wire, 12
······lid. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (3)

【特許請求の範囲】[Claims] （１）　？１′４体チップを」さ１有するチップキャリ
アの−に面お」：び下面の両面に配線用導体端子部を配
設し、前記配線用導体端子部をマザーボードに導電固着
した半導体装置。(1)? A semiconductor device in which wiring conductor terminal portions are provided on both sides of the upper and lower surfaces of a chip carrier having a four-piece chip, and the wiring conductor terminal portions are conductively fixed to a motherboard. （２）　チップキャリアがマザーボードの凹陥部に配置
されて′なる特許請求の範囲第１項に記載の半導体装置
。(2) The semiconductor device according to claim 1, wherein the chip carrier is disposed in a recessed portion of a motherboard. （３）チップキャリアがテーバ状側面を有する特許請求
の範囲第１項に記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the chip carrier has a tapered side surface.
JP58125305A 1983-07-08 1983-07-08 Semiconductor device Pending JPS6017935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58125305A JPS6017935A (en) 1983-07-08 1983-07-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58125305A JPS6017935A (en) 1983-07-08 1983-07-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6017935A true JPS6017935A (en) 1985-01-29

Family

ID=14906798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58125305A Pending JPS6017935A (en) 1983-07-08 1983-07-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6017935A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0915641A1 (en) * 1997-11-05 1999-05-12 Nec Corporation Surface mount assembly for electronic components

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0915641A1 (en) * 1997-11-05 1999-05-12 Nec Corporation Surface mount assembly for electronic components

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