JPS60178770A - Electronic device - Google Patents

Abstract

PURPOSE:To reduce the cost and to process data at a high speed with an electronic device by securing synchronization between actions between a double writing control means of data and a clear means against a memory means which stores the picture information. CONSTITUTION:A bidirection data bus 101 of a CPU is provided together with an address bus 102, AND gates 103 and 104, an OR gate 105, a RAM106, a latch 107, a 3-state gate 108, and a timing signal generator 109 which produces signals 111 and 112 after a fixed period of time from the rise of a signal 110 sent from the CPU. A signal 113 is set at ''H'' and ''L'' in the write and read modes of the CPU respectively. In such a constitution, a double writing action is carried out synchronously with the writing action of the CPU. Then the RAM 106 is cleared concurently with the reading action of the CPU. In addition, said timing is secured by the same timing generating circuit 109 and according to a shown timing chart. This can increase the processing speed of the CPU.

Description

[Detailed Description of the Invention] [Prior Art] Conventionally, there has been a method in which information such as code data sent from a host computer etc. is developed as a bit image on an internal random access memory, and then this is read out and output. In an output device such as a laser beam printer (LBV), writing to the random access memory requires so-called overwriting.

That is, for example, when outputting the pattern shown in FIG. 1(a), the pattern shown in FIG. 1(b) is first written, and then the 11ff
This means that the pattern i(c) is overwritten.

It is very difficult to judge whether a pattern to be written is one that is simply written or one that should be overwritten, so it is necessary to clear the random access memory to be written in advance.

Therefore, it is necessary to clear the portion of the data that has been expanded onto the random access memory and read it again to finish printing each time.

However, the above operation cannot be performed if the text output device is slow and the CP
If the processing speed of U is sufficient, it can be achieved by the operation of the CPU alone, or if the processing speed of a laser beam printer or other high-speed printer is high enough, the operation of the CPU is not enough.
Usually, a high-speed sub-processor is used to perform parallel processing with the CPU, which has the disadvantage that the entire processing device becomes very expensive.

〔the purpose〕

In view of the above points, it is an object of the present invention to eliminate the above-mentioned drawbacks, and to provide an electronic device that is inexpensive and capable of high-speed data processing. - [Example] The present invention will be described in detail below with reference to the drawings.

FIG. 2 is an external view of a page printer which is a laser beam printer to which the present invention is applied.

1 is a printer main body, 2 is an operation display section, and 3 is a power switch. Further, 4 is a paper discharge section. Reference numeral 5 denotes a transmission cable, which is connected to a host. The printer 1 may be a terminal in a network or a fax machine. The interface is Centronics' interface method,
The R3232-C system or a video signal may be input. In addition, the operation display unit 2 has the rON LINE J key to indicate that data is being transmitted from the host, the rERROR5KIPJ key to skip errors,
It also has keys for self-diagnosis, manual feeding, and keys for outputting data up to the point of transmission rather than printing each page. 6 is a ROM cartridge in which character fonts such as alphabets and kanji characters and programs are stored.

FIG. 3 is a block diagram showing an embodiment of the invention.

In Fig. 2, 101 is the CPU's bidirectional data/hess consisting of 8 bits, and 102 is the same <1 of the CPU.
6-bit address bus, 103° and 104 are A, ND
gate, 105 is an OR gate, 106 is a gate with a capacitance of 1, for example
28K byte random access memory (hereinafter referred to as RA)
(referred to as M). Note that the information written to the RAM 106 can be used with an inkjet printer, LED printer, or LB.
It is output to various output devices 999 such as a P printer. or,
RAM 106 may be a computing device such as a microprocessor. Reference numeral 107 indicates a rat≠, 108 indicates a three-state gate, and 109 indicates a timing signal generator that generates the signal 111 and the signal 112 after a certain period of time from the rise of the signal 11O from the CPU. The timing is shown in a timing chart.

In addition, the signal 113 is at H level when the CPU is in a write operation.
This is a level signal that is at L level during a read operation.

Figure 4 shows the timing of each signal when the signal 113 is at H level, that is, the CPU write operation, and Figure 5 shows the timing of each signal when the signal 113 is at the H level.
13 shows the timing of each signal when the signal is at the L level, that is, during the read operation of the CPU.

Hereinafter, the operation of the Kinomio side will be explained based on FIGS. 3 to 5.

First, the write operation of the CPU will be explained.

The code information sent from the host device (not shown) is
It is also converted into corresponding dot pattern information by a CPU (not shown) and output to the data bus 101. Next, the CPU expands the dot pattern data output to the data bus 101 onto the RAM 106.
Address information 102 is output to 6, and signal 113 is set to H.
level (during CPU write operation). Thereafter, a signal 110 is sent to the timing signal generator 109 to start the timing signal generator 109 (FIG. 4).

The RAM 106 given the address information 102 outputs the read data 114 at timing 401 in FIG. 4 after obtaining a predetermined access time (■ in FIG. 4). The read data 114 is latched by the latch 107 by the signal 111 (FIG. 4). Since signal 113 is at H level, AND gates 103 and 104 are open. Therefore, information 116, information 117, information 101, and information 11
8 have the same content.

Furthermore, the three-state gate 108 is closed.

Information 117 and information 118 are ORed by OR gate 1o5.
is taken and written to the RAM 106 as information 115 by the write signal 112 to the RAM 106 (the fourth
Figure ■).

That is, OR information with data previously written in the RAM is written, which corresponds to overwriting.

Next, referring to FIG. 5, the read operation of the CPU will be described.

The dot pattern data developed on the RAM 106 is
After the development is completed, it is sent to a printing section (not shown).

- Since the dot pattern data sent to the star printing section no longer needs to be saved, the contents of the RAM at that address must be cleared.

The CPU sends the dot pattern data developed on the RAMI OS to the printing section (not shown) via the data bus 101, so the CPU sets the signal 113- to the L level (CPU (7)!
(during J-mode operation) Address information 102 is sent to the RAM 106 in order to read the contents of the RAM 106 (7).

Further, as shown in FIG. 5, a signal 110 is sent to the timing signal generator 109, and the timing signal generator
(Fig. 5 ■).

After a predetermined access time (■ in Figure 5), RAM1
06 outputs read data 114, which is latched into the latch 107 by the latch signal 111 (Fig.
).

Since the signal 113 is at L level, the three cheat game
) 108 is open, and the same contents as the read data 114 from the RAM are sent to the data bus ioi.

Further, since AND gates 103 and 104 are both closed, information 117 and information 118 are both all 0s, and therefore information 115 is also all 0s.

At the same time, information 115 whose content is all O is written to the RAM 106 by the write signal 112 (fifth
(■) in the figure, that is, the RAM 106 is cleared.

〔effect〕

As detailed above, the overwrite operation is performed simultaneously during the CPU write operation, the RAM clear operation is performed simultaneously during the CPU read operation, and the above timing is controlled by using the same timing generation circuit. The speed can be significantly improved, and the load on the CPU can be reduced.

Furthermore, as described in detail above, according to the present invention, when the CPU reads data, the RAM is simultaneously cleared by the same timing generation circuit, thereby significantly improving the processing speed of the CPU.

Further, according to the present invention, it was possible to provide an electronic device that is inexpensive and capable of high-speed data processing.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of overwriting in which the pattern (b) is written, the pattern (c) is overwritten, and the pattern (a) is output. FIG. 2 is an external view of a printer to which the present invention is applied. FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 4' is a signal timing chart when the signal 113 is at H level. FIG. 5 is a signal timing chart when the signal 113 is at L level. 109 is a timing signal generator, 106 is a RAM, and 113 is a level signal. Applicant Canon Co., Ltd./15---------ZH1/ALiD=
===llj--1111-1LL#sai-ru

Claims (1)

[Scope of Claims] Memory means for storing image information as bit image data; data overwriting control means for overwriting data on the memory means; clearing means for clearing data in the memory means; An electronic device characterized in that the operation timings of the writing control means and the clearing means are in a synchronous relationship with each other.