JPS60178718A - Receiver circuit - Google Patents

Abstract

PURPOSE:To always keep the high frequency accuracy by storing the control data corrected so that the minimum step frequency of the 2nd local oscillator is held in response to the operation of a correction switch when the power supply of a device is applied and setting the lower digits of the reception frequency by the control data in a reception mode. CONSTITUTION:The frequency display of a receiver is set at a correction frequency through a tuning circuit by the reset release of a CPU or the operation of a correction switch 18 when a power supply is applied. The correction reference data on the CPU to be applied to a D/A converting circuit 16 which delivers the control voltage 161 for the 2nd local oscillation frequency is stored to the CPU. Then the data on each point where the demodulation output frequency increases with the minimum reception frequency is stored over the variation range of lower digit frequencies. Then the lower digit frequencies is reproduced and set by the stored data on the minimum frequency step in a reception mode according to the frequency control operation of the function 17.

Description

[Detailed Description of the Invention] This invention is based on PLL (Phase Loeked Lo
op) In a radio receiver configured to set the upper digits of the reception frequency using the first local oscillator under control, and set the lower digits of the reception frequency by finely adjusting the second local oscillation frequency, the fine adjustment of the second local oscillator Adjusted Stesono frequency data for all CPUs (
By storing and reproducing the signals in the central processor unit (Central Processor Unit), it is possible to obtain a receiver circuit in which the configuration of the first local oscillator is simplified and the frequency setting accuracy of the lower digits is the same as described above.

Recent radio receivers for intermediate and higher grades have a second local oscillator that injects the local oscillation frequency into the first mixer of the super-hetero gain type.By using the PLL control method, high stability of the oscillation frequency and high precision of frequency setting are achieved. It is now possible to However, in practice, there are problems caused by the basic performance of the PLL control circuit. For example, in the basic method of a PLL controlled oscillator, the variable step frequency of the oscillation frequency is the same as the reference frequency input to the phase comparator, so for example, the minimum variable step of the tuning frequency is set to 100 Hz.
(100 Hz step variable is the minimum requirement for SSB radio wave reception), the reference frequency should be set to 10
0Hz, which can be obtained comparatively easily by dividing the output of the crystal oscillator.
The control output of the phase comparator is converted to VCO (VoltageCon
LPF (Low Pa5s Fite) added to the circuit added to the trolled 0scillator
The cutoff frequency of r ) must be set extremely low, and as a result of the large time constant of the LPF, the lock-up time (the time it takes for the oscillation frequency to stabilize in phase synchronization) when the frequency changes becomes long. , the tuning operation not only feels unnatural but also may generate noise.

The second problem is that the lower the reference frequency is, the more difficult it becomes to remove ripples in the control voltage of the VCO, and the C/N of the local oscillator output deteriorates. As a countermeasure, the reference frequency should be set high, for example, 10 kHz or more, and only the upper digits of the receiving frequency should be set to iPLL.For the lower digits, a mixer stage should be installed in the middle of the PLL circuit, and the local oscillation frequency should be set to another PLL circuit.
There is a multiplex PLL control method in which all lower digit frequencies are set using a LL control oscillator, but this is of course expensive, so intermediate models use this local oscillator f VXO (Variable Xry
In some cases, the oscillation frequency of an oscillator with relatively good frequency stability, such as an oscillator (stal 0scillator), is finely adjusted (for example, in the 10 kHz range) and the lower digits are displayed assuming equal division. Its feature is that continuous frequency setting is possible, but the frequency accuracy is inferior to that of the 9th generation.

As another measure, the first local oscillator may have a frequency of, for example, 10kHz.
There is a method in which only the above upper digit frequencies are set, and the lower digit frequencies are set by finely adjusting the second local oscillation frequency of the second mixer between the first intermediate frequency stage and the second intermediate frequency stage. This format simplifies the configuration of the first local oscillator, improving the stability and C/'N of the PLL circuit, but there is no benefit in using the PLL method or VXO method for fine-tuning the frequency of the second local oscillator. This is the same as in the previous case.

As shown in the figure, a frequency marker generator 15 is controlled by a single reference oscillator 13.
, a PLL-controlled first local oscillator 11, a microcomputer 12, a second local oscillator whose frequency is controlled by the microcomputer 12 to set the upper digits of the reception frequency, and a second local section for the intermediate frequency interstage mixer 5. oscillator 6;
In a wireless receiver of the type that finely adjusts the oscillation frequency and interpolates the lower digits of the received frequency, the second local oscillator 6
This receiver circuit is characterized in that control data 121 calibrated to maintain the minimum step frequency of is stored in the CPU 12, and upon reception, the lower digits of the injury frequency are set based on the data 121.

Here, the first local oscillator is under PLL control, and the basic configuration is that the output of the VCO 31 is injected into the first mixer 2, frequency-divided by the programmable frequency divider 32, and then phase-divided by the phase comparator 33 to the reference frequency 141. In comparison, the configuration is such that the VCO 31ffi is controlled by a control voltage 133 corresponding to the phase difference between the image frequencies, and the VCO frequency is stabilized when the phase difference of the phase comparator is O. However, in the figure, the LPF of the control voltage 133 circuit
is omitted from the description. In order to perform all settings up to the 10kHz digit of the reception frequency using the first local oscillator, the PLL reference frequency 141 is normally set to IQk)Iz, so the output of the several MHz crystal oscillator 13 is The output of the oscillator 13 is obtained by dividing the frequency by 14, but the output of the oscillator 13 is
It also serves as the reference frequency for the oscillator and marker generator, and by controlling the main frequency relationships within the nine devices using the frequency of a single reference oscillator, adjustments and maintenance to maintain frequency accuracy are possible. It is often used because it has the effect of making it easier.

The output of the first mixer passes through the first IF filter 4 and is added to the second mixer 5. However, since the filter 4 only needs to be used to an extent that does not cause intermodulation interference in the second mixer, the passband width is 10 to 2.
A relatively simple configuration such as a 0 kHz monolithic type may be used. Buffer amplifiers and the like are omitted from the diagram.

When converting to the second IF with the second mixer 5, the oscillation frequency of the second local oscillator 6 is finely adjusted to interpolate the intermediate change in the frequency interval of the 10 kHz step set in the first local oscillator. , a change of 10 kHz is sufficient for an oscillation frequency of several MI (z or more), so a simple and relatively stable VXO is used, and the frequency is adjusted by changing the capacitance in series or parallel with the crystal oscillator. Here, in the present invention, the vXO is of a voltage controlled type, for example, a voltage controlled variable capacitance diode is used as a capacitor in series or parallel with the crystal oscillator 61, and a control voltage is applied to this).
The frequency tolerance of 10 kHz or less is performed according to the data stored in 12, and the details will be explained later.

The m 21 F filter 7 is a main filter, and for example, for SSB, a filter with a bandwidth of 2 to 2.5 kHz and a Schieso factor of 2 or less is used. In the present invention, the switches S2 and 83 of the input/output section of the i-shift filter are used to defecate (directly connect) the main band filter 7 during frequency calibration. The switch Sz+Ss works in conjunction with other St IS4 185 to switch the circuit configuration between reception and calibration. The first side of the figure is the reception state, and the second side is the calibration state.

At the time of reception, the tuning pulse 171 output from the tuning function 17 is input to the CPU, and the stored data for the lower digit frequency interpolation is converted into the tuning pulse 1.
The output 121 changed by 1 step for each input of
/A converter 16, and its output voltage 161 is applied to a voltage variable capacitance diode 62 connected in series or parallel with the crystal oscillator of the second local oscillator 6, for example, L 00 Hz.
The frequency is increased or decreased over the entire range of 10 kHz in steps, and the upper digit frequency is set by the overflow output 122 of the lower digit.

The means for causing the CPU to store control data calibrated to maintain the minimum step frequency of the second local oscillator when the device is powered on and in response to the operation of the calibration switch is as disclosed in claim 2. , When the CPU is reset when the power is turned on or when the calibration switch 18 is operated, the CPU 12 outputs the calibration command 123 (via the relay 19 or electronic switch) (a) Disconnects the antenna circuit and outputs the marker. to the input section, to cause the main band filter 7kSzhS3 to defeat kp, to set the BFO frequency of the demodulator 9 to the normal calibration operating position 84, and if necessary, to output p audio to S5. (b) Adjust the frequency display on the receiving wall to the calibrated frequency (using the tuning function 17); (c) The output 91 of the demodulator 9 and the entire waveform shaping circuit 11 are all passed through to the CPU 12 and counted. , the CPU outputs the control voltage 161 for controlling the second local oscillation frequency so that the demodulator output frequency becomes half the difference between the frequency at the time of the BFO LSB and the frequency at the time of the USB. a program for setting calibration reference output data; (d) after storing the calibration reference output data in the CPU, the CPU stores data at each point where the demodulated output frequency increases by the minimum received frequency step over the lower digit frequency change range; (e) Upon completion of the above calibration, the calibration state of 81 to S5 is returned to the full receiving state (outputting the signal to 123); (f) In the receiving state, (tuning function 17) The receiver according to claim 1, wherein the lower digit frequency is reproduced (at 121) according to the stored data of the minimum frequency step in accordance with the frequency adjustment operation. It is a circuit.

The marker frequencies used here can be calibrated in any band of the receiver, and can normally be received at 100 kHz intervals to avoid the hassle of searching for marker positions. To do this, a reference frequency of 100 kHz is passed through a nonlinear circuit such as a diode, or a multivibrator oscillation is synchronized with 100 kHz to generate all harmonics of 100 kHz.

In the circuit shown in the figure, the reference frequency is the same as that of the PLL circuit, but in reality, it is possible to obtain the desired frequency by using all the appropriate frequency division outputs of the frequency divider 14.

In the above paragraphs (,), "main band filter 7 'c S
z.

The "operation to cause the sive feet to S3" is performed by the second mixer because the marker frequency and the first local oscillation frequency are kept constant when the frequency of the second local oscillator 6 is changed over the lower digit frequency change range during calibration. 1st I input to 5
The F frequency is constant, so the second IF frequency does not change by the amount that the second local oscillation frequency changes, and is outside the passband of the second IF filter 7 (the bandwidth of the filter 7 is for SSB). is 2 to 3 kHz, whereas the lower digit frequency change range is 10 kHz), this is the simplest means to widen the passband width.

In section (c) above, "the demodulator output frequency is half the difference between the BFO LSB frequency and the USB frequency" means that the BFO frequency at LSB is generally the center frequency of filter 7 + 1.5. kHz (however, in this case, this is not the case at the demodulator input, and it does not necessarily match the received wave). 9. Since the BFO frequency during USB is the center frequency - 1.5 kHz, the BFO frequency during LSB is The difference in BFO frequency during USB is 3 kHz, and when the output 91 of the demodulator 9 matches half of that, 1500 Hz, the marker signal is at the center of the filter 7, and the lower digit frequency is O (exactly). means that the frequency is 0O9OkHz), and this state is the reference operating point of the second local oscillator. Therefore, at this time, the "D/A conversion circuit 16 that outputs the control voltage 161 that fully controls the second local oscillation frequency"
"Calibration standard output data of the CPU" 121 is set to "store the calibration standard output data in the CPU" in section (d),
Then, the CPU stores data at each point where the demodulated output frequency increases by the minimum received frequency step over the lower digit frequency change range.This means that the demodulated frequency input to the CPU is based on 1500 Hz, and in this case, the following In the step, 1600 Hz is the second point, then 1
1, increasing in 00 Hz steps up to 11,400 Hz.
The C'PU performs lower digit frequency calibration using a program that stores the 00 point as step frequency data. The reason why the CPU stores the data of each point that increases with the minimum reception frequency step is that when converting the second IF frequency to a lower value than the first IF frequency, the local frequency is If the input frequency is set higher than the input frequency, the local frequency and the second IF frequency will increase or decrease proportionally, but if the local frequency is set lower than the second IF frequency, the second IF frequency will be the local frequency. It increases or decreases in inverse proportion to the oscillation frequency of vXO, and the same effect can be obtained even if the control voltage is the same, the frequency increases or decreases in the opposite way regardless of whether the variable capacitance diode is connected in series or parallel to the crystal oscillator. Since there are many combinations of detailed configurations to obtain this, the condition is that the configuration is such that the demodulated output frequency increases by the minimum reception frequency step.

The feature of this calibration method is that the analog demodulation frequency i CP
Since it is measured by a counter inside U, is the number of D/A stages large? By setting, even the units of p and Hz can be easily set, and the frequency nonlinearity of the vXO6 and the D/A converter 16 is automatically corrected and does not pose a problem.

When the calibration and storage of the frequency setting data 121 for the second local oscillator is completed, the CPU changes the calibration command 123 to a reception command and outputs it, and turns the switches 81 to S5 to the 1 side to enter the reception state.

The BFO is equipped with both LSB and USB, and is used by switching according to the mode of the received wave.In the figure, S4 has all the crystal oscillators switched, but the VXO type has a crystal oscillator circuit. A circuit that switches all of the capacitors, and two BF'O
The operation is the same even if the i switching method is used. USB is commonly used in commercial communications, but in amateur communications, the commonly used sideband differs depending on the band, so the crystal oscillator 101 and It is necessary to arrange 102.

The frequency calibration operation described above is automatically performed each time the power switch is turned on, and can also be performed at any time using the calibration switch 18 if necessary, so as long as the frequency of the reference oscillator 13 is maintained accurately, There is no need to worry about changes, and the reference oscillation frequency can be corrected very accurately by receiving standard radio waves such as JJY, so the receiver circuit of the present invention has the advantage of always maintaining a high degree of frequency accuracy.

[Brief explanation of drawings]

The figure is an example of a circuit configuration diagram for implementing the present invention. 1... Antenna, 2... 1st mixer, Dan... 1st
Local oscillator, 4... first IF filter, 5... second
Mixer, 6... Second local oscillator, 7... Second IF filter, 8...Amplifier, 9... Demodulator, 10...
BFo, 11... Waveform shaper, 12... CPU, 1
3... Reference frequency oscillator, 14... Branch unit, 15.
... Marker generator, 16 ... 1A converter, 17 ... Tuning function, 18 ... Calibration switch, 19 ... Relay,
31hS2rS3+'541sfi+・+Relay contact or electronic switch. Patent applicant Yaesu Musen Co., Ltd.

Claims (2)

[Claims] (1) Frequency marker generator, PLL-controlled first local oscillator, and microcomputer all controlled by a single reference oscillator, and all upper digits of the receiving frequency controlled by the microcomputer In a radio receiver of the type that includes a first local oscillator for the intermediate frequency interstage mixer, a second local oscillator for the intermediate frequency interstage mixer, and interpolation of the lower digits of the receiving frequency by finely adjusting the oscillation frequency deposit, Control data i calibrated to maintain the entire minimum step frequency of the second local oscillator according to the operation of the calibration switch.
1. A receiver circuit, which is stored in a CPU, and sets lower digits of a reception frequency based on the data upon reception. (2) The means for making the CPU store the control data calibrated to maintain the entire minimum step frequency of the second local oscillator when the device is powered on and in response to the operation of the calibration switch is to cancel the reset of the CPH when the power is turned on or By operating the calibration switch, the CPU outputs a calibration command and (a) disconnects the antenna circuit, injects the marker output into the input section, and defaults the main band filter (usually the second intermediate frequency). (b) Adjust the frequency display of the receiver to the calibration frequency, and set the demodulator's BFO frequency to the normal calibration operating position. (
e) The demodulator output is input to the CPH through the waveform shaping circuit and counted, and the demodulator output frequency is the LSB of BFO.
A program that sets the CPU's calibration reference output data to a D/A conversion circuit that outputs a control voltage that controls the second local oscillation frequency so that the frequency is half the difference between the frequency at the time of operation and the frequency at the time of USB. , (d) After storing the calibration reference output data in the CPU, the CPU stores a program for storing data at each point where the demodulated output frequency increases by the minimum received frequency step over the lower digit frequency change range;
(f) In the reception state, with the frequency adjustment operation, the lower digit frequency is reset by the stored data of the minimum frequency step. A receiver circuit according to claim 1, characterized in that the receiver circuit is reproducibly set.