JPS63217830A - Frequency synthesizer tuner - Google Patents

Abstract

PURPOSE:To suppress the deviation of an actual reception frequency with respect to the desired reception frequency by adding a correction voltage to a control voltage applied to a dual tuning circuit of a reception circuit, and setting the level of the correction voltage to a level optimizing the level of an intermediate frequency signal. CONSTITUTION:At first a maximum point of an intermediate frequency signal level, that is, a reception signal fd (point A) is obtained and frequencies (points B, C) having a level lower than the point A by a prescribed level (e.g., 3dB) are obtained, and a midpoint D (D=(B+C)/2) between the points B and C is calculated and the point D is used as an optimum correction data. Moreover, the frequency (f) of the X axis is expressed in f=1/2pi(LC<1/2>), and since the capacitance C is subject to change by the control voltage V, the frequency varies with the control voltage V. The tuning frequency of the reception circuit is controlled optimizingly by supplying the correction voltage obtained in such a way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a frequency synthesizer tuner (hereinafter referred to as a synthesizer tuner), and particularly to a tuner in which tracking error is corrected.

[Conventional technology]

An example of a conventional synthesizer tuner will be explained with reference to FIG. Figure 12 is a block circuit diagram of a synthesizer tuner, and the radio waves arriving at antenna 1 are high frequency (
The signal becomes an RF (hereinafter referred to as RF) signal and is supplied to the antenna tuning circuit 2 which attempts to pass only the RF multiplied signal of the target frequency. The antenna tuning circuit 2 is configured by, for example, an LC tuning circuit including a variable capacitance element, and receives a local frequency control voltage (hereinafter referred to as control voltage) supplied from the PLL circuit 3.
The value of the variable capacitance element of the LC tuning circuit is changed in accordance with the signal to increase the gain of the circuit for the frequency to be received. The output signal of the antenna tuning circuit 2 is supplied to the RF amplifier circuit 4. The RF amplifier circuit 4 is a tuned amplifier circuit, and is constituted by, for example, a high frequency amplifier circuit including an LC tuned circuit 4a (not shown) consisting of a variable capacitance element and a coil whose capacitance changes according to the control voltage. The output signal of the RF amplifier circuit 4 is supplied to a frequency mixing circuit (hereinafter referred to as a mixing circuit) 5. The mixing circuit 5 mixes the output signal and the local oscillator signal supplied from the VCO (voltage controlled oscillator) 6 to obtain an intermediate frequency (hereinafter referred to as IF) signal, which is then supplied to the IF amplifier circuit 7. . The IF amplifier circuit 7 is a tuned amplifier circuit having a tuning circuit that passes only a signal of a specified IF frequency, increases the IF times signal level, and supplies the increased signal level to a detection circuit (not shown). The detection circuit demodulates the received signal to obtain, for example, an audio signal.

The control circuit 8 changes the control voltage output from the PLL circuit 3 to a level corresponding to the frequency to be received in response to a reception channel command signal supplied from the keyboard 9.

The PLL circuit 3 is composed of a crystal oscillator, a pre-frequency divider, a programmable frequency divider, a phase comparator, a low-pass filter, etc., and together with the VCO 6 forms a well-known frequency synthesizer.

In this configuration, when the operator instructs the control circuit 8 to receive a broadcast signal or the like of a predetermined frequency via the keyboard 9, the control circuit 8 sets a frequency division number corresponding to the frequency in the programmable frequency divider.

Then, the control voltage signal output from the low-pass filter is supplied to the VCO 6, and the local oscillation frequency is set to a frequency corresponding to the frequency to be received.

Further, the control voltage signal is applied to the antenna tuning circuit 2 and the RF
The tuning frequency of each tuning circuit is set to the frequency supplied to each tuning circuit of the amplifier circuit 4 to be received, and the desired broadcast radio waves are received.

By the way, the tuning characteristics of the antenna tuning circuit 2 and the RF tuning amplifier circuit 4 are not necessarily the same, and a constant relationship between the oscillation frequency of the VCO 6 and the tuning frequency of each tuning circuit with respect to the control voltage is maintained over the entire reception band. This is difficult due to the characteristics of the circuit. As a result, a problem occurs in which the actual reception frequency deviates from the frequency to be received, which is a so-called tracking error.

In order to improve this problem, the applicant of the present application proposed a synthesizer tuner equipped with a tracking error correction means in Japanese Patent Application No. 61-253311. The contents will be explained below.

In the block circuit of the tuner shown in FIG.
Components corresponding to the block circuit shown in FIG. 2 are denoted by the same reference numerals, and a description thereof will be omitted.

IF multiplied signal narrowband filter 2 output from mixing circuit 5
1 or a broadband filter 22 and then supplied to the F amplifier circuit 7. The changeover switch 23 selects one of the two filters. For example, in normal reception, the wideband filter 22 is selected, and the narrowband filter 21 is selected when adjusting the tuning characteristics of a tuning circuit, which will be described later. The switching operation of the changeover switch 23 is controlled by the contents of the changeover register 45. The signal meter output signal is supplied from the IF amplifier circuit 7 to the A/D converter 46.

The control voltage of the PLL circuit 3 is supplied to the antenna tuning circuit 2 and the RF tuning circuit 4a via adder circuits 24 and 25, respectively. A correction voltage, which will be described later, is supplied to the other input terminal of each adder circuit.

A reception channel command signal indicating the channel to be received from the operator via the keyboard 9 is sent to the microprocessor 3.
1. In addition to controlling the conventional circuit, the microprocessor 31 performs a correction operation for tuning circuit characteristics, which will be described later. The memory 32 stores the output (IF signal level) of the A/D converter 46 in response to a storage command signal from the microprocessor 31. ROM33 is microprocessor 3
1, and outputs stored information to the microprocessor 31 in response to a read address command (not shown) from the microprocessor 31.Antenna tuning frequency Correction register (hereinafter referred to as antenna correction register) 3
4 and an RF tuning frequency correction register (hereinafter referred to as RF correction register) 35 are set with correction values supplied from the microprocessor 31. registers 34 and 35
are stored in D/A converters 41 and 42, respectively.
is converted into an analog voltage signal and supplied to the other input end of each adder circuit 24 and 25 as the above-mentioned correction voltage. Note that the value of the correction voltage is a positive or negative value with respect to the control voltage of the PLL circuit 3. The control voltage is controlled by changing the frequency division number of a programmable frequency divider (not shown) of the PLL circuit 3. The microprocessor 31 stores frequency division number data corresponding to the channel to be received in the ROM.
33 by reading or calculation and setting it in the frequency setting register 44. By setting the contents of this register 44 to the programmable frequency divider of the PLL circuit 3, the level of the control voltage signal is set, and the VCO 6
The oscillation frequency of is set. The microprocessor 31 supplies a signal indicating selection of the narrowband filter 21 or the wideband filter 22 to the switching register 45 depending on the adjustment operation of the tuning circuit or the radio wave condition. The tuning control signals supplied to the antenna tuning circuit 2 and the RF tuning circuit 4a are, so to speak, a coarse adjustment signal (control voltage) and a fine adjustment signal (correction voltage).
As a result, appropriate adjustment can be made according to the characteristics of each tuned circuit. Circuits 31-35 and 44 form a control circuit. The other configurations are similar to the conventional circuit.

Next, the reception operation will be explained with reference to the control flowchart shown in FIG. In such a tuning method, the frequency division number corresponding to the channel to be received is set in the frequency register, and then only the tuning frequency of the tuning circuit is changed so that the reception level or detection output is maximized. The configuration is such that the tuning control voltage for the

First, when the microprocessor 31 is executing the main control program or is on standby, when the operator supplies the reception channel data X indicating the channel to be received to the microprocessor 31 via the keyboard 9, the microprocessor 31 This is stored once and the process moves to this subroutine.

Then, the above channel data X is fetched (step S
l). Frequency division number 1) r corresponding to this channel data
V(x) is read from the ROM 33 or obtained by calculation and set in the frequency setting register 44 (step S2). The value set in the register 44 is set in the programmable frequency divider of the PLL circuit 3, and the control voltage of the PLL circuit 3 is set to a value corresponding to the channel to be received.

Then, according to this value, the local frequency of the VCO 6 and the tuning frequencies of the antenna tuning circuit 2 and RF tuning circuit 4a are adjusted, and a reception channel is set.

Next, microprocessor 31 clears variable N. When the variable N is smaller than Nmax corresponding to the number of data supplied to the antenna correction register 34 (step S4
) generates antenna correction data ANT (N).

The antenna correction data is the product of the variable N and the constant a that determines the range of change, and the initial value a. It is formed by the sum of The value of this correction data takes a positive or negative value. The antenna correction data is supplied to the register 34 (step S5). ANT
By changing the contents of the correction register 34, the correction voltage supplied to the antenna tuning circuit 2 changes, and its tuning frequency changes. The microprocessor 31 reads the level of the intermediate frequency signal (via the A/D converter 46) corresponding to the antenna correction data ANT (N),
This is stored in the register IF(N) (step S
6). Now, since the value of N is 0, register IF (0) is selected corresponding to antenna correction data ANT (0). After completing step S6, 1 is added to the value of variable N to increase the variable N, and step S4 described above is executed (step S7). Steps 84 to S7 are repeated to store reception level data corresponding to each piece of antenna correction data in registers IP (0) to IF (Nmax). variable N
When the value exceeds Nmax (step S4), the process moves to a subroutine for extracting data indicating the maximum reception level from registers IF(0) to IF(Nmax) (step S8).

An example of a subroutine for extracting the data of the maximum reception level will be explained with reference to the flowchart of FIG.

First, clear the variable K, and set the maximum value Kmax of the variable to N
max is set (step 531). Register IF
(step 532)
, increases the value of the variable by 1 (step 534). In step S32, the value of register IF(K) is set to register I.
If it is larger than F(K+1), register (K+1>
Store the value of register IP(K) in (step 535
). After that, step S33 is executed.

By repeating steps 332 to S35, a larger value is stored in register IF (K+1), and finally the maximum value is stored in register IF (K+nax). When the value of the variable reaches Kmax, step S3
5 (step 534).

In steps 335 to S39, the number of the register storing the maximum value is determined.

First, set the value of the variable to "0" (step 535).
, the value of register IF (0) is register IP (Kmax
) (step 536).

If they are not equal, the value of the variable is increased by "1" (step 537). If the value of the variable is not equal to Kmax, the process moves to step S36 (step 538).

In step S36, when the value of the register IF(K) is equal to the maximum value, the value of the variable at this time is set to the variable N (step 539). Further, when the value of the variable is equal to Kmax in step S38, step S39 is executed. In this way, the value of the variable N when the maximum value is obtained is obtained, the subroutine is ended, and the process returns to step S8.

The value of this variable N is fetched (step S9), and step S
Similarly to step 5, calculate the correction data ANT (N) or read the correction data from the register corresponding to the value of the variable N to obtain the final correction data, output this to the antenna correction register, and end the antenna correction value setting subroutine. (Step S10).

After completing the above subroutine, the RF correction value subroutine shown in the flowchart of FIG. 8 is executed. Steps 321 to S28 of this subroutine correspond to steps 83 to SIO of the antenna correction value setting subroutine, and constants and initial values are set in step S23. is set, and the control operation is the same except that it is output to the RF correction register 35 in step S28, so a description thereof will be omitted.

In short, the above process is to sequentially vary the tuning frequency of the tuning line as f1 → f0 → f2 with the characteristics shown in Figure 10, and then change the tuning frequency to the frequency (fo in the figure) at which the level of the received signal f at that time is maximum. It's about getting in sync.

In this way, the tuning frequency of each tuning circuit with adjusted correction voltage is set appropriately, so tracking errors are suppressed, and variations in the characteristics of the variable capacitance diodes or coils that make up the tuning circuit are suppressed. is not a problem, and there is an advantage that the tuning circuit can be made unadjusted.

[Problem that the invention seeks to solve]

In such a conventional device, when the tuning line is single-tuned, its frequency characteristics are as shown in Fig. 10. Therefore, the frequency at which the received frequency level is maximum can be used as correction data. .

However, if the tuning line is a double-tuned circuit, its characteristics will be as shown in FIG. 11, where the tuning frequency is f. and the receiving frequency fd of the signal do not match. Therefore, when the correction data corresponding to the maximum value of the intermediate frequency signal is used in the above processing, the difference between the receiving frequency fd and the tuning frequency fo will increase.

[Means for solving problems and their effects] Therefore,
SUMMARY OF THE INVENTION An object of the present invention is to provide a synthesizer tuner in which each tuning means of a receiving circuit can be appropriately adjusted for a selected receiving channel even in a double-tuned circuit.

In order to achieve the above object, in the synthesizer tuner of the present invention, in addition to the control voltage from the PLL circuit, each tuning means of the receiving circuit is supplied with a voltage that is a predetermined level lower than a correction voltage that maximizes the level of the intermediate frequency signal. is obtained, arithmetic processing is performed based on correction data corresponding to the voltage, and the tuning frequency of the receiving circuit is optimally controlled by supplying the correction voltage obtained as a result.

[Embodiments of the invention]

Examples of the present invention will be described below. The configuration example of the synthesizer tuner according to the present invention is the same as that shown in FIG.
The processing of the microprocessor 31 is different. The processing will be explained below. In the first embodiment of the present invention, in the characteristics shown in FIG. 2, first, the maximum point of the intermediate frequency signal level, that is, the received signal fd (point A) is determined. Next, a frequency B at a level lowered by a predetermined level (for example, 3 dB) from this point A.
Find the points and 0 points. Then, the midpoint point between point B and point 0 (
D-(B+C)/2) is calculated, and this point D is used as the optimum correction data. In FIG. 2, the frequency f on the horizontal axis is set to f=1/2π, 0 and −, and this capacitance C changes depending on the control voltage V. Therefore, the control voltage V
The frequency changes accordingly.

In the main control loop of FIG. 3, the difference from FIG. 7 is that step S8 is now a process S8' for executing a subroutine for extracting optimal data from IF (0) to IF (Nmax). The other processing is the same as that in FIG.

In the optimum value extraction subroutine shown in FIG. 5, processes similar to those in the subroutine of FIG. 9 are denoted by the same reference numerals. First, the register I F (Kmax
) is the same as that shown in FIG. 9. After step S34, this maximum value I F
Data at a level lower than (Kmax) by a predetermined value A (for example, 3 dB) is set in the register IF (Ka) (step 540). Next, set the value of the variable to "0", and
Set variable a to "0" in step S35'), register I
It is determined whether the value of F (0) is equal to the value of register IF(Ka) (step 536).

If they are not equal, the value of the variable is increased by "l" (step 537). If the value of the variable is not equal to Kmax, the process moves to step 336 (step 538).

In step 336, the value of register IP(K) is
When it is equal to F(Ka), step S41 determines that a is “
0". If a=Q, then B in Figure 2
Corresponding to the point, store K at this time in register M1 (
Step 542). Then, in step S43, a is set to "1" and the process goes to step S37. Also, step S4
1, when a is not "0", that is, when a is "1", it corresponds to point C in Figure 2, and K at this time is stored in register M.
2 (step 544). Also step 33g
If K matches Kmax in step S4
Perform step 4.

2 corresponding to IF (Ka) in the processing up to step S44.
Since two variables K are stored in registers M+ and M2,
In step S45, the midpoint (M,
10M2)/2 is set as the variable N, the subroutine is ended, and the process returns to step S8.

The value of this variable N is fetched (step S9), and step S
Similarly to step 5, calculate the correction data ANT (N) or read the correction data from the register corresponding to the value of the variable N to obtain the final correction data, output this to the antenna correction register, and end the antenna correction value setting subroutine. (step 510).

After completing the above subroutine, the RF correction value subroutine shown in the flowchart of FIG. 4 is executed. Steps 321 to S28 of this subroutine correspond to steps 83 to S10 of the antenna correction value setting subroutine of FIG. 3, and constants and initial values are set in step S23. is set, and in step 328 the RF correction register 3
Since the control operation is the same except that the output is output to 5, the explanation will be omitted.

FIG. 6 shows a characteristic diagram for explaining the second embodiment of the present invention. In the figure, first, the maximum value A of the intermediate frequency level is determined, and then a point C, which is 3 dB lower at a frequency higher than point A, is determined with respect to that level.

Next, the level in the direction of point A (lower frequency direction) from this 0 point is detected, and the first peak point, point E, is determined.

Then, point F (F-(A+E)/2) is the midpoint between point A and point E.
) is the optimal data.

〔Effect of the invention〕

As explained above, in the present invention, a correction voltage is added to the control voltage supplied to the double-tuned circuit of the receiving circuit, and the level of this correction voltage is set to a level that optimizes the level of the intermediate frequency signal. Therefore, the tuning frequency of the tuning circuit is appropriately set with a certain frequency correlation to the local oscillator frequency that is accurately set according to the frequency to be received by the PLL circuit, and the actual frequency for the desired reception frequency is set appropriately. This is preferable because it suppresses the shift in reception frequency.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an embodiment of the present invention and the configuration previously proposed by the applicant; FIG. 2 is a diagram showing frequency characteristics for explaining the first embodiment of the present invention; 3 to 5 are flowcharts for explaining the reception operation of the first embodiment, FIG. 6 is a diagram showing frequency characteristics for explaining the second embodiment of the present invention, and FIGS. 7 to 5 are flowcharts for explaining the reception operation of the first embodiment. FIG. 9 is a flowchart for explaining the reception operation previously proposed by the applicant, FIG. 10 is a diagram showing frequency characteristics in the single-tuned circuit applied to the reception operations of FIGS. 7 to 9, and FIG. 11 12 is a diagram showing frequency characteristics in a double-tuned circuit, and FIG. 12 is a flowchart showing a conventional example. 3...PLL circuit 24.25.26...Addition circuit 31...Microprocessor 41, 42. 43...D/A converter 46...A
/D converter

Claims (1)

[Claims] control voltage generation means for generating a control voltage corresponding to set frequency data; reception high frequency signal processing means including a tuning circuit whose tuning characteristics change according to the control voltage; and a local oscillation device with a frequency corresponding to the control voltage. voltage-controlled oscillation means for generating a signal, frequency conversion means for mixing the output signal of the received high-frequency signal processing means and the local oscillation signal to obtain an intermediate frequency signal, and correction data for the control voltage to the tuning circuit. and a control means that generates the set frequency data and the correction data, and the control means calculates the set frequency data according to the designated reception channel. , the correction data is sequentially changed from the initial value to the final value, the level of the previous intermediate frequency signal is sampled and stored sequentially in synchronization with the change in the correction data, and a predetermined value is determined from the maximum value among the sampled values of the intermediate frequency. A frequency synthesizer tuner characterized in that the correction data corresponding to the optimum intermediate frequency signal level is set as the final correction data by performing a desired calculation based on the correction data corresponding to a low level.