JPS60176298A - Method of producing multilayer printed circuit board - Google Patents

Method of producing multilayer printed circuit board

Info

Publication number
JPS60176298A
JPS60176298A JP3171384A JP3171384A JPS60176298A JP S60176298 A JPS60176298 A JP S60176298A JP 3171384 A JP3171384 A JP 3171384A JP 3171384 A JP3171384 A JP 3171384A JP S60176298 A JPS60176298 A JP S60176298A
Authority
JP
Japan
Prior art keywords
layer
forming
inner layer
multilayer printed
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3171384A
Other languages
Japanese (ja)
Inventor
大貫 秀文
浅野 智明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3171384A priority Critical patent/JPS60176298A/en
Publication of JPS60176298A publication Critical patent/JPS60176298A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (技術分野) 本発明は、多層印刷配線板の製造方法に係わり、特に多
層印刷配線板の内層の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a multilayer printed wiring board, and particularly to a method for manufacturing an inner layer of a multilayer printed wiring board.

近年、印刷配線板に搭載する、IC,LSI等の電子部
品の高速度化、高密度化に伴ない、これらの電子部品の
消費する電力の供給が問題となってきている。このため
、多層印刷配線板の内層導体層に用いる銅箔の厚さを次
第に厚くシ、電力供給を良好に行なう傾向となってさて
いる。すなわち、一般には、内層導体層としての電源層
および地気層に厚さ35〜70μmの銅箔を使用してい
たが、厚さ150〜300μmまたは、それ以上の岸さ
の銅箔を使用することにより、電力供給を改善しようと
している。
In recent years, as electronic components such as ICs and LSIs mounted on printed wiring boards have become faster and more dense, the supply of power consumed by these electronic components has become a problem. For this reason, there is a trend to gradually increase the thickness of copper foil used for the inner conductor layer of multilayer printed wiring boards to improve power supply. That is, in general, copper foil with a thickness of 35 to 70 μm was used for the power supply layer and the ground air layer as inner conductor layers, but copper foil with a thickness of 150 to 300 μm or more is used. By doing so, we are trying to improve the power supply.

(従来技術) 第1図(A)〜−に従来工法による厚い内層導体層を使
用した多層印刷配線板の製造工程を示す。
(Prior Art) Figures 1A to 1-- show the manufacturing process of a multilayer printed wiring board using a thick inner conductor layer by a conventional method.

第1図(A)は、絶縁基材1に厚い金楓箔2a、2bを
接着した両面金稿箔張り絶縁板の断面図である。
FIG. 1(A) is a sectional view of a double-sided gold maple-covered insulating board in which thick gold maple foils 2a and 2b are adhered to an insulating base material 1.

ここで金楓箔2a、2bには、例えは厚さ150μm以
上の銅箔音用いる。
Here, the gold maple foils 2a and 2b are, for example, copper foils with a thickness of 150 μm or more.

次に金稿箔2a、2b上に感光性樹脂層3a、3b(例
えはデーポン社製リストン■ドライフィルム”1220
 )’t−被着形成させ、フォトマスク4a。
Next, photosensitive resin layers 3a, 3b are applied on the gold foils 2a, 2b (for example, Riston Dry Film "1220" manufactured by Dapon Co., Ltd.).
)'t-deposition and photomask 4a.

4bを介してB元させ(第1図(B) ) 、禾絽元部
分をクロロセン等の溶剤を用いて俗解・除去させ、エツ
チングレジスト被膜5a、5b金形成きせる(第1図(
CJ )。
4b (Fig. 1 (B)), and the etching resist film 5a, 5b is formed by removing the etching resist film 5a and 5b using a solvent such as chlorocene (Fig. 1 (B)).
CJ).

次lC会楓箔2 a、 2bのエツチングレジスト被膜
5a、5bに被われていない部分を塩化第2餉液寺を用
いてエツチング除去しくm1図(11)、さらにエツチ
ングレジスト被& 5 a 、 5 b ′に塩化メチ
レン等の溶剤を用いて溶解e除去させ、内層板6の回路
形成を終了させる(第1図(均)。
Next, the portions of the maple foils 2a and 2b that are not covered with the etching resist coatings 5a and 5b are removed by etching using a second chloride solution. b' is dissolved and removed using a solvent such as methylene chloride to complete circuit formation on the inner layer plate 6 (FIG. 1 (uniform)).

次に内層&6と外層導体層8a、8beグリプレグ7a
、7bおよび7c、7d?!−介して配置しくm1図0
り)、ホットプレスで熱圧着させて多層化基板9を形成
させる(第1図(G) )。
Next, inner layer &6 and outer conductor layer 8a, 8be Gripreg 7a
, 7b and 7c, 7d? ! -It should be placed through m1 figure 0
1), and then thermocompression bonded using a hot press to form a multilayer substrate 9 (FIG. 1(G)).

次に多層化基板9にスルホールIOをあけ(第1図(ハ
))、 外層導体層8a、8b問および内層導体層11a 。
Next, through holes IO are made in the multilayer substrate 9 (FIG. 1 (c)), and the outer conductor layers 8a and 8b and the inner conductor layer 11a are formed.

tibの間を電気的に接続するスルホールめりき11−
施しく第1図(i)八 さらに、外ノー導体層ga、8b上に形成したスルホー
ルめっき120表面に感光性樹脂* 3 c 、 3 
dt−被層形成させ、フォトマスク4.c、4dk介し
て14r元しく第1図(J))、未絡元部分tクロロセ
ン等の溶剤を用いて溶解嗜除去させ、エツチングレジス
ト被膜5c、5dを形成させる(第1図(6))。
Through-hole cutout 11- for electrically connecting between tib
Furthermore, as shown in FIG. 1(i), a photosensitive resin*3c, 3 is applied to the surface of the through-hole plating 120 formed on the outer non-conductor layer ga, 8b.
dt-layer formation and photomask4. The unentangled portions are dissolved and removed using a solvent such as chlorocene to form etching resist films 5c and 5d (Fig. 1 (6)). .

次に、スルホールめり@12上に形成したエツチングレ
ジスト被% 5 c 、 5 dに被われていない部分
を塩化第2銅故等でエツチング除去しく第1図(旬)、
さらにエツチングレジスト被% 5 c 、 5 dを
塩化メチレン等の溶剤で俗解O除去させ、多層印刷配線
&l 3t−得る(第11舖)。
Next, the portions not covered by the etching resist coatings 5c and 5d formed on the through-hole holes 12 were removed by etching with cupric chloride, etc., as shown in FIG.
Further, the etching resist layers 5c and 5d are removed with a solvent such as methylene chloride to obtain a multilayer printed wiring (No. 11).

しかし上述の従来工法では、厚い金桐箔を内層導体層に
使用した場合以下の3つの大きな欠点を有していた。す
なわち、 (イ)エツチングによるアンダーカプトが大きくなり、
回路形成精度が悪化し、エツチング残りやオーバーエッ
チを発生しやすく、絶縁劣化おるいは電源供給不良を発
生する。第1表は従来工法による回路形成精度の一例を
示したものである。
However, the above-mentioned conventional method had the following three major drawbacks when thick gold paulownia foil was used for the inner conductor layer. In other words, (a) the undercap caused by etching becomes larger;
Circuit formation accuracy deteriorates, etching residue and over-etching are likely to occur, resulting in insulation deterioration or power supply failure. Table 1 shows an example of the accuracy of circuit formation using the conventional method.

第1表 (ロ)内層板の絶縁基材と内層回路パターンとの間の設
差が太きいため、積層時に段差の部分が樹脂で埋まらず
、積層ボイドを発生する。
Table 1 (b) Since the gap between the insulating base material of the inner layer board and the inner layer circuit pattern is large, the stepped portion is not filled with resin during lamination, resulting in lamination voids.

←9 (ロ)と同じく段差が大きいため、外層導体層の
平坦性が悪化し、エツチングレジスト被膜の被着不良や
無光ボケを発生する。
←9 As in (b), the large step difference deteriorates the flatness of the outer conductor layer, causing poor adhesion of the etching resist film and non-light blurring.

(発明の目的) 本発明の目的はこのような従来欠点を解消した多層印刷
配線板の製造方法を提供することにある。
(Objective of the Invention) An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board that eliminates such conventional drawbacks.

(発明の構成) 本発明によれば、良好な電力供給が可能で、回路形成精
度が高く、積層ボイドの発生もなく、外海導体層の平坦
性も良好でパターンを高精度で形成できる多層印刷配線
板の製造方法、すなわち導体層の所望の位置にエツチン
グを施す工程と、上記エツチングを施した導体層のエツ
チングを施した側の表面に絶線8M脂を頭布し絶縁l−
を形成させる工程と、上記絶線層を形成させた導体層2
枚を1リグレグを介して熱圧着させ内116 & k形
成させる工程と、 上記内層板の表向の所望の位置にエツチングレジストす
工程と、上記エツチングを施した内層板の表面に絶に輌
+iiを頭布し絶線層を形成させる工程と、上記絶縁層
を形成させた内層&t1枚以上内層に配置し、プリプレ
グを介して外層導体1−を熱圧着させ、多層化藏敬ヲ形
成させる工程と、上記多I−化基板にスルホールを形成
させる工程と、上記スルホールを形成させた多1m化基
板にスルホールめっきを施す工程と、 上記スルホールめっ@を施した多層化基板の外層の所望
の位置をエツチング除去し、外層回路を形成させる工程
とからなることt特徴とする多層印刷配線板の製造方法
が得られる。
(Structure of the Invention) According to the present invention, multilayer printing allows for good power supply, high circuit formation accuracy, no lamination voids, good flatness of the outer conductor layer, and high precision pattern formation. The manufacturing method of a wiring board includes the step of etching a conductor layer at a desired position, and applying insulation 8M resin to the etched surface of the etched conductor layer.
and a conductor layer 2 on which the disconnected layer is formed.
A step of thermo-compression bonding the inner layer plate through one leg to form an inner layer 116&k, a step of applying an etching resist to a desired position on the surface of the inner layer plate, and a step of applying an etching resist to the etched surface of the inner layer plate. A process of forming a disconnected layer by placing the above-mentioned insulating layer on the inner layer, and a process of forming a multilayer structure by placing one or more sheets of the insulating layer on the inner layer, and bonding the outer layer conductor 1- by thermocompression via a prepreg. a step of forming through holes on the multi-I substrate, a step of applying through hole plating to the multi-layer substrate on which the through holes are formed, and a step of forming a desired outer layer of the multi-layer substrate with the through hole plating A method for manufacturing a multilayer printed wiring board is obtained, which is characterized by comprising the steps of etching away the positions and forming an outer layer circuit.

(実施例〉 以下、本発明の実施例を第2図(N〜())、第3図(
5)〜(F) 、第2図((J−(U)を用いて説明す
る。
(Example) Hereinafter, examples of the present invention will be described in Fig. 2 (N~()) and Fig. 3 (
5) to (F), will be explained using FIG. 2 ((J-(U)).

第2図(At 、第3図(A)は金属箔2a、2bの一
■曲図である。
FIG. 2 (At) and FIG. 3 (A) are one-part diagrams of the metal foils 2a and 2b.

金s4箔2a、2bには例えは犀さ150μm以上の銅
箔を用いる。
For example, copper foil with a thickness of 150 μm or more is used as the gold S4 foils 2a and 2b.

次に虻楓箔2a、2b上に感光性樹脂層3a、3b。Next, photosensitive resin layers 3a and 3b are placed on the maple foils 2a and 2b.

3c、3d(例えはデーポン社製リストン■ドライフィ
ルム$1220 )k被着形成させ、フォトマスク4a
、4bおよび4c、4de介して路光させ(第2図(B
)、第3図(縛)、禾り元部分をクロロセン等の溶剤を
用いて溶解・除去させ、エツチングレジスト被膜5a、
5bおよび5c、5di形成させる(第2図(C)、8
3図(C))。この時フォトマスク4a、4dは全面が
光透過性のものt用い、感光性樹脂+*3a、adの全
面かに′#、されるようにし、エツチングレジスト被i
5a、5dt−金属箔2a。
3c, 3d (for example, Riston dry film manufactured by Dapon Co., Ltd. $1220) k is deposited, and photomask 4a is formed.
, 4b, 4c, and 4de (Fig. 2 (B)
), FIG. 3 (binding), the etching resist film 5a is formed by dissolving and removing the exposed portion using a solvent such as chlorocene,
5b, 5c, and 5di are formed (Fig. 2(C), 8
Figure 3 (C)). At this time, the photomasks 4a and 4d are made so that the entire surface thereof is light-transmissive, and the entire surface of the photosensitive resin is coated with the etching resist.
5a, 5dt-metal foil 2a.

2bの片面の全面に形成させる。It is formed on the entire surface of one side of 2b.

次に金8箔2a、2bの片側からエツチングレジスト被
膜5a、5bおよび5c、、5dに被われていない部分
を塩化第2銅等を用いて、少なくともエツチングの深さ
が金属箔2a、2bの厚さの1/2以上になるようにエ
ツチング′fctM丁(第2図(U 。
Next, from one side of the gold 8 foils 2a, 2b, the portions not covered by the etching resist coatings 5a, 5b, 5c, 5d are etched using cupric chloride or the like, so that the etching depth is at least that of the metal foils 2a, 2b. Etch the thickness to more than 1/2 of the thickness (Fig. 2 (U).

第3図(ロ)。Figure 3 (b).

次にエツチングレジスト被%sa、sb′J?よび5c
、5di塩化メチレン等の溶剤を用いて除去する(第2
図(勾、第3図(匂)。
Next, apply etching resist %sa, sb'J? and 5c
, using a solvent such as 5di methylene chloride (second
Figure (Kado, Figure 3 (Oi).

次に釡@泊’l a、 2bのエツチングを施した側の
面に、スクリーン印刷・ロールコート等によって絶縁樹
脂層14a、14bを形成させ、片面樹脂コート金属箔
15a、15b ’e影形成せる(第2図ψ゛)。
Next, insulating resin layers 14a, 14b are formed on the etched side of the pot @ Tomari'l a, 2b by screen printing, roll coating, etc., and one side resin coated metal foil 15a, 15b'e shadow is formed. (Figure 2 ψ゛).

第3図(F))。Figure 3 (F)).

次に片面樹脂コート金属箔15a 、15bをプリプレ
グ7を介して、絶縁樹脂層t4a 、14bが1リグレ
グ7の側をむくように配置しく第2図(Gl )、熱圧
着させて、内層板16i得る(第2図u10次に内層&
16の表面上に感光性樹脂層3e。
Next, the single-sided resin-coated metal foils 15a and 15b are placed through the prepreg 7 so that the insulating resin layers t4a and 14b face the side of the first leg 7 (FIG. 2). Obtain (Figure 2 u10 then inner layer &
photosensitive resin layer 3e on the surface of 16;

3f(例えはチーポン社製リストン■ドライフィルム”
1220 )t”M着形成させ、フォトマスク4e、4
f を介して路光させ(第2図(I) ) 、未熟光部
分をクロロセン等の溶剤を用いて溶解・除去させ、エツ
チングレジスト被膜5e、5fi形成させる(第2図(
J))。
3F (for example, Riston Dry Film manufactured by Chipon Co., Ltd.)
1220) t”M deposition is formed, and photomasks 4e, 4
f (Fig. 2 (I)), and the immature optical part is dissolved and removed using a solvent such as chlorocene to form etching resist films 5e and 5fi (Fig. 2 (I)).
J)).

次に塩化第2鉋液等のエツチング液により内層板16の
エツチングレジスト被膜5e、5fに破われていない部
分をエツチングし、貫通5i7a。
Next, the portions of the inner layer plate 16 that are not torn in the etching resist coatings 5e and 5f are etched using an etching solution such as a dichlorochloride solution to form a through hole 5i7a.

17b、17cを形成させる(第2図(5))。17b and 17c are formed (FIG. 2 (5)).

次に貝通都17a 、17ci形成させた内層板16の
表面にスクリーン印刷・ロールコート等に↓りて絶縁樹
脂層14a、14bfc形成させ、絶縁樹脂コート内1
−叡ill形成させる(第2図に))。
Next, the insulating resin layers 14a, 14bfc are formed on the surface of the inner layer plate 16 on which the shells 17a and 17ci have been formed by screen printing, roll coating, etc., and the inside of the insulating resin coat 1
- formation of an illumination (see Figure 2)).

次に絶縁樹脂コード内層板18および外j−専体l鋳8
a、8bkグリグレグ7.7を介して配置しく第2図(
N+ ) 、熱圧着させて多層化基板1’l形成させる
(第2図<(J) )。
Next, the insulating resin cord inner layer plate 18 and the outer j-exclusive l casting 8
a, 8bk Grig Reg 7.7.
N+) and thermocompression bonding to form a multilayer substrate 1'l (FIG. 2<(J)).

次に多層化基&19にスルホールl(lあけ(第2図(
P))、スルホールlOに外層導体1m 8 a 。
Next, open a through hole (l) in the multilayer group &19 (Fig. 2 (
P)), 1 m 8 a of outer layer conductor in throughhole lO.

8bと絶縁樹脂コード内層板18の導体部分の端面を電
気的に接続するスルホールめっき12t”mしく第2図
(Q )、 さらに外層導体層8a、9b上に施されたスルホールめ
っさ12上に感光性樹脂層3g、3h1kwL眉形成さ
せた後、フォトマスク4g、4he介して無光させ(第
2図(麹)、未無光部分全クロロセン等の溶剤で俗解・
除去させエツチングレジスト被膜5g、5h?<形成さ
せる(第2図(S))。
8b and the end face of the conductor portion of the insulating resin cord inner layer plate 18 are electrically connected through-hole plating 12t''m (FIG. 2(Q)), and further on the through-hole plating 12 applied on the outer conductor layers 8a and 9b. After forming a photosensitive resin layer of 3g and 3h1kwL on the film, it was made to be unlighted through a photomask of 4g and 4he (Fig. 2 (koji)), and the unlighted part was completely washed with a solvent such as chlorocene.
Etching resist film removed 5g, 5 hours? <Formation (Fig. 2 (S)).

次にスルホールめっき12上のエツチングレジスト被膜
5g、5hに被われていない部分を塩化第2銅液等でエ
ツチング除去しく第2凶t’t))。
Next, the portions of the through-hole plating 12 that are not covered by the etching resist films 5g and 5h are removed by etching using a cupric chloride solution or the like.

さらに工、ソテングレジストil1%5g、5h’i塩
化メチレン等の溶剤で俗解・除去させ、多層印刷配線&
23を完成させる(第2図(IJ) )。
Furthermore, it was removed using a solvent such as Sotengresist IL1% 5g and 5h'i methylene chloride, and multilayer printed wiring and
23 (Figure 2 (IJ)).

(効果) 以上、本発明の工法では、厚い金楓箔を片側から2回に
分けてエツチングするため、アンダーカットが小さくな
り、回路形成精度が向上する。第2表は、本発明の工法
による内層形成精度の一例である。
(Effects) As described above, in the method of the present invention, since the thick gold maple foil is etched in two steps from one side, undercuts are reduced and circuit formation accuracy is improved. Table 2 shows an example of the accuracy of forming the inner layer according to the method of the present invention.

第2表 また厚い金楓箔のエツチング部分を次通したスルホール
の外側の部分が絶縁樹脂で元てんされているので検器の
発生が小さく、積層ホイドの発生もなく、また外層導体
層の平坦性が態化することもないので、高り度で外層回
路を形成することが可能となった。
Table 2 Also, since the outer part of the through-hole that passes through the etched part of the thick gold maple foil is filled with insulating resin, the occurrence of detection is small, there is no lamination hoid, and the outer conductor layer is flat. Since the characteristics do not change, it has become possible to form outer layer circuits at a high level of quality.

なお、本笑施例では、絶縁樹脂コート内層板を1枚用い
た4層の多層印刷配線板で説明したが、絶縁樹脂コート
内層板を2枚以上、るるいは通常の工法により形成され
た内層板を組み合せて用いても何ら支障のないことは勿
論である。
In addition, in this example, a four-layer multilayer printed wiring board using one insulating resin coated inner layer board was explained, but two or more insulating resin coated inner layer boards were formed using Rurui or a normal construction method. Of course, there is no problem even if the inner layer plates are used in combination.

【図面の簡単な説明】[Brief explanation of drawings]

第1図tS−一は従来の工法による多層印刷配線板の製
造工程を示す断面図。 第2図(5)〜(F)、第3図(N〜(0,第2図(q
〜(U)は本発明の工法による多層印刷配線板の製造工
程を示す断面図でbる。 ■・・・・・・絶縁基材、2a、2b・・・・・・金楓
箔、3a〜3h・・・・・・感光性樹脂層、4a〜4h
・・・・・・フォトマスク、5a〜5h・・・・・・エ
ツチングレジスト被1戻、6゜16・・・・・・内層板
、7a〜7d、7・・・・・・ブリグレグ、8a、 3
b・・・・・・外層導体層、9.19・・・・・・多層
化基板、lO・・・・・・スルホール% lla 、1
lb−−−−−−内lWI導体ノ曽、12・・・・・・
スルホールめ、@、13,23・・・・・・多層印刷配
線板、14a、14b・・・・・・絶縁樹脂層、15a
、15b・・・・・・片面樹脂コート金楓箔、17a。 17b、17c・・・・・・貫通部、18・・・・・・
絶縁樹脂コート内層板。 慕 / 図 漆 / 田 阜 / 簡 察 2 図 算 2 國
FIG. 1S-1 is a cross-sectional view showing the manufacturing process of a multilayer printed wiring board using a conventional method. Figure 2 (5) - (F), Figure 3 (N - (0, Figure 2 (q
- (U) are cross-sectional views showing the manufacturing process of a multilayer printed wiring board by the method of the present invention. ■...Insulating base material, 2a, 2b...Golden maple foil, 3a-3h...Photosensitive resin layer, 4a-4h
...Photomask, 5a to 5h...Etching resist cover 1 return, 6゜16...Inner layer plate, 7a to 7d, 7...Brig leg, 8a , 3
b...Outer conductor layer, 9.19...Multilayer substrate, lO...Through hole % lla, 1
lb------Inner lWI conductor noso, 12...
Through hole, @, 13, 23...Multilayer printed wiring board, 14a, 14b...Insulating resin layer, 15a
, 15b... One side resin coated gold maple foil, 17a. 17b, 17c... Penetration part, 18...
Insulating resin coated inner layer board. Ho / Illustrated lacquer / Taku / Simple analysis 2 Illustrated calculation 2 Country

Claims (1)

【特許請求の範囲】 導体層に一万の面から選択的にエツチングを施す工程と
、前記エツチングを施した導体層のエツチングを施した
側の表面に絶縁体を形成して絶縁層を形成する工程と、 前記絶縁層を形成させた導体層2枚才グリプレグを介し
て圧着させ第1の内層板を形成する工程と、前記第1の
内層板の表面の所望の位置に工、ソテングを施す工程と
、前記エツチングを施した第1の内層板の表面に絶縁体
を形成し絶縁層ケ形成して第2の内層板全形成する工程
と、 前?3U2第2の内層板t1枚以上内j―に配置し、・
グリプレグを介して外層導体層を圧着させ多層化基板を
形成する工程と、 前記多層化基板にスルホールを形成する工程と、前記ス
ルホールを形成させた多層化基板にスルホールめっ@を
施す工程と、 前記スルホールめっきを施した多層化基板の外層の所望
の位置紫エツチング除去し、外層回路を形成する工程と
からなることを特徴とする多層印刷配線板の製造方法。
[Claims] A step of selectively etching a conductor layer from 10,000 sides, and forming an insulator on the etched surface of the etched conductor layer to form an insulating layer. a step of forming a first inner layer plate by crimping two conductive layers with the insulating layer formed thereon via a preglypreg; and applying machining and sautéing to a desired position on the surface of the first inner layer plate. a step of forming an insulator on the surface of the etched first inner layer plate, forming an insulating layer, and completely forming the second inner layer plate; 3U2 1 or more second inner layer plates t are placed inside j-,
A step of forming a multilayered substrate by crimping an outer conductor layer via a Gripreg, a step of forming through holes in the multilayered substrate, and a step of applying through hole plating to the multilayered substrate with the through holes formed therein. A method for manufacturing a multilayer printed wiring board, comprising the step of removing desired positions of the outer layer of the multilayer substrate subjected to the through-hole plating by ultraviolet etching to form an outer layer circuit.
JP3171384A 1984-02-22 1984-02-22 Method of producing multilayer printed circuit board Pending JPS60176298A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3171384A JPS60176298A (en) 1984-02-22 1984-02-22 Method of producing multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3171384A JPS60176298A (en) 1984-02-22 1984-02-22 Method of producing multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS60176298A true JPS60176298A (en) 1985-09-10

Family

ID=12338703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3171384A Pending JPS60176298A (en) 1984-02-22 1984-02-22 Method of producing multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS60176298A (en)

Similar Documents

Publication Publication Date Title
US4211603A (en) Multilayer circuit board construction and method
US7346982B2 (en) Method of fabricating printed circuit board having thin core layer
US4915983A (en) Multilayer circuit board fabrication process
JP2009283739A (en) Wiring substrate and production method thereof
KR100642167B1 (en) Method for producing multi-layer circuits
JPH10125818A (en) Substrate for semiconductor device, semiconductor device and manufacture thereof
KR100726238B1 (en) Manufacturing method of multi-layer printed circuit board
KR20130031592A (en) Method for manuracturing printed circuit board with via and fine pitch circuit and printed circuit board by the same method
JPH05259639A (en) Manufacture of printed wiring board
JP2010016061A (en) Printed wiring board, and manufacturing method therefor
JPS60176298A (en) Method of producing multilayer printed circuit board
JP2005175185A (en) Flexible wiring board
US6274291B1 (en) Method of reducing defects in I/C card and resulting card
KR100704917B1 (en) Printed circuit board and the manufacturing method thereof
CN87100490A (en) method for manufacturing multilayer printed circuit board
JP2004134467A (en) Multilayered wiring board, material for it, and method of manufacturing it
US6444403B1 (en) Resin laminated wiring sheet, wiring structure using the same, and production method thereof
JPH02301187A (en) Manufacture of both-sided wiring board
JPH06252529A (en) Manufacture of printed wiring board
JP2622848B2 (en) Manufacturing method of printed wiring board
JPH03225894A (en) Manufacture of printed wiring board
KR100468195B1 (en) A manufacturing process of multi-layer printed circuit board
JPH1168308A (en) Manufacture of wiring board
JPS63137499A (en) Manufacture of multilayer printed interconnection board
JP2006269708A (en) Printed wiring board and its manufacturing method