JPS60175173A - Information processing system - Google Patents

Abstract

PURPOSE:To reduce considerably the number of hardwares by controlling main memory access from plural arithmetic processors and plural I/O proccessors and communication among respective processors only by one system control unit. CONSTITUTION:Memory access requests from respective units 2-5 are set up in request receiving circuits 20-23 in an SCU1. The request receiving circuits 20- 23 check whether the addresses of the received memory access requests are included in a specified area or not. If a certain address exceeds the access range, the outarea access error is reported to the requested unit through an answering circuit 24. If the access requests are included in the specified area, a control circuit decides the priority of respective requests in accordance with the signals from the request receiving circuits 20-23, selects the request having the highest priority and sends the selected request to an MMU6 through a request sending circuit 25.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an information processing system configured with loosely coupled multiprocessors.

BACKGROUND OF THE INVENTION Multiprocessor systems having a plurality of processing units are classified into tightly coupled types in which the entire memory area is shared, and loosely coupled types in which the main memory area is not shared. Coarsely coupled multiprocessors have high independence between devices and excellent fault tolerance, but tightly coupled systems are superior to loosely coupled systems in terms of improved performance. On the other hand, normal operations are performed in a tightly coupled system, and when debugging new software, the system is operated in a loosely coupled manner, and operation input is also performed by debugging on an independent system in parallel with business operations. In order to build a paulownia, each device must be completely prepared in 21 units, which poses a problem in that the amount of hardware increases.

That is, the main memory and the input to the main memory fMit
It is necessary to prepare completely duplicate system control devices to control access to the system.

OBJECTS OF THE INVENTION An object of the present invention is to provide a loosely coupled information processing system that minimizes the increase in the amount of hardware.

In other words, the system of the present invention includes a plurality of arithmetic processing units, a plurality of input/output processing units, and a raw memory connected to the main memory access of the plurality of arithmetic processing units and the input/output processing units, and each of the processing units. one system control device that controls communication between the two, a state holding means that maintains whether the plurality of arithmetic processing units are in a tightly coupled operating state or a loosely coupled operating state, and the arithmetic processing unit that is capable of intercourse in the loosely coupled operating state A connection control circuit that maintains a combination of the device and the input/output device, and in a loosely coupled operating state, only communication between the arithmetic processing device and the input/output device specified by the connection control circuit is allowed. It is characterized by

Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes arithmetic processing units (hereinafter referred to as CPU) 2 and 3; input/output processing unit k (hereinafter referred to as l);
0P) 4 and 5; Main memory device (hereinafter referred to as MMU) 6 and system control load that controls access to MMU 6 of CPU 2.3 and l0P4.5 and communication between CPU2.3 and l0P4.5. (hereinafter referred to as '5CU).

The operation of 5CUI differs between tightly coupled mode and loosely coupled mode. This mode is set during initial setup.

In tightly coupled mode, CPUs 2, 3 and 10P45 can access Renci's main memory area and any processor, but in loosely coupled mode, CPU1 can access l0P4.
, CPU2 can only communicate with l0P5.
Communication between I and CPU2 is prohibited. The area of main memory that can be accessed is also limited. The operation in the coarse coupling mode will be explained below with reference to FIG. FIG. 2 is a diagram showing a schematic configuration of 5CUI.

Memory access requests from units 2 to 5 are set in request receiving circuits 20, 21, 22 and 23 of 8CU1. The request reception circuits 20 to 23 have registers that store areas of main memory that can be accessed by each of the processing devices 2 to 5. In this embodiment, each of the request reception circuits 20 to 23 includes two sets of registers for specifying an accessible area in the form of a start address and size, and the values thereof are set at the time of initial setting.

Referring to FIG. 3, the storage area of the MMU 5 is divided into
CPIJ2. l0P4 and cpu3. It is divided into the area of Iop5 Senkawa and the area that can be accessed in common by all the places.

Referring to Figure 2, request reception (b) road 20
．． 21, 22 and 23 check whether the address of the accepted memory access request is within the specified area. If it is outside the access range, the response circuit 24t? sends an out-of-range access error to the requesting device. Report via. If the access request is within the designated area, the control circuit 27 determines its priority according to the signals from the valley request reception circuits 20 to 23, selects the request with the lowest priority, and sends the request to the request transmission circuit 25. MMLJ6
Send to. The MMU 5 performs a write or read operation according to the request and sends the result to the memory rewrite path 26. Further, the reply is sent to the customer via the response circuit 24.

Communication between processing devices is performed as follows. Each place (
The communication request from the CPU (I (JP startup or interrupt report to the CPU from the IOP) from the CPU) is processed by the request reception circuits 20 and 21 in the same way as memory access.

22 and 23. Each time a request is accepted, 'i'r20.2'1, 22 and 23 check based on the initial setting information whether the communication between the processing devices is performed in the coarse coupling mode. Violating accesses are reported to the requesting device in the same manner as memory out-of-area access errors. If the access is permitted, the priority is determined by the control circuit 27, and if the priority is lower, the request is sent to the request destination processing device via the response circuit 24.

In this embodiment, the CPU 3 and l0P5 can access addresses n to (2n-1) and addresses 2n to m of the MMU 6. This correspondence between main memory addresses and program addresses is performed within the CPU using a known page table that is used in the process of converting virtual addresses generated by a program to real addresses in main memory.

Although this embodiment describes a system with one SCU, it is obvious that it can also be applied to a system with 28 CUs shown in FIG. 4, and in the example shown in FIG.
This enables coarse-coupled interlocking of two operating systems.

Effects of the Invention The present invention has the advantage that a coarsely coupled operation system can be constructed with one SCU, so that the amount of node hardware can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of system control @C negative Kirin, FIG. 3 is a diagram showing main memory area allocation, and FIG. Figure 3 is a diagram showing another embodiment of the invention. 1 to 4, 1.7... system control device, 2, 3, 8.9... arithmetic processing unit, 4.5, 9.11... ...I/O processing device key, 6
．． 12... Main memory. MMul-. Figure 3 Cptl 2. l0p4 Aku P Suugekiku Q Shifu j cptn, rθP,, 5 A'/ff Sqa, @ area゛C, pu2.3', l0p4.6 1riPs possible storage area゛

Claims (1)

[Claims] A plurality of arithmetic processing units and a plurality of input/output processing units. a system control device that is connected to a main memory and controls a plurality of arithmetic processing units, main memory access of the input/output processing device, and communication between the respective processing devices; a state holding means for maintaining either a tightly coupled operating state or a loosely coupled operating state; and a connection control circuit that maintains a combination of the arithmetic processing unit and the input/output processing device that can be borrowed in the loosely coupled operating state; An information processing system characterized in that in a coupled operating state, only communication between the arithmetic processing unit and the input/output device specified by the connection control circuit is allowed.