JPS60175172A - Information processing system - Google Patents

Abstract

PURPOSE:To reduce considerably the number of hardwares by dividing one main memory area under roughly coupled state to be used and to access a part of main memory areas in common by plural arithmetic processors. CONSTITUTION:Memory access request from respective units 2-5 are set up in request receiving circuits 20-23 in an SCU1. The request receiving circuits 20-23 check whether the addresses of the received memory access requests are included in a specified area or not. If a certain address exceeds the access range, an outarea access error is reported to the requested unit through an answering circuit 24. When the access requests are included in the specified area, a control circuit 27 decides the priority of the requests in accrodance with the signals from the request receiving circuits 20-23, selects the request having the highest priority and sends the selected request to an MMU6 through a request sending circuit 25.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an information processing system configured with loosely coupled multiprocessors.

BACKGROUND OF THE INVENTION Multiprocessor systems having a large number of processing units are classified into tightly coupled types in which the entire memory area is shared, and loosely coupled types in which the raw memory areas are not shared. A loosely coupled multiprocessor has excellent fault tolerance due to the independence between devices, but a tightly coupled system is superior to a loosely coupled system in terms of improved performance. On the other hand, a continuous system is also used in which normal operations are performed in a tightly coupled manner, and when debugging new software, the system is operated in a loosely coupled manner, and the debugging system is debugged in parallel with business operations. However, in order to construct a loosely coupled system, each device must be prepared in duplicate, which poses the problem of increasing the number of hardware covers.
In other words, the system control device that controls the access of the arithmetic processing unit to the main memory needs to be prepared in duplicate in advance.Objective of the Invention The object of the present invention is to provide a coarse coupling system that minimizes the increase in the amount of hardware. Our goal is to provide information processing systems.

Configuration of the Invention In other words, the system of the present invention includes a plurality of arithmetic processing units, a plurality of human output processing devices, and a main memory connected to each other, and the main memory access of the plurality of arithmetic processing units and the input/output processing device and the processing one system control device that controls communication between devices; a state holding means that maintains whether the plurality of processing devices 7 are in a pipe-coupled operation state or a coarse-coupled continuous state; It has an access check means for checking whether or not the main memory access address of the output processing device is within the main memory area to which access is permitted.
The main memory chain plate of the section is characterized in that it can be accessed in common by the plurality of arithmetic processing units.

Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention is an arithmetic processing device! L (hereinafter referred to as CPU) 2 and 3; input/output processing units (hereinafter referred to as 10P) 4 and 5; main memory unit (hereinafter referred to as MMU) 6 and CPU 2.3 and 10P4゜5's access to MMLJ6 and CP (J2, 3 and 10P4) .5, and a system control unit (hereinafter referred to as 5CU) 1 that controls communications between the 5CUs.

One work of 8CU1 differs between tight coupling mode and coarse coupling mode. This mode is set during initial setup.

In tightly coupled mode, CPU2.3 and l0P4.
5 can access any main memory area and any processor, but in loosely coupled mode, the CPU
'4 and C1'U2 can only communicate with 10P569,
Communication between CPU1 and CPU2 is prohibited, and areas of the main memory that can be accessed are also noted. The operation in the coarse coupling mode will be explained below with reference to FIG. Figure 2 is 8C0
FIG. 1 is a diagram showing a schematic configuration of FIG.

Memory access requests from each of the devices 2 to 5 are set in the 5CUl refinishing circuits 20, 21, 22, and 23. The request reception circuits 20 to 23 are located at six locations [i&2
~5 is a register that stores an accessible area of main memory. In this embodiment, each of the request reception circuits 20 to 23 includes two sets of registers for specifying an accessible area in the form of a start address and size, and the values thereof are set at the time of initial setting.

Referring to FIG. 3, the storage area of the MMU 6 is divided into
CPU2, l0P4 and CPU3. It is divided into an area of 10P5 special river and an area that can be accessed in common by all processing scissors.

Referring again to FIG. 2, the request receiving circuit 20,
21, 22 and 23d Check whether the address of the accepted memory access request is within the specified area. If it is outside the access range, an out-of-range access error is reported to the requesting device itK via the response circuit 24. If the access request is within the designated area, the control circuit 27 determines its priority according to the signals from each request receiving circuit 20 to 23, selects the request with the lowest priority, and sends the request to the request sending (b) path 25. via MMU
Sending child to 6. The MMU 6 performs a write or read operation according to the request and sends the result to the memory reply circuit 26. Further, the reply is sent to the requesting railway bridge via the response path 24.

Communication between processing units is performed as follows. Communication requests from each processing unit (IOP activation #iJ, I or interrupt report from the IOP to the CPU from the CPU) are memory access and network requests) + row circuits 20.21°22 and 23
is set to Valley request reception circuit 20.21.2
2 and 23 check whether communication between processing devices is allowed in the coarse coupling mode based on initial setting information. Violating accesses report access violations to the requestor as well as memory out-of-range access errors. If the access is allowed, the control circuit 27 determines the priority level 1-1, and if it is the highest priority, the request is sent to the hair request processing device via the response circuit 24. The CPU 3 and l0P5 can access addresses n to (2n-1) and addresses 2n to m of the MMU 6. This correspondence between main memory addresses and program addresses is performed within the CPU using a known page table that is used in the process of converting virtual addresses generated by a program into real addresses in main memory.

Although this embodiment describes a system with one SCU, it is obvious that it can also be applied to a system with 28 CUs shown in FIG. 4. In the example shown in FIG. Combined operation is possible.

The present invention has the effect of being able to significantly reduce the amount of hardware because it is possible to construct a loosely coupled operation system with one SOU.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a system control device, FIG. 3 is a diagram showing allocation of main memory areas, and FIG. 4 is a diagram showing an example of the configuration of a system control device. This is a prisoner showing another example. 1 to 4, 1.7... system control device, 2, 3, 8.9... arithmetic processing device, 4.5, 9. il... input/output processing device, 6.
12... Main memory.

Claims (1)

[Claims] A plurality of arithmetic processing units, and a plurality of input/output processing and cages. Main memory access of the plurality of arithmetic processing units and the input/output processing unit connected to the main memory;
one 7-stem control device for controlling communication between the two; a state holding means for maintaining whether the plurality of arithmetic processing units are in a tightly coupled operating state or a loosely coupled operating state; It is equipped with an access check means for checking whether the main memory access address of the processing unit is within the main memory area to which access is permitted, and divides and uses one raw memory area in a loosely coupled state. An information processing system characterized in that a main memory area of the information processing system can be accessed in common by the plurality of arithmetic processing units.