JPS60173859A - Semiconductor ic device - Google Patents

Abstract

PURPOSE:To prevent the capacitance coupling due to parasitic capacitance by a method wherein, in the structure of intersection of wiring conductor layers, an impurity layer and a polycrystalline semiconductor layer are constructed as part of another wiring conductor layer; whereas, in the structure of intersection of the circuit element and the wiring conductor layer, one region in the circuit element is made up of the impurity layer, thus forming the polycrystalline semiconductor layer into the electrode. CONSTITUTION:After an N type epitaxial layer 1 is formed on a P type semiconductor substrate 9, a high concentration P type semiconductor region 10 is formed and isolated into a plurality of island regions. Successively, a high concentration N type semiconductor region 11 is formed in the isolated N type epitaxial region 1. Next, an Si oxide film 2 is formed by selective oxidation. After removal of the nitride film on an aperture 12, a polycrystalline Si layer is grown, and further the polycrystalline Si layer other than in the neighborhood of the aperture 12 is changed into an Si oxide film 4; then, a high concentration N type semiconductor region 13 is formed on the remaining polycrystalline Si layer 3. A Pt silicide layer 5 is formed on the Si layer 3. This silicide layer 5 is exposed by forming an oxide film 6, and wiring regions 7 and 7' are formed at the same time. This manner enables the prevention of the coupling of intersecting wirings or wirings with each other due to parasitic capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to integrated circuit devices, and particularly to semiconductor integrated circuit devices using so-called PSA technology.

(Prior art) PSA (Polysilicon Self-Ali
gned) Technology (IEEE 5solid-8tate)
C4rcuits 5C-I30ct.

In semiconductor integrated circuit devices (hereinafter referred to as ICs) using technology (see 1978 PP693-698), platinum silicide is formed on the surface of a polysilicon layer to lower the layer resistance of this polysilicon layer to about 5 Ω/gate. In addition, the parasitic capacitance between the polysilicon layer and the semiconductor substrate is small. Taking advantage of this advantage, at a location where two metal wires must cross, it is possible to create a structure in which one wire is connected to a polysilicon layer and the other wire is passed over the polysilicon layer.

FIG. 1 is a sectional view showing a conventional structure of a wiring intersection to which the PSA technology is applied. In the figure, 1 is a semiconductor silicon substrate, 2 is a thermal oxide film, 3 is a polysilicon layer, 4 is a second thermal oxide film formed by selectively oxidizing the polysilicon layer 3, and 5 is a polysilicon layer 3. A platinum silicide layer is formed on top to lower the resistance, 6 is a third silicon oxide film formed by CVD, etc., and 7 and 7' are two low resistance wiring layers that must be crossed. (For example, it is made of metal such as aluminum).

Polysilicon layer 3 is formed for the intersection of two interconnections N7 and 7'. That is, the wiring layer 7 is divided into two parts and connected to the platinum silicide N5 through the openings 8 formed in the third oxide film 6 to realize spot gas conduction. Another wiring layer 7 is formed on the oxide film 6 on the platinum silicide layer 5, making it possible for the wiring layers 7 and 7' to intersect.

In this way, in an IC to which the PSA technology is applied, wiring lines can easily cross each other.

Recently, ICs that operate at high frequencies have been designed because transistors using PSA technology have high fT. Therefore, the coupling due to capacitance between the wiring layer 7' and the platinum silicide layer 5 at the intersections of the wirings, which was hardly a problem in conventional ICs, can no longer be ignored. Especially, the influence of signal interference is noticeable between the input circuit of a high-gain amplifier circuit and the output circuit through which a relatively large signal flows.

This signal interference can also occur between wiring and circuit elements. That is, in ICs, a technique is often used in which all other wiring lines cross over the collector region of a transistor.

FIG. 2 is a sectional view showing a conventional example in which a darning crossing is performed. 9 is a P-type silicon substrate, l is an N-type epitaxial layer, 10 is a P-type isolation region, and 14 is an NPN
) A heavily doped N-type buried region 15 provided to reduce the collector series resistance of the transistor is formed by fully ion-implanting P-type impurities such as boron to a depth of 0.8 μm.

Layer resistance IKΩ/base region 16 is diffused from the upper polycrystalline silicon layer 3-1 to a depth of 0.6μ, layer resistance 1
00Ω/hole heavily doped P-type base contact region. 13-1 is an emitter region.

Further, 11 is an N-type collector lead-out region connected to the buried region, and 13-2 is a collector contact region. Furthermore, 3-1.3-2U Emitsuta.

Polysilicon e for collector, 7-1, 7-2, 7
-3 are base, emitter, and collector electrode wirings, respectively. 2, 4.6, as shown in FIG. This is the third oxide film. The wiring 7' is a platinum silicide 5' formed on the collector polysilicon layer 3-3.
and intersect with each other through the oxide film 6. In this structure, the distance between the wiring 7' and the platinum silicide layer 5 is 5000A.
Since there is only the oxide film 6, capacitive coupling cannot be ignored.

In order to avoid such signal interference, countermeasures were taken such as specifying in advance the wiring that cannot cross each other or the wiring and circuit elements, and detouring one of the wirings, but the layout of the wiring and circuit elements There were disadvantages such as a decrease in the degree of freedom and a decrease in the degree of integration.

(Object of the Invention) An object of the present invention is to provide a semiconductor integrated circuit device that prevents capacitive coupling due to parasitic capacitance.

(Structure of the Invention) That is, the present invention provides a first insulating film that is partially buried in an impurity layer, a polycrystalline semiconductor layer that is in contact with a part of this impurity layer, and a polycrystalline semiconductor layer that is provided on a first insulating film. It has a second insulating film formed by oxidizing a polycrystalline semiconductor, a third insulating film further formed on the second insulating film, and a conductor layer on the third insulating film. It is characterized by the formation of

In the cross structure of two wiring conductor layers, one wiring conductor layer is formed as a conductor layer formed on a third insulating film, and an impurity layer and a polycrystalline semiconductor layer are formed as part of the other wiring conductor layer. configured.

In the cross structure of a circuit element and a wiring conductor layer, the conductor layer formed on the third insulating film serves as a wiring conductor layer, and the impurity layer constitutes a region within the circuit element and serves as a polycrystalline semiconductor layer. has as an electrode.

In this way, since three layers of insulating films are interposed, capacitive coupling is sufficiently prevented.

(Examples) Hereinafter, examples of the present invention will be described with reference to the drawings. Explain in detail.

FIG. 3 is a sectional view showing the first embodiment of the present invention.

To explain this along with the manufacturing process, first, the specific resistance is 1~
An N-type epitaxial layer 1 having a resistivity of about 1 Ω·α and a thickness of about 5 μm is formed on a P-type semiconductor substrate 9 having a resistivity of about 3 Ω. Next, the surface of the epitaxial layer l is covered with P such as cibron.
A heavily doped P-type semiconductor region 10 is formed by diffusing type impurities to reach the P-type semiconductor substrate 9, and the N-type epitaxial layer 1 is separated into a plurality of island regions. Next, in one separated N-type epitaxial region 1, N-type impurities such as phosphorus are back-diffused from the surface to a depth of 3 μm2 with a surface concentration of 1×1.
A high concentration Nm#=conductor region 11 of approximately 0 CTL is formed.

Next, a silicon oxide film with a thickness of approximately 1 μm is partially buried in the semiconductor by selective oxidation at 1000° C. for several hours so as to exclude the opening 12 connecting to the wiring region to be formed in the upper part. form 2. After removing the nitride M used for selective oxidation and formed on the opening 12, a polycrystalline silicon layer is grown over the entire surface to a thickness of about 5800A.
Further, by selective oxidation technology, the polycrystalline silicon layer except the vicinity of the opening 12 is changed to a silicon oxide film 4 having a thickness of about 13 μm. After that, the polycrystalline silicon layer 3 remaining in the opening 12
Then, when an N-type impurity is diffused and a heat treatment is performed, the N-type impurity is diffused from the semiconductor surface directly under the polycrystalline silicon layer 3, and a second layer having a concentration similar to that of the N-type impurity is diffused into the high concentration N-type semiconductor region 11. Two high concentration N-type semiconductor regions 13 are formed. Next, a platinum silicide layer 5 with a thickness of about 2000 Å is formed on the polycrystalline silicon layer 3 to reduce contact resistance.

Next, an oxide film 6 having a thickness of about 5000 Å is formed by the CVD method, and an opening that allows the platinum silicide layer 5 to be completely exposed is partially removed. Finally, aluminum is deposited on the entire surface as a wiring material to a thickness of about 12 μm, and this is selectively removed to form a highly doped N-type semiconductor region 11.
A wiring region 7 connected to this wiring and another wiring region 7' crossing this wiring are formed at the same time.

At the intersection of the wirings obtained in this way, one side of the aluminum wiring 7' and the other wiring side of the high concentration N
There are 3N oxide films 2, 4, and 6 between the mold region 11, and the total thickness thereof is 2a000X, which is 56 times that of the conventional structure os and oooX. As a result, wiring 7
The capacitance between ' and region 11 is (56)', or about 0.1
It is greatly reduced by 8 times and can prevent capacitive coupling. Therefore, intersections can be freely provided without worrying about mutual interference between wires, achieving high integration and without reducing the degree of freedom in design.

FIG. 4 is a cross-sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention, and is a cross-sectional view of a semiconductor integrated circuit in which a conductive wiring is crossed on the collector of an NPN synristor, and in which RIA is performed. It is. In FIG. 4, the same components as in FIG. 2 are indicated by the same numbers, and their explanation will be omitted. The main difference from FIG. 2 is that the N-type region 1 in contact with the buried region 14 is formed widely, an oxide film 2 is formed on the surface except for a part of it, and second and third layers are formed on top of it. Oxide films 4 and 6 are formed, and wiring 7' is formed thereon. Therefore, the oxide films 2, 4, and 6 are interposed between the transistor and the conductive wiring 7', and coupling from the conductive wiring 7 to the collector of the NPN transistor due to parasitic capacitance is less likely to occur. The same effect as the embodiment (FIG. 3) can be obtained at the intersection between the two.

As described above, according to the present invention, coupling due to parasitic capacitance between a circuit element and conductive wiring that crosses the circuit element, or
Coupling due to parasitic capacitance between electric wires can be prevented, and a high performance, highly integrated semiconductor integrated circuit device can be obtained.

Note that the present invention is applicable to conductive wiring, other conductive wiring, and NPN.
) Explained for the gold side the cross structure with the transistor,
Similar effects can be obtained even if the present invention is implemented between other circuit elements such as PNP transistors and capacitors and conductive wiring.

[Brief explanation of drawings]

1 and 2 are partial cross-sectional views of conventional semiconductor integrated circuit devices, respectively. FIGS. 3 and 4 are partial cross-sectional views showing embodiments of the present invention, respectively. 1...Semiconductor substrate, 2...Insulating film (oxide film)
, 3... Polycrystalline silicon layer, 4... Oxide film, 5
...Platinum silicide layer, 6-...Oxide film, 7
, 7'... Conductive wiring, 8... Opening part, 9
...P-type semiconductor substrate, 10--high concentration P-type diffusion region, 11--high concentration N-type diffusion region, 12-.
・ Opening part, 13・ N-type diffusion region, 14...
High concentration N-type buried region, 15... P-type base region, 1
6...High XUP type base contact region. Agent Patent Attorney Susumu Uchihara 3 Figure 1 10 + 14 7 1110 Figure 2

Claims (3)

[Claims] (1) a first insulating film partially buried in an impurity layer; a polycrystalline semiconductor layer in contact with a portion of the impurity layer;
a second insulating film provided on the insulating film and formed by oxidation of a polycrystalline semiconductor; a third insulating film formed on the second insulating film; and a third insulating film formed on the third insulating film. conductor layer, and the first conductor layer is formed under the conductor layer. A semiconductor integrated circuit device characterized in that second and third insulating films are present. (2) The semiconductor integrated circuit device according to claim 11, wherein the impurity layer and the polycrystalline semiconductor layer constitute a part of another conductor layer. (3) The semiconductor integrated circuit device according to claim (1), wherein the impurity layer constitutes a part of a circuit element.