JPS60171838A - Pcm-adpcm mutual converting device - Google Patents

Abstract

PURPOSE:To lock multi-frame phase by transmitting frame phase matching and multi-frame phase difference information to plural PCM signal trains where the frame phase and the multi-frame phase are not matched mutually. CONSTITUTION:The frame synchronism is taken from the PCM signal train at synchronism circuits 4, 5 and the signal is locked to the same frame phase by frame aligners 6, 7. A synchronizing signal is detected by multi-frame detectors 8, 9 from each PCM signal train and the phase difference is detected by a multi- frame phase difference discriminating circuit 14. A reference multi-frame phase difference discriminating circuit 14. A reference multi-frame synchronizing signal is generated in response to the synchronizing signal, the synchronized PCM signal train is applied with ADPCM coding at an ADPCM coder 12, and the signal applied with ADPCM coding and the PCM signal are selected switchingly by a PCM/ADPCM switching circuit 16, and the frame is formed by the said PCM/ ADPCM signal, the reference multi-frame synchronizing signal and a multi-frame phase difference signal at a format converting circuit 15.

Description

Detailed Description of the Invention [Technical Field] The present invention has a multi-frame structure on the transmitting side, and uses PCM to transmit frames in which mutual frame phases and multi-frame phases are different.
At least two signal sequences are received, these PCM signal sequences are converted into an ADPCM signal sequence equivalent to one sequence by ADPCM encoding means, and sent to the transmission path, and on the receiving side, the above-mentioned ADPCM encoding means and PCM-ADP is converted into the original two PCM signal sequences by the reverse means.
The present invention relates to a CM mutual conversion device.

<Prior art> PCM signal having a frame structure, for example 1.544
1ijb-, (SPCM The details of the primary group multiplex frame structure are stipulated in CCITT Recommendation G, 78B. In this recommendation, one frame is 198 bits (192 information bits + 1 frame synchronization bit). bits) and 12 bits for signaling information transmission.
It has a multi-frame structure in which frames are grouped into one group.

The signaling information is transmitted by converting the normally 8-bit encoded audio channel to 7-bit encoding every six frames, and inserting signaling bits into vacant time slots.

Two series ADPC of such PCM primary group audio signal
Bandwidth compression is performed by M encoding, and IJ44
Transmission at a transmission bit rate equivalent to one Mb/S sequence is being considered.

Normally, in order to process multiple series of PCM signals having a frame structure, mutual bit synchronization and frame phase synchronization are required.

Generally, the frame phases of each PCM signal sequence do not match, and therefore a frame aligner is required to match the mutual frame phases. This frame aligner can be realized with simple hardware using FIFO memory, elastic store memory, etc.
The circuit configuration is also well known.

As described above, signaling information is inserted into each PCM signal train every six frames. This signaling information is extracted and stored in temporary memory before being ADPCM encoded. Thereafter, the signal is inserted into a predetermined time slot in the ADPCM signal sequence and transmitted to the receiving side. When returning to the original two-series PCM signal sequence on the receiving side by means opposite to ADPCM encoding, it is necessary to form a multiframe structure and insert signaling information in the same way as on the transmitting side. Generally, multiframe phases are synchronized on the transmitting side, and this allows the insertion position of signaling information to be determined when reconstructing the multiframe on the receiving side, thereby preventing quality deterioration.

Conventionally, multiframe analysis power was required for this multiframe phase synchronization.

This can be achieved by increasing the memory capacity of a normal frame aligner by an amount corresponding to multiple frames.

Compared to a frame aligner, this multi-frame aligner requires approximately 12 times the memory capacity when one multi-frame is composed of 12 frames, for example. This means that the signal propagation delay increases by 1 as the memory capacity increases.
This means a two-fold increase. Therefore, providing a multi-frame aligner is not preferable in terms of 8-1 wear and transmission characteristics.

<Object of the Invention> Therefore, an object of the present invention is to provide a PCM-ADP that can perform multi-frame phase synchronization with a simple configuration without increasing hardware or deteriorating transmission characteristics.
The purpose of the present invention is to provide a CM mutual conversion device.

<Configuration of the Invention> The PCM-ADPCM mutual conversion device of the present invention includes means for performing frame synchronization and multiframe synchronization for each received PCM signal sequence, and means for aligning these PCM signal sequences to the same frame phase. means for detecting a multiframe synchronization signal from each frame-phase synchronized PCM signal sequence; means for detecting a phase difference between these multiframe synchronization signals; and a means for detecting a reference multiframe synchronization signal in response to these multiframe synchronization signals. means for generating the synchronized PCM signal, means for ADPCM encoding the synchronized PCM signal string, switching means for selectively outputting the ADPCM encoded signal and the PCM signal, and an output of the switching means. The transmission side is equipped with a means for configuring a transmission path frame by the PCM/ADPCM signal, the reference multiframe synchronization signal, and the multiframe phase difference signal, and the received multiframe synchronization signal position information of at least two series is used as the reference multiframe synchronization signal. and multi-frame phase difference information.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 and FIG. 2 each show a PC according to an embodiment of the present invention.
FIG. 8 is a block diagram of the transmitting side and receiving side of the M-ADPCM mutual conversion device, and is a diagram showing the structure and timing of each PCM signal sequence and MF synchronization signal.

On the transmitting side, the mutual frame phase received at terminals 1 and 2,
PCM signal sequence PCM (,
r), synchronization circuit 4゜5 for frame synchronization of PCM (K), PCM signal train PCM (J), PC
M (Frame aligner 6 that matches the frame phase of the costume)
．． 7. PCM signal sequence PCM with matched frame phase
(J), multiframe detector for detecting multiframe synchronization signals from PCM (K) 8.9. Signaling memory circuits 10 and 11 temporarily store signaling information of phase-aligned PCM signal sequences PCM (J) and PCM (K) in response to a multi-frame synchronization signal.
．． A multiframe phase difference determination circuit 14 that detects the phase difference between both multiframe synchronization signals ADPCM (Ll multiframe synchronization signal generation circuit 1B, frame Phase matched PCM signal train PC
ADPCM encoder 12 which ADPCM encodes M (Jl, PCM (K). PCM signal from frame aligner 6.7 and ADP from ADPCM encoder 12
A ring memory circuit 10 that switches and selects a CM encoded signal and outputs it, that is, transmits PCM as it is or transmits ADPCM encoded data depending on the amount of traffic.
．． 11 and the ADPCM (a reference multi-frame synchronization signal from the Ll multi-frame synchronization signal generation circuit 18 and a phase difference signal of the multi-frame synchronization signal from the multi-frame phase difference determination circuit 14), a transmission line frame is constructed, It consists of a format conversion circuit 15 that outputs from the terminal 8 via a transmission line to the receiving side.

On the receiving side, after performing frame synchronization and multi-frame synchronization of the ADPCM (L) signal train input from terminal 21,
The multi-frame phase difference signal inserted in the ADPCM (L) signal sequence with the PCM signal sequence PCM (
°frame synchronization circuits '2, 2 . In response to the write control signal from the frame synchronization circuit 22, the PCM signal sequence PCM(J),
Signaling memories 28, 24.into which PCM(K) signaling information is written. The ADPCM encoder 12 on the transmitting side converts the ADPCM (Ll signal sequence into the original 8-bit PCM signal sequence PCM (J)', PC
M ([ADPCM decoding circuit 25 that decodes to 0'. PCg/ADPCM switching circuit z6 that switches depending on settings whether to use the transmitted PCM signal or the ADPCM decoded PCM signal, and the switching circuit amount 6 The multi-frame synchronization signal from circuit 22 causes this PCg to
A PCM (J
T frame configuration circuit 2 'I', PCM (Kl') Consists of frame configuration circuit 28.

Next, the operation on the transmitting side will be explained with reference to the block diagram of FIG.

At terminals l and 2, two signal sequences PCM (J) and PCM (J) and PCM (J) with mutually different frame phases and multi-frame phases are generated.
CM(8)) are received. Here, the PCM signal sequence PCM (Jl, PCM (Jl) is 12 channels of audio PJ, , PJ where one frame is 8 bits per channel).
,...

P JB (P Kl + P Kl e...” P
Ku ) + T 9 and 1-bit frame synchronization signal F
It consists of 6 frames F, , F, ,...

F6 constitutes one multiframe. It is assumed that the audio channels of the 8th frame and the 6th frame are encoded in 7 bits, and the LSB is used for signaling information A and B. The received PCM signal sequences PCM (J) and PCM (fQ) are applied to synchronization circuits 4 and 6, respectively, to achieve frame synchronization, as shown in FIG. 8 (1).

(2) becomes as follows. The frame-synchronized PCM signal strings PCM(J) and PCM([0 do not yet match each other in frame phase, and these are input to frame aligners 6 and 7, respectively.Here, the PCM signal strings PCM (Jl and PCM (10) are arranged so that the frame phases of the signal trains match each other, and are shown in Fig. 8 (31
, +41 shows the 5 PCM signal sequence PCM (JY,
PCM (K)'.

However, the PCM signal sequences PCM(J)', PCM
Even if the phase of a single frame matches, the phase of multiple frames does not match. As mentioned above, in order to match the multi-frame phases, a multi-frame aligner is required, and the memory capacity for the multi-frames is also required, which not only increases the number of 71-domain squares, but also increases the propagation delay time for the multi-frames. Therefore, it is not preferable in terms of transmission characteristics.

In the present invention, PCM signal sequences PCM (J) and PCM (K) are AD
This is to obtain the same functions and characteristics as performing PCM encoding processing, transmitting mutual multi-frame phase information of PCM signal sequences PCM (, y) and PCM (K) to the receiving side, and performing multi-frame alignment.

The PCM signal sequence PCM (Jf and PCM (K)' which is the output from the frame aligner 6.7 is the multi-frame detector 8, 9 and the signaling memory circuit 10.1.
1 and is added to the ADPCM encoder 12. Figure 8+6 in multi-frame detector 8.9
1, (as shown in 71, the PCM signal sequence PCM (J
)' and the MF synchronization signal of the PCM signal sequence PCM(6)l are detected, the signaling memory circuits 10, 11, the ADPCM(L) output multiframe generation circuit 18, and the multiframe phase difference determination. added to circuit 14. In the signaling memory circuit 10 and the signaling memory circuit 11, ring information A and B are temporarily stored. In the ADPCM encoder 12, the PCM signal sequence PCM (J)' and PCM (8 pins of 1 light) PCM (4 pins) ADPCM
After converting it into , it is sent to the PCFJAD PCM switching circuit 16. PC/ADP (Groove switching circuit 16 is set depending on the setting.
PCM or ADPCM sequence P(Ji (J)' M
ADPCM (L) using either the F synchronization signal or the MF synchronization signal of the PCM signal sequence PCM(K)' as a reference.
The MF synchronization signal is generated and sent to the format conversion circuit 15. Normally, the PCM signal sequence P as shown in Figure 8 (8)
The MF synchronization signal of CM (J)' is used as a reference phase setting signal, and the PCM signal train PCM (Jf/iF
PCM signal train if synchronization signal cannot be used? CM
Change to the MF synchronization signal of (K)'. ADPCM (
The method for setting the MF synchronization signal of L) is, for example, ADPCM.
(This can be easily done by loading the value of the multi-frame counter of Ll to a constant value using the MF synchronization signal of the PCM signal sequence PCM (J)'.
The phase difference between the synchronization signal and the MF synchronization signal of the PCM signal sequence PCM (K)' is calculated. There are various ways to calculate it, but an easy way is to calculate the PCM signal sequence PCM (J)'
Considering the case where the start address of the multi-frame counter of ADPCM (L) is loaded by the MP synchronization signal of PCM (K)', the address value of the multi-frame counter described above is read by the MF synchronization signal of PCM signal sequence PCM (K)', and then, The difference from the start address value becomes the phase difference. If you set the start address to address 0, the PC
The counter address value itself read by the MF synchronization signal of the M signal sequence PCM()0' becomes multiframe phase difference information. This multi-frame phase difference information is sent to the format conversion circuit 15. In the format conversion circuit 15, data PJ, γPJ, PK, ~PK, , AJI~ from the PCM7/ADPCM switching circuit
AJII, AKI~AKII and signaling information A, B and ADPC from the signaling memory circuit 10゜11
M (L) In response to the ADPCM (current MF synchronization signal) from the multiframe synchronization signal generation circuit 18 and the phase difference between the multiframe synchronization signal from the multiframe phase difference determination circuit 14, as shown in FIG. 8 (5). An ADPCM (L) signal train is constructed. In this embodiment, the ADPCM encoded data is AJ i (i=1 to 11) and AKi (i=
(AJ
1, AKI), (AJ2, AK2), old,
...(AJll, AKll) Arranged like this,
TS121'? One frame includes signaling information A, B and multi-frame phase difference information. Also,
When transmitting a mixture of PCM data and ADPCM encoded data, the PC
M1 channel. For example, (AJ, , AKl
), (PJ2), (PK!), 1 old... (AJI
This results in signal sequences such as II, AKll1), and (PJll). Then, the ADPCM (Ll signal sequence is
As shown in Figure 8 (9), 6 frames R, r, +F8
, p'4+FI *F8 is assumed to be 1° multi-frame. The contents of TS12 are shown in the table below.

Here, bit Gl + GI * Gs eG4 is used as multi-frame phase difference information. That is, P.C.
M signal strings PCM (J) and ADPCM (bit G is “0” if the multi-frame phases of the scent match)
, PCM signal sequences PCM(K) and ADPCM (bit G1 if the multi-frame phases of the signals match)
is represented by ll@, and bits G, , G3 . The 8 bits of G represent the phase difference O to 7 between the PCM signal sequence PCM (Jl and PCM (6). If one multiframe consists of 6 frames as in this example, 8 bits is sufficient. Yes, if the number of multi-frames is large, the frame configuration may be changed and the tema/I/chi frame phase difference information bits may be increased.

As described above, multi-frame phase difference information is converted into ADPC.
It is inserted into the MILI signal train and transmitted from terminal 8 to the receiving side in FIG.

Next, the operation on the receiving side will be explained with reference to FIG. The ADPCM (L) signal train applied to the terminal 21 is first applied to the frame synchronization circuit z2. After frame synchronization and multiframe synchronization are achieved in this frame synchronization circuit 22, multiframe phase difference information 01 to G4 inserted in the ADPCM (L) signal sequence is extracted, and the PCM
The signal strings PCM (J) and PCM (Kl) are reproduced. At the same time, the PCM signal string PC
Generates write control signals for the signaling memory circuits 28, 24 of M (Jl and PCM(K)).

ADPC with frame synchronization and multi-frame synchronization
The M (L) signal train is connected to the signaling memory circuit 28゜2.
4 and at the same time P(4/ADPCM switching circuit 2
6 and the ADPCM decoding circuit z5. In the signaling memory circuits 28 and 24, in response to the write control signal from the frame synchronization circuit z2, the signaling information A of the PCM signal train PCM (J) is sent to the signaling memory circuit 28, and the signaling information B of the PCM signal train PCM (6) is sent to the signaling memory circuit 28. is written into the signaling memory circuit 24. In the ADPCM decoding circuit 25, ADPCM (L
) Signal train C, transmitting side 17) The original PCM (J)' and PCM
(K)' is decoded into 8-bit PCH, PCMADPc
It is added to the M switching circuit 26. The switching circuit membrane 6 selects either the transmitted PCM signal or the ADPCM-decoded PCM signal to the PChgADPα switching circuit z6.

PCM (Jl' and PCM (K)' frame configuration circuits 27 and 28 have a PCg/ADPCM switching circuit 26
The output of V, the signaling information A and B from the V bunarinda memory circuit 28 and the signaling memory circuit 24 are added, and the MF multiplied signal of the PCM signal string PCM (J) and the PCM signal string PCM are added from the frame synchronization circuit 22.
(K) MF times signal is added. PCM (J)
', PCM (Kl' frame (Jl, PCM
Each signaling information A and B of ()0 is a PCM signal sequence PC
M(J) is inserted into the correct bit position of PCM(K).

Through the above operations, it becomes possible to insert the signaling information A and B into the same frame position and bit position as on the transmitting side.

<Effects of the Invention> According to the present invention, the frame phase can be adjusted without providing a multi-frame aligner for performing multi-frame phase alignment for a plurality of PCM signal streams whose frame phases and multi-frame phases do not match each other. By sending phase alignment and multiframe phase difference information, it is possible to reconstruct multiframes on the receiving side.In particular, when only a specific channel is transmitted as PCM without ADPCM encoding, it is possible to insert signaling information. Since the position can be determined, it is possible to prevent quality deterioration in the audio channel due to reinsertion of signaling information.Furthermore, since the multi-frame 4 ina is not required, the signal transmission delay corresponding to the memory capacity required for multi-frame alignment is reduced. can be removed, improving characteristics.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 each show a PC according to an embodiment of the present invention.
FIG. 8 is a block diagram of the transmitting side and receiving side of the M-ADPCM mutual conversion device, and is a diagram showing the structure and timing of signals. 1, B, 8: terminal, 4, 5: synchronous circuit. 6.7: Frame aligner. 8.9: Multi-frame detector. 10.11: i/Gnarinda memory circuit. 1.2: ADPCM encoder. 18: ADPCM (L) multi-frame synchronization signal generation circuit・■4=Multi-frame phase difference determination circuit. 15: Format conversion circuit. 16: PCg/ADPCM switching circuit. Patent applicant: NEC Corporation

Claims (1)

[Claims] On the transmitting side, at least two sequences of PCM signal sequences having a multi-frame structure and different frame phases and multi-frame phases are received, and these PCM signal sequences are transmitted to the ADP.
ADPCM equivalent to one series by means of CM encoding
It is converted into a signal string and sent to the transmission path, and on the receiving side, the above A
In a PCM-ADPCM mutual conversion device that converts into two original PCM signal sequences by means opposite to the means for DPCM encoding, means for performing frame synchronization and multiframe synchronization for each received PCM signal sequence. , means for aligning these PCM signal sequences to the same frame phase, means for detecting a multi-frame synchronization signal from each frame-phase synchronized PCM signal sequence, and means for detecting a phase difference between these multi-frame synchronization signals. and means for generating a reference multiframe synchronization signal in response to any of these multiframe synchronization signals, and said synchronized PC.
means for ADPCM encoding an M signal sequence;
a switching means for selectively outputting the CM encoded signal and the PCM signal; and a PCM signal which is the output of the switching means.
PCM-A, characterized in that the transmitting side is equipped with means for configuring a transmission path frame using the ADPCM signal, the reference multiframe synchronization signal, and the multiframe phase difference signal.
DPCM mutual conversion device. ′