JPH0662039A - Cell forming and encoding system - Google Patents

Cell forming and encoding system

Info

Publication number
JPH0662039A
JPH0662039A JP21250892A JP21250892A JPH0662039A JP H0662039 A JPH0662039 A JP H0662039A JP 21250892 A JP21250892 A JP 21250892A JP 21250892 A JP21250892 A JP 21250892A JP H0662039 A JPH0662039 A JP H0662039A
Authority
JP
Japan
Prior art keywords
cell
signal
bits
circuit
pcm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21250892A
Other languages
Japanese (ja)
Other versions
JP2826423B2 (en
Inventor
Toru Yasuda
透 安田
Tamami Matsuyama
珠美 松山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP21250892A priority Critical patent/JP2826423B2/en
Publication of JPH0662039A publication Critical patent/JPH0662039A/en
Application granted granted Critical
Publication of JP2826423B2 publication Critical patent/JP2826423B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To provide a cell forming and encoding system for an ATM transmission line provided with cell abandonment compensation for which the degradation of transmission efficiency is less with a simple circuit by multiplexing two cells constituted of bits whose importance is different and transmitting them. CONSTITUTION:The upper 8 bits of a 9-bit PVM signal are made into the cells by a cell forming circuit 12, the upper 7 bits and the lowest 1 bit are made into the cells by the cell forming circuit 15 and the output signals of the two cell forming circuits are multiplexed by a multiplex circuit 14 and outputted to a transmission line 20. The 9-bit PCM is outputted from the two cell signals when there is no cell abandonment on the transmission line in the selection circuit 24 of a reception example and when either of the cell signals is abandoned, 8-bit PCM signal is outputted from the other cell signal.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は音声、画像信号の符号化
方式に関し、特にATM(Asynchronuo T
ransfei Mode,非同期転送モード)方式の
装置に用いられ信号が伝送中にセル廃棄を受けた場合に
対応するセル化符号方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding system for voice and image signals, and more particularly to an ATM (Asynchronous T
The present invention relates to a cell coding system which is used in a device of a transfer mode (asynchronous transfer mode) system and corresponds to a case where a signal undergoes cell discard during transmission.

【0002】[0002]

【従来の技術】従来、この種のセル化符号化方法は、セ
ル廃棄補償対策として、全く同一のセルを2度繰り返し
て伝送する方式、あるいは、階層化符号化と呼ばれる周
波数領域で分割して低周波数領域のセルと高周波数量域
のセルを伝送する方法等が用いられている。
2. Description of the Related Art Conventionally, as a cell discard compensation measure, this type of cell coding method is a method in which the same cell is repeatedly transmitted twice or divided in a frequency domain called hierarchical coding. A method of transmitting cells in the low frequency range and cells in the high frequency range is used.

【0003】[0003]

【発明が解決しようとする課題】ATMの伝送路を利用
して音声信号や画像信号を伝送する場合、ATM伝送路
の特徴であるセル廃棄が起きると廃棄されたセル分の情
報が失われてしまうという問題があり、セル廃棄を補償
するために全く同一のセルを繰り返し伝送したり階層化
符号化を用いて低周波数領域を優先セル(セル廃棄の確
率が低いセル)に指定するなどの方法があるが、全く同
一のセルを2度繰り返して伝送する方法は効率が悪いと
いう欠点が有り、また階層化符号化方法は、符号化が複
雑で単純な符号化を行う場合にはハード量の追加が大き
すぎる、また、優先セルを利用しているが優先セル自体
も廃棄される場合は無効となる問題がある。
When a voice signal or an image signal is transmitted using an ATM transmission line, when the cell discard, which is a feature of the ATM transmission line, occurs, information about the discarded cells is lost. There is a problem that the same cell is repeatedly transmitted to compensate for the cell loss, or a low frequency region is designated as a priority cell (cell with a low probability of cell loss) by using hierarchical coding. However, the method of repeatedly transmitting the same cell twice has the drawback of being inefficient, and the layered coding method is complicated in coding and requires a large amount of hardware when simple coding is performed. There is a problem that the addition becomes too large, and when the priority cell is used but the priority cell itself is also discarded, it becomes invalid.

【0004】[0004]

【課題を解決するための手段】本発明のセル化符号化方
式は、音声あるいは画像信号をPCM信号に符号化し、
前記PCM信号を複数個まとめてセルを構成し伝送する
装置において、時刻Tの入力信号をNビット(Nは自然
数)でPCM符号化しM個をまとめてセルを構成する第
一のセルと、前記第一のセルと同一時刻Tの同一入力信
号を(N+n)ビット(nは自然数,N〉n)でPCM
符号化を行い前記(N+n)ビットの内上位(N−n)
ビットと下位nビットをM個まとめてセルを構成する第
二のセルとの2個のセルにセル化をおこない前記第一の
セルと前記第二のセルとを多重化し伝送している。
According to the cell coding system of the present invention, a voice or image signal is coded into a PCM signal,
In a device for constructing and transmitting a cell by combining a plurality of PCM signals, a first cell that PCM-encodes an input signal at time T with N bits (N is a natural number) to compose M cells to form a cell; PCM the same input signal at the same time T as the first cell with (N + n) bits (n is a natural number, N> n)
Encoded and the upper (N-n) of the (N + n) bits
The first cell and the second cell are multiplexed and transmitted by performing cell formation into two cells, that is, a second cell forming a cell by combining M bits and lower n bits.

【0005】[0005]

【実施例】次に、本発明の一実施例について図面を参照
して説明する。
An embodiment of the present invention will be described with reference to the drawings.

【0006】図1は本発明のセル化符号化装置の実施例
のブロック図である。入力端子Aから入力された入力信
号101はA/D変換器11に入力される、A/D変換
器11では入力信号101を9ビットのPCM信号に変
換する。9ビットのPCM信号のうち上位7ビット(こ
の場合上位とはビットの重要度順位をいう)のPCM信
号102をセル化回路12とセル化回路15とに出力
し、第8ビットのPCM信号103をセル化回路12に
最下位の第9ビットのPCM信号104をセル化回路1
5にそれぞれ出力する。
FIG. 1 is a block diagram of an embodiment of a cell coding device according to the present invention. The input signal 101 input from the input terminal A is input to the A / D converter 11. The A / D converter 11 converts the input signal 101 into a 9-bit PCM signal. Of the 9-bit PCM signal, the PCM signal 102 of the higher 7 bits (in this case, the higher order means the bit importance order) is output to the cell assembling circuit 12 and the cell assembling circuit 15, and the PCM signal 103 of the 8th bit is outputted. To the cell assembling circuit 12 and the least significant 9th bit PCM signal 104 as the cell assembling circuit 1
Output to 5 respectively.

【0007】セル化回路12では入力されたPCM信号
102とPCM信号103とで図2に示す第1のセル信
号を構成し、第1のセル信号105をバッファ13に出
力する。図2では第1のセル信号105はM個の8ビッ
トのPCM信号(b8が最上位ビットで以下b7、b
6、b5、b4、b3、b2、b1の8ビット)で構成
している。
In the cell assembling circuit 12, the input PCM signal 102 and PCM signal 103 form the first cell signal shown in FIG. 2, and the first cell signal 105 is output to the buffer 13. In FIG. 2, the first cell signal 105 is M 8-bit PCM signals (b8 is the most significant bit, and is hereinafter referred to as b7, b.
6 bits, b5, b4, b3, b2, b1).

【0008】一方、第2のセル化回路15では入力され
たPCM信号102とPCM信号104とで図2に示す
ように第2のセル信号と構成し、第2のセル信号107
をバッファ16に出力する。図2では第2のセル信号は
M個の8ビットのPCM信号(b8が最上位ビットで以
下b7、b6、b5、b4、b3、b2と最下位ビット
のb0の8ビット)で構成してる。
On the other hand, in the second cell conversion circuit 15, the input PCM signal 102 and PCM signal 104 constitute a second cell signal as shown in FIG.
Is output to the buffer 16. In FIG. 2, the second cell signal is composed of M 8-bit PCM signals (b8 is the most significant bit, and b7, b6, b5, b4, b3, b2 and 8 bits of the least significant bit are b0 below). .

【0009】バッファ13では入力された第1のセル信
号105を多重化するために2倍の速度の信号に変換し
第1のセル信号106として多重化回路14に出力す
る。一方、バッファ16では入力された第2のセル信号
を多重化するために2倍の速度の信号に変換し第2のセ
ル信号108として多重化回路14に出力する。多重化
回路14では、入力された第1のセル信号106と第2
のセル信号108とを多重化して多重化信号109とし
て出力し、多重化信号109は伝送路出力端子Bから伝
送路20に出力される。
The buffer 13 converts the input first cell signal 105 into a signal having a double speed for multiplexing, and outputs it as a first cell signal 106 to the multiplexing circuit 14. On the other hand, the buffer 16 converts the input second cell signal into a signal having a double speed for multiplexing and outputs it as the second cell signal 108 to the multiplexing circuit 14. In the multiplexing circuit 14, the input first cell signal 106 and the second cell signal 106
And the cell signal 108 is output as a multiplexed signal 109, and the multiplexed signal 109 is output from the transmission line output terminal B to the transmission line 20.

【0010】伝送路入力端子Cから入力された多重化信
号201は分離回路21に入力される。分離回路21で
は入力された多重化信号201を第1のセル信号202
と第2のセル203信号とに分離して、第1のセル信号
202はセル分解回路22に、第2のセル信号203セ
ル分解回路23にそれぞれ出力する。
The multiplexed signal 201 input from the transmission line input terminal C is input to the separation circuit 21. The demultiplexing circuit 21 converts the input multiplexed signal 201 into the first cell signal 202.
And the second cell 203 signal, and outputs the first cell signal 202 to the cell disassembly circuit 22 and the second cell signal 203 cell disassembly circuit 23, respectively.

【0011】セル分解回路22では入力された第1のセ
ル信号202を上位7ビットのPCM信号204と第8
ビットのPCM信号205に変換し選択回路24にどち
らも出力する。一方、セル分解回路23では入力された
第2のセル信号203を上位7ビットのPCM信号20
6と最下位の第9ビットのPCM信号207に変換し選
択回路24にどちらも出力する。
In the cell disassembly circuit 22, the input first cell signal 202 is combined with the PCM signal 204 of the higher 7 bits and the eighth PCM signal 204.
It is converted into a bit PCM signal 205 and both are output to the selection circuit 24. On the other hand, in the cell disassembly circuit 23, the input second cell signal 203 is transferred to the PCM signal 20 of the higher 7 bits.
6 and the least significant 9th bit PCM signal 207 and both are output to the selection circuit 24.

【0012】選択回路24では、第1のセル信号202
と第2のセル203がどちらもセル廃棄を受けなかった
場合にはPCM信号204(あるいは205どちらでも
良い)PCM信号205とPCM信号207とを選択し
てPCM信号208としてD/A変換器25に出力す
る。このときのPCM信号208は最上位ビットがb8
で、以下b7、b6、b5、b4、b3、b2、b1と
最下位ビットのb0の9ビットである。
In the selection circuit 24, the first cell signal 202
If neither the second cell 203 nor the second cell 203 receives the cell discard, the PCM signal 204 (or either 205 may be used), the PCM signal 205 and the PCM signal 207 are selected and the D / A converter 25 is used as the PCM signal 208. Output to. At this time, the most significant bit of the PCM signal 208 is b8.
In the following, 9 bits of b7, b6, b5, b4, b3, b2, b1 and b0 of the least significant bit.

【0013】第2のセル信号203だけがセル廃棄を受
けた場合には選択回路24は、PCM信号13とPCM
信号14とを選択して第9ビット目には“0”レベルを
挿入してPCM信号208としてD/A変換器205に
出力する。このときのPCM信号208は最上位ビット
がb8で、以下b7、b6、b5、b4、b3、b2、
b1と続き最下位ビットは“0”の9ビットである。
When only the second cell signal 203 has undergone cell discard, the selection circuit 24 selects the PCM signal 13 and the PCM signal.
The signal 14 is selected, a "0" level is inserted in the 9th bit, and the PCM signal 208 is output to the D / A converter 205. The most significant bit of the PCM signal 208 at this time is b8, and the following bits b7, b6, b5, b4, b3, b2,
Following b1, the least significant bit is 9 bits of "0".

【0014】第1のセル信号202だけがセル廃棄を受
けた場合に選択回路24は、PCM信号13を選択し、
第8ビット目には“0”レベルを、第9ビット目にも
“0”レベルを挿入してPCM信号208としてD/A
変換器25に出力する。このときのPCM信号208は
最上位ビットがb8で、以下b7、b6、b5、b4、
b3、b2と続き第8ビットと最下位ビットは“00”
の9ビットである。
When only the first cell signal 202 receives the cell discard, the selection circuit 24 selects the PCM signal 13,
A "0" level is inserted in the 8th bit and a "0" level is inserted in the 9th bit as well, so that the PCM signal 208 is D / A.
Output to the converter 25. The most significant bit of the PCM signal 208 at this time is b8, and the following bits b7, b6, b5, b4,
Continued with b3 and b2, the 8th bit and the least significant bit are "00"
Of 9 bits.

【0015】第1のセル信号202と第2のセル信号2
03がどちらもセル廃棄を受けた場合には選択回路20
4はPCM信号17としてb8からb0まで全て“0”
の信号をD/A変換器25に出力する。D/A変換器2
5では入力されたPCM信号208をD/A変換して出
力信号209を出力する。出力信号209は出力端子D
から出力される。
First cell signal 202 and second cell signal 2
If both 03 receive the cell discard, the selection circuit 20
4 is a PCM signal 17 and all "0" from b8 to b0
The signal of is output to the D / A converter 25. D / A converter 2
In 5, the input PCM signal 208 is D / A converted and an output signal 209 is output. Output signal 209 is output terminal D
Is output from.

【0016】このようにして、セル廃棄によりセルの欠
落が生じても2つのセルが同時に廃棄されない限り最低
でも7ビット精度のPCM信号が伝送でき、セル廃棄が
生じない通常時には9ビット精度でPCM信号が伝送で
きる。
In this manner, even if a cell is dropped due to cell discard, a PCM signal with a precision of at least 7 bits can be transmitted unless two cells are discarded at the same time, and a PCM signal with a precision of 9 bit is normally used when cell discard does not occur. The signal can be transmitted.

【0017】なお、本実施例では説明を簡単化するため
に、PCM符号化ビット数を9ビットにして第8ビット
を第1のセルに第9ビット(最下位ビット)を第2のセ
ルにそして上位7ビットを第1のセルと第2のセル両方
に割り当てているがこれらの数字を限定するものではな
い。
In this embodiment, in order to simplify the explanation, the number of PCM coded bits is set to 9 bits, the 8th bit is set to the first cell, and the 9th bit (least significant bit) is set to the second cell. The upper 7 bits are assigned to both the first cell and the second cell, but these numbers are not limited.

【0018】[0018]

【発明の効果】以上説明したように本発明は、重要度の
異るビットより構成された2つのセルを多重し伝送して
いるのでセル廃棄によりセルの欠落が生じても2つのセ
ルが同時に廃棄されない限り最低でも7ビット精度のP
CM信号が効率良くでき、またセル廃棄が生じない通常
時には9ビット精度でPCM信号が伝送できる。
As described above, according to the present invention, since two cells composed of bits of different importance are multiplexed and transmitted, even if cell loss occurs due to cell discard, the two cells are simultaneously transmitted. P with at least 7-bit precision unless discarded
The CM signal can be efficiently generated, and the PCM signal can be transmitted with 9-bit accuracy in the normal state where cell discard does not occur.

【0019】すなわち、単純な2度繰り返しを行うのと
殆ど同じ簡単な回路構成ですみ、かつセル廃棄補償のた
めに伝送効率を低下させることがないという効果があ
る。
That is, there is an effect that a simple circuit configuration almost the same as the one in which simple double repetition is performed and the transmission efficiency is not lowered due to cell discard compensation.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明における一実施例のブロック図で
ある。
FIG. 1 is a block diagram of an embodiment of the present invention.

【図2】図1におけるセルの構成図である。FIG. 2 is a configuration diagram of a cell in FIG.

【符号の説明】[Explanation of symbols]

A 入力端子 B 伝送路出力端子 C 伝送路入力端子 D 出力端子 11 A/D変換器 12 第1のセル化回路 13 バッファ 14 多重化回路 15 第2のセル化回路 16 バッファ 21 分離回路 22 セル分解回路 23 セル分解回路 24 選択回路 25 D/A変換器 A input terminal B transmission path output terminal C transmission path input terminal D output terminal 11 A / D converter 12 first cell assembly circuit 13 buffer 14 multiplexing circuit 15 second cell assembly circuit 16 buffer 21 separation circuit 22 cell disassembly Circuit 23 Cell disassembly circuit 24 Selection circuit 25 D / A converter

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H04Q 11/04 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H04Q 11/04

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 音声あるいは画像信号をPCM信号に符
号化し、前記PCM信号を複数個まとめてセルを構成し
伝送する装置において、時刻Tの入力信号をNビット
(Nは自然数)でPCM符号化しM個をまとめてセルを
構成する第一のセルと、前記第一のセルと同一時刻Tの
同一入力信号を(N+n)ビット(nは自然数,N〉
n)でPCM符号化を行い前記(N+n)ビットの内上
位(N−n)ビットと下位nビットをM個まとめてセル
を構成する第二のセルとの2個のセルにセル化をおこな
い前記第一のセルと前記第二のセルとを多重化し伝送す
ることを特徴とするセル化符号化方式。
1. A device for encoding a voice or image signal into a PCM signal, forming a plurality of the PCM signals to form a cell, and transmitting the cells, wherein the input signal at time T is PCM encoded with N bits (N is a natural number). The same input signal at the same time T as that of the first cell, which is formed by assembling M cells, and (N + n) bits (n is a natural number, N>
(n) performs PCM coding to perform cell formation into two cells, that is, a second cell that constitutes a cell by combining M pieces of upper (N−n) bits and lower n bits of the (N + n) bits. A cell coding system, wherein the first cell and the second cell are multiplexed and transmitted.
JP21250892A 1992-08-10 1992-08-10 Cellular coding method Expired - Lifetime JP2826423B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21250892A JP2826423B2 (en) 1992-08-10 1992-08-10 Cellular coding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21250892A JP2826423B2 (en) 1992-08-10 1992-08-10 Cellular coding method

Publications (2)

Publication Number Publication Date
JPH0662039A true JPH0662039A (en) 1994-03-04
JP2826423B2 JP2826423B2 (en) 1998-11-18

Family

ID=16623836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21250892A Expired - Lifetime JP2826423B2 (en) 1992-08-10 1992-08-10 Cellular coding method

Country Status (1)

Country Link
JP (1) JP2826423B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5725982A (en) * 1995-05-18 1998-03-10 Fuji Electric Co., Ltd. Photoconductor for electrophotography

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5725982A (en) * 1995-05-18 1998-03-10 Fuji Electric Co., Ltd. Photoconductor for electrophotography

Also Published As

Publication number Publication date
JP2826423B2 (en) 1998-11-18

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