JPS60170322A - Solid element relay circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a solid-state relay, and more particularly to a novel M
The present invention relates to a solid-state relay using an OSFET, a circuit to drive the MOSFET, and a photovoltage generator to generate the energy to operate the device.

(Prior Art and its Problems) A reed relay is a commonly used electromechanical relay. Such relays have a limited operating life, for example on the order of about 1 million cycles, and are also cumbersome and expensive. Therefore, efforts are being made to replace the solid-state relays with relays using solid-state elements. However, despite these efforts, no device has been produced that can compete with reed relays in terms of characteristics or economy.

Most commercially available solid-state relays use a thyristor (SCR or triac) as an output element.

However, Cyrisk is only an analogue of an ideal electromechanical switch. For example, a thyristor is at least 0.6v
It has an on-state voltage drop of , must reverse polarity to turn off, requires a half-cycle turn-off time, and has large holding current and large reverse leakage current.

Therefore, thyristors are generally unsatisfactory for applications such as general purpose device switching with reed switches. The use of anti-parallel connected thyristors is disclosed in US Pat. No. 4,296,331.

Solid state element relays using MOSFETs (not thyristors) form a solid state element analog with excellent conduction/blocking properties ideal for a pair of mechanical contacts. Bidirectional conduction MO8FETs can control alternating current and direct current circuits, Form a true contact point.

LED with appropriate input energy for switching transistors! Relays are also known which are irradiated by other radiation sources and form an output current which switches the elements. Such a relay is described in U.S. Pat. No. 4,227,
No. 098.

When the primary smear switching device is a power MO8FET, the input current from the photovoltage source must sufficiently charge the gate capacitance of the device to turn the device on. When using photovoltage generators, typically stacks of solar cell type devices, such generators must operate at high impedance to prevent dissipation of the battery output current from the MOSFET gate capacitance. The high impedance delays the discharge of the gate capacitance when the human radiation signal to the light generator is turned off and the light generator output voltage disappears. and U.S. Patent No. 4,227,098
In this circuit, the main power MO8FET remains on after the human input signal lasts the length of time required to discharge the gate capacitance of the power MO8FET into the high impedance circuit.

The circuit of U.S. Pat. No. 4,227,098 has a large dV
/dt charges the drain-gate capacitance of the power MO8FICT and turns on the relay without a human signal, making it susceptible to false firing due to the large dV/dt between the power MO3-FET terminals.

Circuits are also known that result in a faster discharge of this gate capacitance due to fast turn-off. However, such a circuit uses a second photovoltage source as shown in US Pat. No. 4,390,790. The second photovoltage source detects the presence or absence of an input signal and turns on the Depletion John MO8FET when the input illumination is turned off by turning off the human input signal. The gate capacitance of the MOSFET then discharges more quickly through the conducting depletion type MO8FRT to obtain a faster turn-off speed.

A charging voltage isolator operates as a voltage source and is used, for example, in a power metal oxide semiconductor field effect transistor (M
power switching devices such as OSFETs) can be turned on. The photovoltage generator used in such charging voltage isolators has a fairly high output, and responds immediately to the energization of the LED to generate a sufficiently large output from the photovoltage stack to control MOSFETs, bipolar transistors, etc. The gate power required to drive the gate of the device must be supplied.

Photovoltaic generators are known to consist of a group of dielectrically insulated photovoltaic generators spaced apart on the surface of an insulating support member and electrically connected together in series. This type of photovoltage generator is shown in the aforementioned US Pat. No. 4,227,098. Such devices are commercially available. Electrically insulated, laterally spaced and series-connected photovoltaic cells are used to collect the generated minority carriers at about 0.
0254 +u It has the disadvantage that only a small volume product with a thickness can be used and the life of the material is short. The electrodes that still connect the elements in series block the incident light. The output current of such devices is therefore limited. Moreover, the device has a fairly complex structure and is expensive to manufacture.

The photovoltage generator consists of a stack of wafer elements connected in series, each element having a PN junction oriented in the same forward conduction direction. These elements can be cut into small slabs,
This slab is illuminated from the edges to create an output voltage between the terminals connected to the two ends of the stack. A device of this type is disclosed in U.S. Patent No. 3,42, issued January 21, 1969, to J.
No. 2,527.

Stacks of edge-illuminated cells are inherently superior to electrically isolated cells. That is, the light penetrates deep into the slab and the carriers formed are collected even if they are formed, for example, 0.127 mm from the collection junction.

Moreover, in edge-illuminated slabs, the electrical contacts between adjacent units are outside the optical path.

Conventional edge-lit configurations used as light generators have limited output current power. And such devices are not good enough to quickly charge the MO8FET gate capacitance to reach the turn-on threshold voltage within a very short time. Typically, each wafer of such devices has a shallow P
It has an N-type layer with type diffusion and forms a collection junction. Also, fairly thick wafers are used and the final stack has such a large height that it is difficult to evenly illuminate it with a single LED located in the center of the stack.

SUMMARY OF THE INVENTION According to a first aspect of the present invention, a novel high voltage bidirectional output switch field effect transistor (BO-8FET) structure is provided, which comprises two lateral transistors having a common central source region. It uses field effect transistors integrated in the direction. This element is operated by the output of an optocoupler or charging voltage isolation circuit. The two outer drain regions of the device are connected to the central source region through respective enhancement-type channel regions, which channel regions
2 through a relatively low resistance conductive path between the two drain electrodes.
The design may be inverted to connect the two outer spaced drains. For example, a resistance path of less than about 2 Ω can be formed. This resistance is an acceptable value for most applications using reed relays.

The novel junction configuration uses a reduced surface electric field with a novel configuration. According to the invention, two channel regions are arranged symmetrically between two depletion regions. A common source connection connects the separated drain regions. The channel region is a P region disposed within an implanted N(-) region formed on a P(-) body. Control circuitry is integrated into the BO3FET chip. In some embodiments, the diode and PNP transistor are N
(=) layer, in this case the diode is formed in the P-type well, while the PNP) transistor is formed in the N (-)
Use the region as its base region. The two main drain regions are isolated from each other and by deep P-isolated diffusions with N(-) regions for PNP transistors and diodes.

The voltage across the drain region when the device is off is on the order of 100 to 1000 (V), making it possible to fabricate a relay that can replace common glue-drill applications. This fairly high voltage is possible because the high output voltage, whether the relay is controlling AC or DC voltage, is blocked by the lateral N(-) drift region and not applied to the gate oxide. Therefore, even at high output voltages of the device, the gate can be made very sensitive using a very thin gate oxide, and the device can be turned on by a relatively low input terminal with a relatively small current source. can do. As a result, the device is turned on by the output of an optical coupler or optical voltage starter, which will be described later. The semiconductor switching device or BO3FET is therefore a high voltage, relatively low resistance device with very sensitive gate turn-on characteristics.

The device of the invention can be used in conventional applications, for example as a direct replacement for existing thyristors or triacs. This device can still be applied for use as a power switching element in solid state relays with other relay elements integrated in the same chip together with the power switching element.

The novel solid-state relay circuit also uses a single photovoltage generator output to drive the BO3FET into conduction with a circuit that has a high manual turn-on impedance and photovoltage start-up to provide a fast turn-off time. This limits device size and low input turn-off impedance requirements.

The novel circuit ensures that the gate voltage always immediately follows the single charge voltage generator output. There are two conditions that cause the power MOSFET gate voltage to deviate from the expected charging voltage generator output. These are the charge accumulated on the gate-source capacitance C and the drain-gate capacitance CD-G under high dv/dt.
This is the charge that accidentally charges the gate with the current flowing through it. When the gate of the power MO8FET is directly connected to the photovoltage generator, the gate signal is properly given from the output of the photogenerator, and the parasitic capacitance C is still the result of charging one of the 5S CD-G. It is known that it is impossible to tell the difference.

Embodiment According to one embodiment of the invention, a sensing impedance is connected between the light generator and the gate of the power MO8FET, which impedance controls an auxiliary circuit to generate a false M
Used to quickly erase O3FET gate voltage. In a preferred embodiment, the sensing impedance is a diode, a Zener diode, a MOSFE
Other elements such as T or resistors can also be used. The use of a separate sensing impedance allows the auxiliary circuit to be controlled to produce a rapid discharge of 1 cm88 volume when the human power signal is turned off without the use of a second light generator array.

In a preferred embodiment of the invention, the charging circuit from the photovoltage generator to the gate-source circuit of the power MO8FET is connected with a diode, which allows current to flow from the photovoltage source to the gate capacitor. It also works as a detection impedance.

A switching transistor circuit is controlled from a human control terminal connected in parallel with the gate capacitance of the power MOSFET element and connected to the positive output terminal of the photovoltage source, and the switching transistor is biased when the photovoltage source output voltage begins to dissipate. . The relay is therefore switched on as soon as sufficient current is generated from the photovoltage source to charge the gate capacitance of the power MO8FET to the required value. However, when the circuit is turned off and the output voltage of the photovoltage source is lower than a predetermined value, the switching transistor turns on and forms a short circuit across both gate capacitances of the power MO5FET and across the photovoltage source. Gate capacity C□8
8 and the output of the photovoltage source are short-circuited by a switching transistor. Therefore, the power MO8-IT is quickly turned off.

A still novel AC clamp circuit is also provided, which includes another switching transistor connected across the gate-source electrodes of the power MO3FET. A resistor-capacitance differentiator circuit is also provided, and when clV/clt exceeds a predetermined value, it turns on the second switching transistor in order to divert the mirror current through the gate-drain parasitic capacitance C of the power MO8FET. . This AC circuit is connected between the above-mentioned sensing impedance and the power MO8FET gate electrode.

The novel solid state device control circuit shown as integrated in a single chip with the BO3 FET can also be used to drive conventional FET devices.

The novel solid state relay of the present invention has many advantages over relays existing on the market, including electromechanical reed relays. And the novel circuit of the present invention can switch AC and DC voltages and has very low leakage current in the off state, which is characteristic of MO8FET type devices. It also has a very low thermal offset voltage and produces no electromechanical interference emissions when closed. It also has a fully resistive output voltage with minimal holding current in the on state. It is capable of sending out analog signals accurately.

Moreover, it requires only a small power of 1 to 2 mW (mW, ) to remain in the on state.Furthermore, the device turns on and off within a few microseconds, much less that a reed relay or a regular solid-state relay would require to operate. The load current capacity of the device of the present invention is limited only by chip size and construction and is only 500 to 100,100 milliseconds to meet the load current rating of a conventional reed relay.
0 (on the order of 0), and it has a very long operating life of more than 1 trillion operations. The bottle is housed in some sort of pancage, such as a DIP container.

A novel photovoltage stack is provided which has significantly higher output voltages and currents due to the reduced number of wafers in the stack to produce a relatively low stack height. According to one embodiment of the present invention, a high resistance P-type body is used. A thin layer of N soil on this body forms a collection junction in the body.

By using a P-type body with a thin N layer forming a collection junction, the minority carriers in the P-type body are electrons. Such carriers have higher mobility than holes, which are the minority carriers in normal N-type bodies.

Preferably, the body material is formed from a float zone pulled crystal ingot with a resistivity greater than about 5 ohms, e.g. 30 to 50 ohms. 1 to 5 [Ω・
Low-resistivity materials such as those manufactured by TSUJI can also be used.

Although the use of low resistivity materials is known to produce high output voltages, the application of the present invention allows the output voltage to be reduced due to the large short circuit currents obtained through the use of high resistivity materials.

Another feature of the invention is that each semiconductor wafer should be as thin as possible without breaking during handling. The novel process of the present invention allows the use of such thin wafers since wafer grinding, which stresses the stack, is the final step before the alloying process. In fact, the wafer is made thinner than the diffusion length of the carriers formed in the wafer. This can be done because a new P layer is spaced over the P(-) body which acts as a reflective layer to reflect the minority carriers already collected by the PN junction.

Another feature of the invention is that the very high conductivity old layer is P(
-) used on one side of the body. The use of a very highly doped N-soil layer allows the use of aluminum-silicon low-melt cage aluminum to alloy the stack together without converting the N-soil layer into a P-shaded region. Preferably, the N0 diffusion is performed with a Linnean blunt. The phosphorus acts as a binder for metal ions within the wafer, further increasing the lifetime of the material.

The above-mentioned reflective P soil layer and N soil layer are PoCt3 and B
Preferably, it is formed by well-known well-displaced diffusion processes, such as those using N predeposition.

As mentioned above, the stack is connected by bonding between adjacent wafers by thin aluminum or aluminum low melt cage alloys. However, metal-infused epoxies or polyamides may be used to connect the stack together if desired.

This allows the use of shallower junctions and reduces stack height.

Silicon monocrystalline wafer endplates are also used in the stack to provide a long enough standoff distance to provide sawing allowance without compromising the junction and conductive epoxy 7.
This allows the wires to be attached to spaced conductors at the ends of the stack without shorting the junctions of the wire.

Their independent outputs when processed as described above are sufficiently high and large enough to quickly turn on a power MO8FET in a stack of less than about 20 elements, preferably about 10 elements. Output current and voltage can be formed.

FIG. 1 shows one embodiment of a circuit that may be used to fabricate a solid state relay using a BO3 FET and the control circuit of the present invention. An opto-isolator or opto-coupler is shown within the closed dashed line 20 in FIG. Charging voltage isolator 20 is connected to relay input terminals 22 and 23.
D21 as well as a stack of photovoltage diodes 19 which form an output current when illuminated by LED21. LF, D214 or its variations are terminals 22.23
The alternating current to still be excited by the direct current. In the illustrated embodiment, a DC input source is connected to terminals 22 and 23K to turn LED 21 on and off. For example, the input circuit may be connected to LED2 to excite the LED.
] is configured to apply a current of approximately 10 (mA) to the current.

The remainder of the circuit of FIG. 1 includes a solid state relay element for turning off and turning off the novel FET 24 having output terminals 25 and 26.

Although element 24 is a high voltage element, it has bidirectional conduction characteristics, so output terminals 25 and 26 are connected to an AC or DC circuit. BO3FET 24 is then connected to two series connected high voltage MO8FIETs 30 and 31 shown in FIG. 2 as connected between terminals 25 and 26.
is equivalent to the circuit of Regular MOSFET30 and 3
1 is turned on and off by a gate-to-substrate control voltage applied between terminals 32 and 33.

The structure and method of manufacturing the BO3FET 24 will be detailed later.

The control elements of FIG. 1 for BO3FET 24 include a diode 35, a PNP) runster 36, and a human resistor 37. Resistor 37 has a very high impedance;
The resistance is about 5 (MΩ).

When the solid state element circuit shown in FIG. 1 is used as described below, its characteristics are similar to those of ordinary solid state element relays and reed relays that are currently in widespread use. For example, the circuit characteristics are terminal 2
5.400 at a maximum load current of about 200 (mA) between 26 and 400
(V). terminals 25 and 2
The maximum resistance between 6 and 6 is 25 [Ω]. The input capacitance of the element is about 60 to 80 (pF), and the output capacitance is about 40 (pF).
pF). The capacitance between the human head and the mouth is about 2 (pF). The turn-on time of a circuit with a resistance of 5 (MΩ) is about 50 microseconds at a drive current of 10 (mA), and the turn-off time is about 90 microseconds. Detection sensitivity can be increased by increasing the input impedance. It is also possible to reduce human power impedance and increase turn-off time.

The characteristics of charging voltage isolator 20 are shown exaggerated in FIG. As shown in FIG. 3, when using a human input impedance of about 5 (MΩ), the output voltage of the stack 19 increases to about 3 [■] in about 4 microseconds after the LED 21 is turned on.
rises to. The driving current of the LED to form the characteristics shown in FIG. 3 is about 10 (mA). The on-time can be reduced by using a higher human impedance 37 or increasing the LED drive current. The output voltage of stack 19 immediately begins to decay due to LED 21 turning off. This decay normally takes a long time, as shown by the broken line in FIG. It is a new diode 35 and P
In the conventional circuit that does not use the NP transistor 36, BO3F
This is because the gate capacitance of ET24 discharges slowly.

However, in the circuit of the present invention, the output voltage of the stack 19 is MO
When the voltage drops to about 0.6 (V), which is lower than the 8FET gate voltage, the PNP transistor 36 begins to conduct.

This changes the input impedance of the circuit to transistor 3
Decreased by a gain of 6. And as shown in Figure 3, for quick turn-on, the stack voltage and BO3FET 24
The gate voltage disappears rapidly, resulting in a fairly fast turn-off.

It should be noted that diode 35 forms a low impedance charging path to the gate circuit of FiBO8FET 24, allowing the full power impedance of resistor 37 to turn on the device quickly. The diode 35 is a sensing impedance and may be replaced with another impedance.

(motion) The circuit of FIG. 1 operates as follows.

To turn on the relay, LED 21 is energized and a charging current flows from stack 19. This charging current flows through the diode 35 and charges the gate capacitance of the BO3FET 24. 08FE becomes new when the threshold voltage of BO3FET24 gate capacitance exceeds (approximately 1.0 (V))
T turns on and is about 2.0 to 2. (V) to fully turn on. This forms a conductive path between terminals 25 and 260. Even a small opto-isolator 19 can turn on the BO3FET 24 if the current and voltage requirements on the BO3FET 24 are small.

Since the current of the photovoltage stack 19 is applied to the high input impedance circuit defined by the resistor 37, a very fast response is obtained. Under normal circumstances, this same high input impedance would prevent rapid turn-off of the device since the gate capacitance would need to be discharged through the same impedance to turn off the BO3-FET. However, the present invention improves the turn-on speed by as much as 20:1 with very high performance for example static induction transistors with high gain characteristics. As described below, BO3FET with PNP) transistor
24 configurations can be substituted. It is particularly noteworthy that transistor 36 is not used to constrain charging voltage isolator 2°, but rather to follow its output voltage. Once the output voltage of stack 19 drops to about 0.6 (V) i below the gate voltage, transistor 36 turns on. The effective human power impedance of this circuit is the resistance of resistor 37 divided by the beta of transistor 36, which is approximately 400. Therefore, the effective input circuit is a fairly low impedance circuit, which is BO
The gate capacitance of the 3FET 24 is discharged fairly quickly and turned off quickly.

The current control characteristics of the circuit of FIG. 1 are shown in FIG.

In FIG. 4, BO3FET 24 turns on when the gate voltage, which is the voltage at the positive output terminal of stack 19 minus the forward drop of diode 35, reaches approximately 1 volt. - When it reaches 2 [■], the element is almost completely turned on, and the load current at that time is, for example, 100100
(reaches BO3FET from blocking state to fully on state
The actual voltage required to switch 24 is less than about 3 volts and the device can operate in a TTL circuit.

5-11 show a single chip of silicon having a diode 35, a transistor 36 and a resistor 37. FIGS. In one embodiment of the present invention, the chip has a thickness of about 0.381 mm for the above-mentioned rating for the entire relay;
It has a length and width of about 1.803 [dragon] to 2.337 (ii). Of course the dimensions can be changed.

The surface of the chip is shown in plan view in FIG.
The metal pattern for the source and drain of O3FET 24 is shown. Of course, the chip of FIG. 5 is one of many chips formed simultaneously on a fairly large wafer.

According to FIGS. 5, 6 and 8, the BO3 FET device 24 consists of two main drain electrodes 50 and 51, shown cross-hunted for convenience. Enlarged pad areas 52 and 53 are used to make electrical connections to seat trains 50 and 51 by conventional wire bonding techniques.

Drains 50 and 51 are connected to terminals 25 and 26 in FIG.
8, each consisting of a plurality of spaced apart elongate fingers, such as drain fingers 54 and 55, shown in enlarged detail in FIG. The configuration of FIG. 5 has exaggerated details and the actual device would use about 15 fingers for the condensed drain region.

A plurality of elongate source contacts, including source contacts 56 and 57, are disposed laterally across the chip and are symmetrically disposed between spaced apart pairs of elongate drain fingers. The individual source fingers are electrically connected to each other by a vertical center conductor 65 and a surrounding boundary 66. The electrical path is therefore e.g. from drain 50 to drain 51 and between fingers 54 and 5 connected in parallel.
5 to source finger 56 and source finger 5
6 to the right to drain fingers 58 and 59. All drain and source metals are aluminum. An electrode connected to the source boundary 66 is provided on the bottom surface of the chip.

Substrate connection pads 60 are provided on the surface of the device of FIG.

The above-described novel interlocking comb-shaped pattern connects the drain 50. This allows high voltages to be used between the two. It should be noted that there are parallel conductive paths for each adjacent pair of drain and source electrodes in FIG. A gate band 61 is provided on the surface of the device of FIG. 5 to provide a simple bond connection to the gate circuit of the device as described below. Furthermore, the substrate pad 60 in FIG.
corresponds to the substrate terminal of the BO3FET 24 in FIG. 1 connected to the negative output terminal of the stack 19, and the gate band 6
1 corresponds to the anode of the diode 35 connected to the positive output terminal of the stack 19.

As shown in FIG. 5, the chip area shown within the dashed area B is reserved for the formation of a diode 35 and a transistor 36, which are schematically illustrated as described below. The surface of the chip supports a resistor 37 around its outer edge in a manner not shown in FIG. 5 but described below.

The junction pattern used in the present invention is shown in FIGS. 6 and 8 in conjunction with the junction pattern in area A of FIG. This pattern is used over the entire surface of the device of FIG.

6 and 8, the body of the chip 70 has a lightly doped P (-) region, as described above, at about 0.
．． 381 (m) thick and has a resistivity of, for example, 30 [Ω·α]. The main P(-) region is not in series with the main current path of the device but defines the breakdown voltage of the BO3FET. A lightly doped N-type drift region is then formed on top of the P(-) body region. The N(-) region 71, often called the depletion region or drift region, preferably has a thickness of 5 [μm].
It is formed using conventional epitaxial growth techniques. However, layer 71 is preferably formed by ion implantation. The N(-) drift region 71 must be properly doped to obtain the correct depletion in the lateral direction during operation of the device to ensure that the electric field at the surface of the device is evenly distributed over the surface. Preferably, the N(-) region 71 is about 1
It is formed by implanting phosphorus ions at a dose of 1012 C ions/al. As mentioned above, about 5 [μ
In order to diffuse the phosphorus ions to a depth of 1.2 m
An implantation process lasting approximately 18 hours at 00 ('C) follows.

A P-middle region 72 is then formed having strips disposed below each of the source strips of FIG. The lateral sides of a strip, such as strip 72, are more lightly doped than the lateral interior. This is because these regions define the channels of the MOSFETs that will be formed as described below.

A field oxide is formed on the surface of area 7e to form a strip such as strip 72 in FIGS. is opened in the field oxide film. Ion implantation is then carried out using, for example, boron ions at a fairly heavy dose of, for example, 3 x 10" [ions/d].
〔μm〕 4. Injection that diffuses deeply is 1 or 2.
00 (°C) for about 100 minutes.

Subsequently, a masking oxide film is grown to approximately s,ooo+:X]. A second mask is then applied to the oxide surface;
Windows are etched over the regions to receive gate and N+ source strips 82 and 83, which will be described below.

A gate oxide layer is then deposited on the exposed silicon surface with a thickness of approximately 700 mm.
It grows to the thickness of (A). Polysilicon is then deposited over the entire surface to a thickness of approximately s, ooo (X).

A third mask is then applied to the polysilicon surface, and a desired polysilicon gate pattern is formed on the device surface by photoetching, and the polysilicon exposed by the mask is etched down to the gate oxide film. The exposed gate oxide is also etched and given a fairly low ion dose, e.g. 3X10'3 [ions/d], to make it more lightly doped P shadow regions 72a and 72b on either side of the P+ strip 720 and below the gate oxide. form. The lightly doped region is then diffused to 2.5-3 [μm] at about 1.125 ('C) for 120 minutes to bring the mask oxide film to about 1.500 (X). This mask oxide film is used during the formation of control circuit elements and is lightly doped P
The region is diffused to prevent the later formation of N0 regions in one-way windows. The use of lightly doped P shadow regions 72a and 72b reduces the threshold voltage of the BOSFET, as discussed below.

A fourth masking and photolithography operation is performed to open the drain region 80 and the overlying strips in the field oxide. A fifth masking and photoetching is also performed to open strips in the 1,500(X) mask oxide over source regions 82 and 83 and over selected areas of the control circuitry. Then, by diffusion, the N0 area 80, 81.8
2 and 83 are formed.

Regions 80 and 81 are N+ strips located below drain contact fingers 54 and 55.

However, in general, N0 regions 80 and 81 are part of a comb-like pattern having the shape of drain electrode 54 in FIG. Needless to say, a similar pattern is formed under the drain electrode 51 at the same time. N+ regions 82 and 83 in FIG. 8 are thin strips located below source fingers 56. In FIG. After this, a captured oxide film is applied to the element surface.
A masking operation opens windows for the necessary metals, including the source and drain contacts. North contact finger 56 connects N+ regions 82 and 83 to the center of P+ region 72.

Obviously other similar strips are disposed below other source fingers and formed in corresponding P-type regions such as region 72. N+ strips 82 and 83 define channel regions 72a and 72b, which regions may be inverted to form an N-type channel for enhancement type MO8FET operation.

Elongated polysilicon gates, shown as polysilicon gates 90 and 91 in FIG. 8, are disposed over channel regions 72a and 72b, respectively. Cha, i, Lua 2
The thickness of the oxide under the active polysilicon gate region above a, 72b is very thin, approximately 700 Å, substantially lowering the threshold voltage of the device. polysilicon gate 90
and 91 are suitably connected to gate pad 61 of FIG. 5 and covered by respective layers 100 and 101 of a silicon or glass insulating layer that insulates conductive polysilicon gates 90 and 91 from source metal strip 56.

It will be seen from the above that the novel process is a DMOS process in which the source and channel regions are self-aligned with the polysilicon gate. In fact, if the initial N(-) region 7
This is a heavy diffusion process that also includes 1.

As shown in FIG. 8a, polysilicon layer 91 is
Wrap around the end of the drain region like so.

According to the present invention, the gate oxide over the channel and drain regions, such as region 72b, is formed by polysilicon gate 91.
ends slightly before the point where the curve begins. This prevents the gate oxide film from being exposed to thermal carriers during avalanche breakdown. This avalanche breakdown occurs in this region of the junction curve. This avoids damage to the gate oxide film.

FIG. 8 shows a cross section of the device extending across the entire surface of the element and including, for example, 1.
There is also a conventional field oxide layer with a thickness of 2 μm. Using conventional processing techniques, the oxide layer is suitably opened and a drain electrode having drain fingers 54 and 55 and north electrode strip 56 is deposited as shown.

a single metal sheet is formed on the surface of the device to form contacts to the chip surface area exposed to the mask oxide window;
This metal is then masked, for example in FIGS. 5 and 8.
The final desired turns are cut as shown in the figure.

The field effect transistor thus obtained has a drain 5
A novel lateral bidirectional conducting field effect transistor (BO3FET
). When a suitably low voltage is applied to polysilicon gates 90 and 91 from a small current source, channels 72a and 72b over the entire area of the chip of FIG. 5 are inverted, and current flows from drain 50 through the inverted channel region. It flows to a source finger, such as source finger 56. The current then flows from the source finger 56 on the other half of the device back out through the inverted channel to the drain 51 finger! l1 Form a conductive path between the two drain electrodes. This device is a high voltage device since there is a very small voltage difference between the polysilicon gates 90-91 and a source finger, such as finger 56, which is fixed at the substrate reference voltage. Therefore, the drain electrode 50.51
Even if a very high voltage appears between them, only a few [volts] is generated in the thin oxide film on the channel regions 72a and 72b.

Therefore, the novel device of the present invention has general application as an AC or DC switching power MO8FET. Of course, the current rating of the device is limited only by the effective width of channels 72a and 72b, dimensions shown in FIG.
In the case of an 803xi x 2.311 mm element, its current rating is approximately 200 (mA). The threshold voltage of the device is very low due to the thin gate oxide film, 2 and 2.5 (V).
The complete turn-on generated between the two voltages is about 1 [V]. The on-resistance of the device is also quite low, for example less than about 25 [Ω].

The spacing between drain fingers, such as drain fingers 54 and 55 in the illustrated embodiment, is 0.20 between
3(p). The width of P ten area 720 is approximately 0.0254 [
It is [related]. In this type of configuration, the lateral electric field between either the drain region, such as region 81 or 80, and the cell region 720 is very well distributed on the surface of the wafer immediately below the field oxide film 93. ing. That is, the conductive potential along the surface is evenly distributed. Therefore, local breakdown due to local electric fields at the surface is avoided.

The new 08FET is in area B in Figure 5 in this regard.
It is very well constructed with a diode 35 and a PNP) transistor 36 integrated in it. The junction patterns used in area B are shown in Figures 7 and 9.
It is shown in detail in the figure. 7 and 9, N(-) region 71 has an enlarged P+ diffusion 110 formed at the same time that P+ diffusion 72 is formed. In FIG. 7, the P+ diffusion 72 is the same as that below the source strip 56 of FIG. 8, but below the shorter source strips on either side of region B of FIG. The N+ strips 82 and 83 are different from the N+ strips 82 and 83. When P-type diffusions 72a and 72b are formed, P-type diffusions 111 and 112 are also performed within the N(-) frame exposed within P-ten rectangular ring 110 of FIG. N+ contact region 113 and N+ region 114 also have N+ regions 82 and 8
Formed when 3 is formed.

The circuit and junction nodes shown in FIG. 7 are shown in FIG. Diode 35 is then defined by a PN junction formed between P region 111 and N+ region 114. N+ region 114 is electrically connected to a polysilicon gate lattice which is connected to gate pad 61 in FIG. The anode of diode 35 is electrically connected to N+ region 113 and then to the positive terminal of the input circuit of the relay.

Very high gain PNP) transistor 36 is in P region 11
2. It is formed of an N(-) main body 71 and a P(-) main body 70. The collector electrode is connected via a P+ ring 110 connected to the P(-) body as shown. Region 110 is then electrically connected to the substrate electrode and to the negative terminal of the optical stack input. PNP)
It should be noted that the formation of the transistor is ideally suited to the processes used to form BOSFET devices, resulting in the formation of very high gain transistors.

Resistor 37 of FIG. 1 may be provided on the chip in any desired manner. Preferably, the resistor is the fifth resistor as shown in FIG.
The resistor terminals surround the outer edge of the chip shown in the figure and have a length of, for example, 2.54 to 5.08 and have a resistance of 1 to 5. It is formed under gate pad 61 in a P slave region 130 that is formed along with the formation of P+ region 72 .

FIG. 10 shows within the dashed line 131 the plane of the N(-) IJ tube region 132, which extends around the chip periphery and has ends spaced apart by the P+ region 130 as shown in FIG. has a department. The strip 132 is, for example, 1
It has a width of 5 [μm]. N ten end pads 133 and 1 are connected to appropriate terminals 135 and 136, respectively (FIG. 11), which are connected to appropriate potential points within the chip.
34 are provided. N+ regions 133 and 134 relative to elbow region 130 define an energy diode 140 (FIG. 11) with a breakdown voltage of 10-12 (V).

The novel 08FET structure of the present invention can also be constructed in other ways. Figures 12 and 13 show a second embodiment of a junction pattern that may be used to construct a BO3FET. The junction patterns in FIGS. 12 and 13 are to be compared with those in FIG. 8, and like symbols indicate the same elements. The basic difference between the configuration of FIG. 8 and the configurations of FIGS. 12 and 13 is that the drains D1 and D
2 is whether it is a perfect interlocking comb tooth shape. P+ in Figure 8
Region 72 is formed as two independent laterally spaced sections 150 and 151 in FIG. . N+ regions 160 and 161 are then formed in P shadow regions 150 and 151, and two N+ regions 160 and 161 are formed in each of P regions 150 and 151 to cooperate with polysilicon gate pairs 162-163 and 164-165. Define channels. Gates 162 and 163 and 164-' 165 are periodically connected to gate metal strips 170 and 171, respectively.

FIG. 14 shows a circuit that can be incorporated into the BOSFET chip described above, which is characterized by increased turn-off speed and protection against unexpected dV/clt turn-on over the circuit of FIG. Elements similar to those in FIG. 1 are given similar reference numerals in FIG.

The high-speed turn-off circuit in FIG.
Consists of 2. These elements form a regenerative turn-off circuit that ensures that the voltage on the gate-to-substrate parasitic capacitance C1 follows, and in fact pulls down, the voltage on the star SS block 19 when the LED 21 is turned off. When the stack voltage is υ lower than the gate voltage of element 24, approximately O,S
(V), P-channel MOSFET 201 turns on and C discharges through the base-eminter circuit of MOSFET 201 and transistor 200. This turns on the transistor 200 and discharges the stack 19. During the discharge, MO3F
Turn on ET201. Element 35, 200, 2
01 and 202 can be easily integrated into a BO3FET chip.

The switch-off speed of the switching circuit in FIG. 14 is 4
equal to the switching speed of the circuit of FIG. 1 with a resistor 37 of 70 (KΩ).The circuit of FIG. .This improves the detection sensitivity, turn-on speed and turn-off speed of the circuit.

FIG. 14 shows a dynamic AC clamp circuit for dV/dt suppression. The distributed parasitic capacitance CD-G between the drain and gate is such that if there is a sufficiently large dV/dt between terminals 25 and 26, a sufficiently large pulse current will flow, and when there is no human input signal at terminals 22 and 23. But MO3FgT24 is turned on.

This suppression circuit consists of resistor 210, capacitor 211 and N
PN) transistor 212, all of these elements are integrated into a power MO3FET chip. The resistor-capacitance voltage divider turns on the transistor 212 when dV/dt between the terminals 25 and 26 exceeds a predetermined value, thereby increasing the capacitance C.
Ground the connection point between 88 and CD-G.

In the circuit of FIG. 14, the resistances 202 and 210 are each 1 (MΩ), and the capacitor 211 is 20 (MΩ).
pF).

15 and 16, the starting wafers from which the light generating wafers used in the stack are made are shown. The dimensions of the wafer in FIGS. 15 and 16 and subsequent figures are exaggerated out of proportion for clarity. Figure 15
The wafer is a high resistivity P-type material, and the wafer is as thin as possible but strong enough not to break if handled carefully. For example, the wafers of FIGS. 15 and 16 were cut from ingots formed by float zone crystal growth and had a resistivity of approximately 50 Ω·steel.
It is the shape. This is generally the highest practical value, but it is 1 to 5 [
It is also possible to use values that are used in ordinary P-type solar cells, such as .OMEGA..OMEGA. The use of high resistivity materials provides greater short circuit current while reducing the output voltage of each cell ultimately fabricated from the wafer.

The wafers used were about 50.8 i+s+ in diameter and about 0.19 wafers thick, which is the thinnest that can be handled in an industrial process without undue damage. Wow...
Although the diameter can be set to 76.2 m, for example, the wafer thickness must be increased accordingly, to 0.23111 m, for example.

The top and bottom surfaces of wafer 320 in FIGS. 15 and 16 are oxidized with grown oxide layers 321 and 322 approximately 0.4 μm thick. A conventional photoresist mask layer 323 is then formed over the oxide layer 322 of FIG. The wafer is typically etched away with the unmasked oxide layer, while leaving the oxide layer 321 in place, as shown in FIG.

A carrier containing boron is then deposited on at least the bottom, unexposed surface of the wafer in FIG. 18, and the boron is then introduced into the wafer to form the P+ region 330 shown in FIG. 19. This treatment was carried out at 1,250 (℃).
0 hours and boron diffuses to a depth of 0.0254 degrees.
Do it until you do. The treatment shown in Figure 19 has a surface resistivity of approximately 50 [
Ω/mouth] is reached.

Oxide layer 321 acts as a mask during boron deposition and subsequent processing. Also, during the boron treatment, an oxide layer approximately 1 μm thick is grown on the bottom surface of the wafer in FIG.

After this, as shown in FIG.
2 is applied to the surface of oxide layer 3310 and the unmasked oxide layer 321 is removed from the top surface of the wafer in FIG.

A very heavy N+ deposition and implantation process using a poat3 source is then performed to form N+ regions 333 on the unmasked surfaces. To diffuse the N+ region 333 onto the top surface of the wafer/-320, a phosphorus material was deposited on the wafer for 2 hours at 1.12 s (°C) until the sheet resistance was approximately 0.8. Ru. After this, the impurity is about 1.20
(0C°C) for 10 hours. This is N0 area 333
This is done to a depth of approximately 0.0254 m. This introduction is stopped until the resistivity of the N soil surface of the wafer reaches approximately 0.5 [Ω/hole]. The surface resistivity is extremely high at 0.5 [Ω/mouth], and the surface resistivity is approximately I x 10”.
It is obtained when it is larger than phosphorus (ion/cd). In fact, the phosphorus ion concentration is the solid solubility limit2
x 10” (ions/cd)t.

This new N0 diffusion extends the lifetime of the P(-) region 320. This is because phosphorus ions act as getters for metal ions in the silicon body. Moreover, the step of forming the very heavily doped N+ region 333 is the final step in forming the junction pattern, and aluminum foil or aluminum low melting point material is used as a means of alloying a large number of wafers into a stack. is allowed to be used. That is, aluminum does not invert the N soil layer to P-type conductivity. Thereafter, as shown in FIG. 22, all oxides are removed from the wafer of FIG. 21 by use of a 6:1 hydroxide fluorine compound etch material.

The next step in the process is the formation of a stack as shown in FIG.
0 wafers are stacked with a (10254 mm thick foil) in between. The number of wafers can vary. The foil 343 is an aluminum silicon low melting point material of 88% aluminum and 12% silicon by weight. End plates 344 and 345 of pure aluminum with a thickness of 203 mm are superimposed on each end of the stack.If plates 344 and 345 are aluminum silicon low melting point material;
The foil immediately adjacent to can be omitted.

Additionally, plates 344 and 345 may be made of silicon.

The entire stack is then placed in a suitable device which applies light pressure in a suitable manner to alloy the stack together. For example, the stack is placed in a belt furnace with nitrogen gas scrubbing. The furnace should have a peak time of about 5oo('c) for 5 minutes with an open pass time of about 45 minutes. Ordinary alloy furnaces can also be used.

After the stack is alloyed, the stack is cut into slabs of desired dimensions. This slab is formed by cutting the stack in a direction parallel to its axis. FIG. 24 shows a slab formed from the stack of FIG. 23, which is cut by a suitable conventional single or multi-blade saw. The slab in Figure 24 is approximately 0.508 (
+i) It has dimensions of width and length of 1.524 (ms). The height of the slab is determined by the total height of the 10 sheets of glue and bonding foil and is approximately 2.54 (m). The width and length as well as the number of wedges per stack can vary. Therefore 1.02CIII) X O,38(ma
) slab elements can also be used. The height of 2,54 (drunk) formed by 10 wafers is small and the distance from the illumination LED located at 0.76 [+x] from the center of the slab is very small from any wafer element on the slab. It is not something that is different and spaced apart.

The photovoltage slab of FIG. 24 is incorporated into the photovoltage slab shown in FIGS. 25 and 26. 25 and 26, top and bottom electrodes 34, respectively.
A support base 350 is shown suitably supporting slab 351 of FIG. 24 with electrodes 352 and 353 extending from 5 and 344. The conventional LED 360 with electrodes 361 and 362 is preferably an infrared output LED.
and placed on the support base 350 and approximately centered on the slab, but at a sufficient distance, e.g. 0.76 mm: ]
to form the desired insulation structure (3,750 (V)) between the LED electrode and the stack electrode. In Figures 25 and 26, the height of the container is approximately 1
, 524 (+ni), and the diameter is approximately 1,52
It is slightly larger than 4 [mm], and the diameter of the top of the container is approximately 3 mm.
, 175 (battle).

This assembly is then covered with a transparent insulating silicone body 370 that is transparent to LED illumination. silicone body 3
70 is covered with a reflective coating 371. Preferably coating 3
71 is made of silicone having the same composition as the main body 370, but includes a white reflective material such as titanium dioxide powder. By using this powdered silicone, the coating 371 is firmly adhered to the silicone body 370.

FIG. 27 shows a detail of the stack of FIGS. 24, 25, and 26 and shows how damage from the cutting saw is created by end plates 344 and 345. In particular, the plates have rough beveled and rough-formed edges, such as edges 401 and 402 on plate 344 and edges 403 and 404 on plate 345. Board 34
4 and 345 are thick enough to accommodate any saw damage that does not extend into the wafer adjacent to the end plate into the junction.

Plates 344 and 345 also have sufficient thickness or stand-off to receive conductive epoxy masses 410 and 411. This standoff is used to secure the stack to the ends of spaced apart leadframe elements or other electrodes 412 and 413 without risk of shorting between active junctions adjacent to the endplates.

Although the invention has been described in terms of several preferred embodiments, many variations and modifications will become apparent to those skilled in the art. Therefore, the present invention is not limited to the above disclosure, but only by the scope of the claims.

[Brief explanation of drawings]

1 is a circuit diagram of a first embodiment of the present invention incorporated in a single chip; FIG. 2 is an equivalent circuit diagram of the bidirectional output semiconductor field effect transistor shown in FIG. 1; and FIG. Figure 1 is a diagram showing the characteristic output voltage as a function of time for the charging voltage isolation circuit, Figure 4 is a diagram showing the current control characteristics of the relay circuit in Figure 1, and Figure 5 is a diagram showing the characteristic output voltage as a function of time for the charging voltage isolation circuit of Figure 1. Figure 6 shows the plane of one chip, particularly showing the drain and source metal patterns, and Figure 6 is an enlarged view of the wafer surface and the junctions formed there. FIG. 8 is an enlarged view of the junction pattern in part B surrounded by the broken line in FIG. 5, and also shows the PNP transistor and diode junctions of the circuit of FIG. 6 shows a cross-section of FIG. 6 along line 8-8 of FIG.
Figure 8a shows the basic junction pattern used in a 3FET device; Figure 8a shows that the gate oxide is a terminated short in the curved area of the polysilicon gate;
9 shows a cross-section taken along line 9--9 in FIG. 7 as well as the junction pattern for the transistor and diode in FIG. 1; FIG. 10 shows a portion of the edge of the chip in FIG. 11 is a cross-sectional view taken along line 11--11 in FIG. 10, FIG. 12 is a plan view of a second embodiment of the invention, and FIG. 13 is a cross-sectional view taken along line 13--13 in FIG. 14 is a diagram showing a second embodiment incorporated into the chips of FIGS. single sea urchin
The top view of..., Fig. 16, is the line 16-16 K in Fig. 15.
Figure 17 shows the wafer of Figure 16 after surface oxidation and formation of a photoresist mask on one surface; Figure 18 shows the removal of the oxide layer from one surface of the wafer; Figure 17 shows the wafer after
Figure 21 shows the wafer of Figure 19 after a photoresist mask has been formed on one surface and the oxide layer has been removed from the other side; Figure 21 shows the wafer of Figure 20 with a very high 22 shows the wafer of FIG. 20 after all oxide has been removed from the wafer, and FIG. 23 shows the wafer of FIG. Figure 24 shows a stack formed with the same wafer as the wafer in Figure 24 with interposed aluminum foil and aluminum contacts at both ends; Figure 24 is a parallel 6 cut from the stack of Figure 23 after the stacks have been alloyed together;
25 shows a top view of the charging voltage isolator of FIG. 24 housed within a plastic housing; FIG. 26 shows a line 26-- of FIG. 25; FIG. 26 is a cross-sectional view, and FIG. 27 is a cross-sectional view of the stack of FIG. 24, and shows the appearance of saw damage after cutting. 19...Photovoltage diode, 2o...Charging voltage insulator, 2
1- LED, 24 ・BOSFET, 30.
31 River MOSFET 150°51,. 80.81・
・Drain, 54, 55. 58...Drain finger,
56... Source finger, 60... Board hat,
61... Gate band, 72a, 72b... Channel region 1, 82, 83, 113, 114, 133, 134-
N+ region 90.91 ・Polysilicon gate, 111
, 112...P type diffusion, 130...P ten area, 200
...NPN transistor, 201...P channel MO8FET, 202-=resistance, 321, 331
- Oxide film, 332... Photoresist layer, 340,
341,. 342...wafer, 344. ．． 345,3
52,353,361,362... Electrode, 351... Slab, 360 = LED 1401,402-... End, 410,441 = Epoxy lump. 1 other person Kate Obi E (V) -F slow F and Siwoa- Sancho Ishin City j-[τμT (Method) February 27, 1985 Commissioner of the Patent Office Tono 2, Name of the invention Relationship between solid-state relay circuit 3 and the famous case requiring amendments Applicant Name International Rectitude ψ−
・] - Boration 4, Dai J! 11 people Address: Minami Vj Yama-chome 1-1-5, Minami-vj Yama-chome, Minato-ku, Sokusoto Minato-ku, Ifζ1 of the amendment order (voluntary) (Shipping port) Showa month [1 Hair]

Claims (1)

[Scope of Claims] (1) LED means having a human power monitoring terminal, and this LED
a charging voltage isolation circuit having a photovoltage plate optically coupled to and electrically insulated from the LED means and having positive and negative output terminals for generating a voltage in response to illumination by the LED means; A light voltage actuated solid state relay circuit having first and second output power terminals, a gate terminal and a substrate terminal, withstanding a voltage greater than about 50 (V) between the output terminals and between the gate and substrate terminals; a bidirectional output semiconductor field effect transistor which switches to a conductive state in response to the application of a voltage higher than about 1 [■] to a voltage of about 100 K
Ω]; a diode having an anode connected to the positive terminal of the photovoltaic stack and a cathode connected to the gate terminal; a base connected to the anode of the diode; a high gain transistor having an emitter connected to the cathode and a collector connected to the substrate terminal, the generation of an output from the photovoltaic stack providing sufficient power to rapidly turn off the field effect transistor. A solid-state relay circuit, wherein the high gain transistor is turned on to reduce the input impedance of the relay circuit when the voltage output of the photovoltaic transistor becomes lower than a predetermined value. (2. The circuit according to claim 1, wherein the high gain transistor is a PNP transistor). (3) In the circuit according to claim 2, the prepacked field effect transistor, the diode, the PNP
) A circuit in which the transistor and the resistor are integrated elements formed within a single chip of silicon. (4) In the circuit according to claim 1, 2, or 3, the field effect transistor has a negligible leakage current flowing between the output terminals when the field effect transistor is off, and has a resistance of about 25 Ω between the output terminals.
] A circuit that is a metal oxide field effect transistor having less conduction resistance. (5) in a bidirectionally conducting insulated gate field effect transistor having a high resistivity body of one conductivity type, a shallow high resistivity implant region of the other conductivity type formed by implantation and processing into said body; first and second laterally disposed drain regions of said other conductivity type formed in said implant region and spaced apart centrally of said drain region extending through said implant region; a central region of said one conductivity type extending as shown in FIG. an insulated gate disposed on a surface of the implant region and aligned with the channel and a gate insulating layer disposed over the channel, connected to the first and second drain regions, respectively; and a source electrode connected to the source region and the central region, the source electrode being disposed adjacent to but insulated from the gate means. A bidirectional conducting insulated gate field effect transistor, wherein current flows between the drain electrode and through the source electrode when the channel is inverted by a voltage of . (6) The device according to claim 5, wherein the one conductivity type is P type and the other conductivity type is N type. (7) A device according to claims 5 and 6, wherein the implanted region has a depth of approximately 5 μm. (8) The device according to claims 5, 6, and 7, wherein the gate insulating layer has a thickness of about 700 (X). (9) A device according to claims 5, 6, 7 and 8, wherein said source means comprises two channels defining respective first and second channels in said central region. A device with spaced source regions. Ql A device according to claim 9, wherein the lateral edges of the low conductivity portion of the central region are defined by the same diffusion window as the source region and are self-aligned to the source region. aυ The device according to any one of claims 1 to 10, wherein the drain region, the central region,
and a device in which the source region has parallel elongated strips spaced apart from each other. a2, the device according to claim 11, wherein the central region is disposed on both sides of the central region and is disposed in the axial direction from the first and second drain regions; and a third portion having a first portion extending from one end of the central region disposed between the second drain regions and a second portion extending from the other end disposed between the third and fourth drain regions. a fourth drain region; and third and fourth drain electrodes connected to the third and fourth drain regions, wherein the first and second drain electrodes are connected to each other and the first
the third and fourth drain regions are connected to each other to form a second common power terminal, and the third and fourth drain regions are connected to each other to form a second common power terminal, and when the channel is inverted there is a An element that allows directional current to flow. (131) The device of claim 12, wherein the first and second drain regions are first comb-shaped drains having a plurality of fingers substantially identical in cross section to the first and second drain regions. the third and fourth drain regions are the third and fourth drain regions;
a second having a plurality of substantially identical fingers in the drain region;
a comb-shaped drain region element, each of the central region, source region and channel region being six pairs of fingers of said first and second comb-shaped drain region. 04 A device according to any one of claims 1 to 13, comprising a diode and a PNP transistor integrated in the body, the diode comprising a PNP transistor formed in the implanted region. a P-type diode region and an N-shaded region formed within the P-type diode region; 15. A device according to claim 14, comprising a base region of the PNP transistor and a collector region of the PNP transistor formed by the P-shaped body. (1e) an insulated high-resistivity lamp extending around at least a portion of the outer edge of the surface of the IJ lamp; a shallow high resistivity depletion layer of said depletion layer; first and second elongated drain regions of said other conductivity type formed in the surface of said depletion layer with adjacent ends spaced apart from each other; an elongated central region of said one conductivity type formed on a surface and extending parallel to and laterally spaced from said first and second drain regions, dividing one from the other; a source region of said one conductivity type extending over a surface and an edge of said source region defining an elongated channel spaced from an edge of said central region and capable of being reversed from said other conductivity type to said one conductivity type; Department and
a gate insulating layer having a gate electrode on top covering the elongated channel on a surface of the body;
ζ A device comprising first and second drain electrodes connected to a drain region of ζ, wherein current flows bidirectionally between the first and second drain electrodes when the channel is inverted. αη The device of claim 16, comprising an elongated source electrode connected to the source region;
The source electrode is adjacent to but insulated from the gate electrode. aυ The device of claim 16, wherein said first and second drain regions each include a first and second comb having a plurality of parallel fingers identical in cross-section in said first and second regions. a tooth-shaped drain region, wherein an elongated central region and source region identical to the central region and the source region are disposed between adjacent pairs of drain region fingers in each of the first and second comb-shaped drain regions; element. (II L, F, D radiation sources and a photovoltage stack with series-connected junctions in the form of a rectangular parallelepiped,
accommodating the LED and the photovoltage stack; the LED is spaced apart from the photovoltage stack by more than about 0.5 (m) to obtain the desired isolation between the LED and the photovoltage stack; wherein the LED is centered on one vertical side of the stack and configured to illuminate at least the one vertical side of the stack, and the stack is configured to have a υ, the stack has a significantly lower height and improves the uniformity of illumination of at least one vertical side of the stack by the LED, the stack being a vertical stack of a plurality of identical single crystal silicon chips υ In a charging voltage insulator, each of the chips has a thin body having planar first and second surfaces, each of the chips has a main body portion of P-type conductive material, and each of the chips has a main body portion of P-type conductive material; each of the chips has a shallow N-type diffusion extending into said first surface to a uniform depth over substantially the entire surface area of said second surface; said P-shaped body extending into said second surface thereof to a depth of approximately 100 psi, said chips having a shallow P soil layer of substantially high conductivity, and said chips disposed between adjacent chips of said stack; a plurality of high conductivity layers mechanically and electrically connecting said stack together such that the forward conduction direction of each is in the same direction; and at least a portion of one surface of a vertical side of said stack. The P-type layer and the N-type layer of each of the P-type body and the chip are exposed and provide edge illumination of the stack.
A charging voltage isolator comprising an edge of a junction with a mold layer and first and second electrodes on opposite ends of the stack. (2G In the element described in claim 19,
The thickness of each of the chips is less than the average diffusion length of minority carriers formed within the body in response to radiation to the vertical sides of the chip. +21) The photovoltage stack consists of a vertical stack of a plurality of identical monocrystalline silicon chips, each of said chips being used for the control of a semiconductor device having a thin body with flat first and second parallel sides. In a photovoltage stack, each of the chips is a main body portion of long-life P conductive material, and each of the chips has a uniform depth of 1 over substantially the entire surface of the first side. The stack has a shallow N diffusion layer extending into the first blood, and is arranged between adjacent chips of the stack, and the stack is mechanically moved so that the forward conduction direction of each of the chips is in the same direction. a plurality of high conductivity layers electrically connected together; A photovoltage stack characterized in that it comprises an edge of a junction between each of the N-soil layers of chia 7' and a j-th and second electrode at both ends of the stack. (2) In the device according to claim 21,
Each of said chips has a shallow P diffusion layer of substantially higher conductivity than that of said P-type body extending into said second blood to a uniform depth over substantially the entire surface of said second surface. element with (c) The device according to claims 21 and 22, wherein the thickness of each of the chips is equal to the number of minority carriers formed in the body in response to radiation to the vertical sides of the chip. less than an average diffusion length, such that the P soil layer acts as a reflector to reflect fractionally modified carriers towards a collection junction formed by the P type body and the N soil layer. I241 In the device according to claims 21, 22 and 23, the N soil layer has a thickness of about 1 x 102
The N layer has a conductivity defined by the presence of 0 to 4 x 1020 [atoms/d] impurities on the first surface, and the N layer is in the P conductivity form when alloyed to the aluminum foil. An element characterized by not changing. (c) In the device according to claims 21, 22, 23, and 24, the plurality of high conductivity layers are made of foil having a thickness of about 0.0254 mm, and an element made of a substance selected from the group consisting of aluminum, aluminum alloy, and aluminum-silicon low melting point material. 26. The device of any of claims 21-25, wherein the chips are less than about 0.23 in thickness and the stack comprises less than about 15 chips. @ In the device according to claim 26, the N soil layer is formed of a diffused Linnean pure substance, and this Linnean pure substance acts as a getter for the metal ions in the P-type body, and An element designed to extend the life of the mold body. 0Q A switching circuit for rapidly switching on and off a power metal oxide semiconductor field effect transistor, said transistor having a drain, source and gate electrode, said switching circuit switching between high and low input voltages. an input unidirectional voltage source having an input unidirectional voltage source having a switching transistor having switchable first and second terminals, a diode, and first and second electrodes and a control electrode, wherein the first and second terminals of the voltage source terminals of the voltage source, the diode and the gate and source electrodes of the power transistor are connected in a closed series circuit such that when the voltage source is switched to the high voltage, current from the voltage source flows through the diode to the the first and second electrodes of the switching transistor are connected to the gate and source electrodes of the power transistor, and the control electrode is connected to the first terminal of the voltage source. , the switching transistor is configured to switch on so as to define a discharge path across the gate capacitor when the voltage of the voltage source decreases from the high voltage to the low voltage.翰 The circuit according to claim 28, further comprising a clamp circuit connected between the gate and source electrodes of the output transistor, and the clamp circuit is configured to adjust the voltage between the drain and the source by dV/dt. 2. A circuit for bypassing a mirror current in the parasitic drain-gate capacitance of the output transistor when the output transistor exceeds a predetermined value. (To) The circuit according to claim 29, wherein the clamp circuit includes a resistor and a capacitor connected in series and a transistor connected in parallel to the resistor and capacitor, and the transistor having a control electrode is connected to the resistor and the capacitor. A circuit connected to the connection point between the capacitor and the capacitor.