JPS601699A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the area of a selector circuit by using in common an output line for memory cells divided into groups. CONSTITUTION:Memory cell groups 1a and 1b which store information are provided together with check cells 2 and 3 which store the information for storage of bit errors produced within memories 1a and 1b, selectors 10, 12, 13 and 8 which select plural pieces of cell information which are needed for correction of the bit error out of the information of cells 1a and 1b and select the check cell information as well as the memory cell information needed for correction of the bit error out of the information of cells 2 and 3, and self-correcting circuits 20, 21, 31 and 32 which perform automatic corrections of bit errors based on each memory cell information and check cell information. Then the output lines of the cells 1a and 1b of each group are used in common every K units.

Description

Detailed Description of the Invention Technical Field of the Invention The present invention relates to a semiconductor memory device having a self-correcting circuit that automatically corrects bit errors occurring in a memory using an error correction code. The present invention relates to a semiconductor memory device that can be downsized.

Background of the Technology As a semiconductor memory device with a built-in circuit that automatically corrects pit errors that occur in semiconductor memory, horizontal and vertical parity check codes are applied to multiple memory cells connected to one word line. We previously proposed a semiconductor memory device that self-corrects pit errors by
(Japanese Patent Application No. 56-37223).

Figure 1 (α), (hl is an explanatory diagram of its principle. α represents the horizontal parity bit for 16 data bits arranged on a 4×4 matrix, and k represents the vertical parity bit.
Indicated by where data bit and parity bit α,
If b is moved as shown by the broken line in Fig. 1 (al), the same 2
The dimensional matrix can be transformed into an 11-dimensional matrix such as Fig. 1(A+). Therefore, Fig. 1(h
) among the 24 bits in the one-dimensional matrix of
By comparing each group shown by the solid line in h) with the parity bits of the lower 8 pits, the error bit position can be detected. Therefore, any 1 of the upper 16 bits
Even if a fixed defect or a non-fixed defect occurs in a bit, the defective bit position can be detected, and accordingly, error correction can be easily performed.

FIG. 2 shows an Ml configuration of a self-correcting memory using the principles of FIGS. 1(α) and (h). Figure 2 shows a self-correcting memory when the data bit width is 1 bit, where 1 is memory cell 4.
2 is a horizontal parity cell section consisting of horizontal parity cells 5; 5 is a vertical parity cell section consisting of vertical parity cells 6; 7-1 to 7-? W
, 9.13 is a selector that selects 1 bit from among the tree pit line information, 8 is a selector that selects a bit from among (ICx 2 TrL) pieces of bit line information, and 12 is a selector that selects 2 m bit lines. Selector for selecting one bit from information, 20゜21c Horizontal and vertical parity check circuit, 24Hry-1'M1.31c 2 person cuff 17V
D'f-t, 32c is a two-man powered EOR gate. K indicates the number of vertical pit line groups, and 2rrL indicates the number of horizontal pit line groups. In this configuration, (K x
2rn ) data bit lines and (K 1,2m
) is formed by the parity pit lines of the book. (K x
2m) Tree data bit lines are grouped in K pit units to form 2m groups of data bit lines to form horizontal parity bit information in bit units.

Further, (rc x 2 m, ) data bit lines form vertical parity bit information in units of 2rn pits, and are therefore grouped in units of 27n pits to form K groups of data bit lines. and.

Corresponding to 2m groups of horizontal data bit lines for forming horizontal parity bit information, 2rn horizontal parity pit lines and 2 groups of vertical data bit lines for forming vertical parity bit information. A vertical parity pit line is provided for each data bit line group, and receives test information for each data bit line group.

In this configuration, the data bit information group to which desired data bit information for performing horizontal and vertical parity checks belongs is selected by the selectors 8 and 7-1 to 7-2m, and the horizontal and vertical parity check circuit 20
, 211=supplied. Horizontal and vertical parity bit information regarding desired data bit information are also selected by selectors 12 and 13 and supplied to horizontal and vertical parity circuits 20 and 21, respectively.

If an error is detected in the desired data bit information, the output of the gate 51 becomes 1'', and the data bit information is inverted, ie, corrected, and outputted at the gate 32.

The layout around the selector and multiplexer in this configuration is shown in FIG. 3 (α). 1 is a memory cell section, 2 is a horizontal parity cell section, 5 is a vertical parity cell section, 8 is a selector for selecting horizontal data bit line information, 10 is a selector for selecting a group of vertical data bit line information, 11 is a multiplexer, 12 , 13 is a selector for selecting horizontal or vertical parity pit line information, 20 and 21 are Suijosai 6 and vertical parity boonic circuits, 6D is a two-man-powered HD gate that inputs bit line information and a selection signal, and 61 is 2
The human-powered AND gate 32 is a two-human powered E011 gate. FIG. 6(h) shows a specific circuit example of the two-person AND gate 60. b is the pit line.

8 is a selection signal line. In this layout, the number of data bit lines is (K×2m), and the total number of output lines of selectors 8 and 10 for selecting horizontal and vertical data bit line information is CIC+2m>.

Prior Art and Problems In a layout with a conventional circuit configuration, the circuit area of selectors 8 and 10 is (Ky, 2m)P, ・(K+ 2
m) Ps; (PJI: pit line pibboo, Ps
5: selector output line pitch). Since this selector occupies a large circuit area within the memory, there is a problem in reducing the circuit area.

OBJECTS OF THE INVENTION In order to solve the drawbacks of the prior art, the present invention divides a plurality of memory cells that store information forming an error correction code into a plurality of groups, and provides an output line for obtaining desired information corresponding to each group. Alternatively, by making the output line and the selector common, the circuit area of the selector is reduced.This will be explained in detail below with reference to the drawings.

Embodiment of the Invention FIG. 4 shows an embodiment of the invention. 1α is g of the memory cell part! A' 1 block, 1h is the second block of the memory cell section, 2 is the horizontal parity cell section, 3 is the vertical parity cell section, 8 is the selector for selecting the horizontal data bit line information group, 10 is the vertical data bit line Selecting information group - 11 is a multiplexer, 12.1 is a selector for selecting horizontal and vertical parity bit line information, 20
, 21 is a horizontal and vertical parity check circuit, '5
0 is an AND gate that inputs bit line information and a selection signal, 61 is a two-man powered A7VZ) gate, and 52 is a two-man powered EOR.
It is a gate. In this embodiment, the memory cell section has two
It is divided.

The configuration is such that (K x m) tree data bit lines are output for each divided block. The vertical data bit line information group forms groups of about 2 mm bits out of (K x 2 m) pieces of data bit line information, but in this embodiment, each divided block has vertical data bits. m-pitch of one group of line information group)K
Assign each group.

With this configuration, the number of output lines of the selector 1o for selecting vertical data bit line information for each block is only m. Therefore, the circuit 1 product of selectors 8 and 10 in this embodiment is (K x 2m) Pa x (K+rn) Ps
Therefore, the circuit area of the selectors 8 and 10 having the configuration shown in FIG. 6 can be reduced to (K + m)/(K + 2 m') times.

FIG. 5 is another embodiment of the present invention. 1a is the first block of the memory cell section, 1h is the second block of the memory cell section,
2 is a horizontal parity cell section, 3 is a vertical parity cell section, 8
is a selector for selecting a horizontal data bit line information group, 10
is a selector for selecting a vertical data bit line information group, and 1
0/2. IOb is the first and second blocks, 11 is a multiplexer, 12,1!1 is a selector for selecting horizontal and vertical parity focus line information, and 14 is (1(x m
) gates 54, circuit block 15 is (
A circuit block consisting of K x m, ) gates 65, 60 is a two-man-powered ANi) gate that inputs bit line information and selection signals, 61 is a two-man-powered AND gate, 62 is a two-man-powered EOR gate, o if the desired data bit line clearance exists in the first block 1α of the memory cell section.
A transfer gate 65 turns off when the desired data bit line information exists in the second block 2a of the memory cell section, and a transfer gate 65 turns off when the desired data bit line information exists in the first block 1α of the memory cell section. 80ff, and the desired data bit line information is stored in the second memory cell gB.
On if it exists in block 2α.

This is the transfer gate. In this embodiment, the memory cell section is divided into two, and each block is configured to output (K x m) data bit lines. Each block (JcX77L) data bit lines are connected to the selector 10α2 circuit block 14. Selector 8. Marboo Brexa 119 circuit block 15.
It is shared through the selector 10b. In this self-correcting memory, a horizontal data bit line information group of 277L groups is formed in units of K pits and a vertical data bit line information group of groups is formed in units of 277L pits from among (J(x2m) pieces of data bit line information). will be done.And,
The (ICx m) data bit lines of the first block 1α of the memory cell section (-assign a group to m pits of the horizontal data pit line group and 1 vertical data bit line group.Similarly, the memory The (K x m) data bit lines of the fJ2 block 1h of the cell section are allocated in the first block 1α of the memory cell section. Allocate the remaining m hits of the group to the group.

In this embodiment (in order to perform error correction of desired data bit information in -, the desired data bit information is present in the first block 1α of the memory cell portion l/), the gate 54 is turned on; Gate 35 is turned off and selector 8
The (K x m) data bit lines on the multiplexer 11 are connected to the (K x m) data bit lines of the first block 1α of the memory cell section.
) data bit line information is conveyed. Further, when desired data bit information exists in the second block 1b of the memory cell portion, the gate 54 is turned off and the gate 35 is turned off. The (K x m ) data bit lines of the selector 8 and the multiplexer 11 are transmitted with (K x m ) data bit information of the second block 16 of the memory cell section. Therefore, the selector 8 can select a bit in the horizontal data bit line information group to which the desired data bit information belongs, and the selector 10a can select the bit in the memory cell section from the vertical data bit line information group to which the desired data bit information belongs. The selector 10A can select m bits existing in the second block 1h of the memory cell section from the vertical data bit line information group. With this configuration, one circuit block 14, 15 is added, but since the data pin I-line is a (K x nl) tree, the circuit area of the selectors 8 and 10 is (K x m
) PBx (IC+2m)Ps, m Figure 3 (
1/ of the circuit area of selectors 8 and 10 in the configuration shown in α)
It is possible to reduce this by 2 times.

The following table summarizes the comparison of the circuit area of the selector according to the embodiment of the present invention and the conventional structure. The reduction in the circuit area of the selector according to the present invention is remarkable.

As described in detail, the present invention provides a semiconductor memory device having a self-correcting circuit that self-corrects bit errors occurring in a memory using an error correcting code. There is an advantage that the circuit area of the selector can be reduced by dividing the memory cells into a plurality of groups and sharing the output line corresponding to each group or the output line and the selector.

Furthermore, if memory cells that store information forming the same error correction code are divided into multiple groups and adjacent cells are arranged so that they belong to different error correction codes, multiple pieces of information within the same error correction code will be There is also the advantage that the soft error rate can be further reduced because the probability of being simultaneously destroyed by particles or the like is lowered.

In the above explanation, the effect was described in the case where a plurality of memory cells storing information forming the same error correction code are divided into a plurality of groups.

A similar effect can be obtained when a plurality of test cells storing test information in the same error correction code are divided into a plurality of groups.

In addition, in the above explanation, the self-correcting memory to which horizontal and vertical parity check codes are applied as error correction codes will be explained.
Although the effects have been described, similar effects can be obtained with self-correcting memories to which other error correction codes are applied.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of horizontal and vertical parity check codes, @2
The figure is a configuration diagram of a self-correcting memory using the principle of FIG. 1, FIG. 3 (α), (A) is a specific layout of the configuration of FIG. 2, and FIG. 4 is an embodiment of the present invention. FIG. 5 shows another embodiment of the invention. 1...Memory cell section, 1α...First of the memory cell section
Block, 1h...Second block of memory cell section, 2
...Horizontal parity cell section, 3...Vertical parity cell section, 4...Memory cell, 5...Horizontal parity cell,
6... Vertical parity cell, 7-1 to 7-2T1L,
8, 9, 10, 10α, 10A, 12.13...
- Selector, 11...Multiplexer, 14...Circuit block composed of gate 34, 15...Circuit block composed of gate 35, 20, 21...Horizontal and vertical parity check circuit, 24 ...Word line, 30...Pit line information and selection signal are input 2
Human-powered AND gate, 31...2 human-powered AND gate, 3
2...Two-man powered EOR gate, 54, 55...Transfer gate Patent applicant: Nippon Telegraph Corporation agent Patent attorney: Gobe Tamamushi (3 others) Figure 1 (a)

Claims (2)

[Claims] (1) A plurality of memory cells that store information, a plurality of test cells that store information for detecting pit errors that occur in the memory, and an error correction code from among the information of the plurality of memory cells. a selector for selecting memory cell information and test cell information necessary for correcting a pit error from a plurality of memory cell information forming a plurality of memory cells and information of the plurality of test cells; and a selector for selecting each selected memory cell information and test cell information. In a semiconductor memory device having a self-correction circuit that automatically corrects pit errors based on cell information, a plurality of memory cells that store information forming the same error correction code are formed into a plurality of groups to obtain desired information. A semiconductor memory device characterized by having a common output line. (2) A semiconductor according to claim 1, characterized in that a selector and an output line respectively corresponding to a plurality of groups of a plurality of memory cells storing information forming the error correction code are shared. Storage device.