JPS60179859A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To correct an error of a memory cell and to save bit errors due to a fixed defective bit, alpha-rays, etc. by including information memory cells in three or more independent groups respectively and forming a test memory cell. CONSTITUTION:Horizontal parity bits (a), vertical parity bits (b) and lower right parity bits (c) are formed for 16 data bits arranged on a 4X4 matrix. The horizontal and vertical parity bits (a), (b) are the test information of horizontal and vertical bit groups and the lower right parity bits (c) are the test information of the bit group (a) in the lower right direction. When an one-bit error is generated in the 16 data bits on the matrix, the three bit groups are compared with respective parity bits to detect the one-bit error and a two-bit error can be also detected and corrected.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a built-in circuit for automatically detecting and correcting fixed defective bits and bit errors caused by the incidence of alpha rays. It is something.

Prior Art and Problems As a semiconductor memory device with a built-in circuit that automatically corrects bit errors that occur within a semiconductor memory, multiple memory cells (dual-use A semiconductor memory device that self-corrects bit errors by
6-57226) Figure 1 is a diagram explaining the principle,
The horizontal parity pits for 16 data bits arranged on a 4×4 matrix are denoted by α, and the vertical parity pits by b. If the data bits and parity pits α and b are moved as shown by the broken lines in FIG. 1(α), the two-dimensional matrix can be converted into a one-dimensional matrix as shown in FIG. 1(A).

Therefore, 2 in the one-dimensional matrix of Fig. 1 f&)
An error in any one bit among the upper 16 bits among the 4 bits can be detected by comparing the error pit position with the parity pits of the lower 8 pits for each group shown by the solid line in the figure. By associating such a one-dimensional matrix with memory cells connected to word lines, a semiconductor memory device that self-corrects pit errors can be realized.

However, if a two-pit error occurs in the data bits, the method shown in FIG. 1 cannot correct it in principle. This will be explained using a two-dimensional matrix shown in FIG. (α) in FIG. 2 shows the case where two pit errors do not exist in the same group. If the inspection focuses on the position where the pit error exists, the error pit can be corrected, but if the inspection focuses on the pit C or d in the figure, the pit C or d is Even though the pits are normal, they are incorrectly corrected and the number of pit errors increases.Also, as shown in Figure 2 (b) (= if two pit errors exist in the same group, Comparing that group with the parity pits, no errors can be detected.

As explained above, in a semiconductor memory device that self-corrects pit errors by applying a horizontal/vertical parity code, it is possible to correct an error in any one pin out of the 4 bits of data forming the horizontal/vertical parity code. , errors of 2 bits or more cannot be completely corrected. Therefore, in this semiconductor memory device, after one pit error caused by a fixed defect is repaired for each word line, non-fixed pit errors caused by α-rays, etc. (2) are repaired in memory cells connected to that word line. In this case, the problem is that the non-fixed bit error cannot be completely repaired.

OBJECTS OF THE INVENTION The present invention attempts to solve the drawbacks of the prior art, and its purpose is to provide a semiconductor memory device capable of relieving both fixed defective pits and non-fixed defective pits. It is about providing.

Composition of the Invention A semiconductor memory device of the present invention has an information memory cell for storing information and a plurality of pit lines and word lines for selecting the information memory cell, in which each of the plurality of pit lines has six pit lines. The number of pit line groups (two pairs of inspection parity pit lines and Each of the test parity pit lines (a plurality of test memory cells that are connected to each other and activated by the word line, and test information regarding a plurality of pit information to be stored in the information memory cell) is stored in the test memory cell. a selector for selecting a group of bit line groups including a pit line related to information to be inspected and a parity pit line for inspection related thereto from the plurality of bit line groups, and using an output of the selector. a plurality of parity check circuits that perform parity checks on the plurality of bit line groups; a circuit that performs logical product or majority logic of the outputs of the parity check circuits; and means for correcting errors in the information.

Embodiment of the Invention FIG. 3 is an explanatory diagram of the principle of error correction in an embodiment of the present invention, and is an example of a case where individual information memory cells connected to each word line are assigned to six independent groups. For the 16 data bits arranged on a 4x4 matrix, the horizontal parity bit α, the vertical parity pit b, and the lower right parity bit are shown as e.The horizontal parity bit and the vertical parity pit are Similar to the horizontal and vertical parity codes, this is check information for bit groups in the horizontal and vertical directions.The lower right parity pit is shown in Figure 3 (
As shown in α), this is the inspection information for the focus group in the downward direction to the right. 1 in 16 data bits on this matrix
If a bit error occurs, the position of one pit error can be detected by comparing three pit groups with each parity pit as shown by (Al in FIG. 6).

Also, 2 out of 16 data bits on the matrix
When a bit error occurs, there is a mode in which normal pits are incorrectly corrected in horizontal/vertical parity codes, as shown in (a) of FIG. 2-bit error can be corrected. Further, in FIG. 3, the bit group in the downward right direction is the object of inspection, but the pits in the downward left direction may be used as the bit group.

FIG. 4 shows a specific configuration example of the present invention based on the principle shown in FIG. In this embodiment, the pits in the two-dimensional matrix shown in FIG. 6 are made one-dimensional, and the one-dimensional pit arrangement is made to correspond to memory cells connected to word lines. In the figure, 1 is an information bit line, 2 is a horizontal parity bit line, 6 is a vertical parity bit line, 4 is a lower right parity bit line, 5α, 5b, 5C are word lines, 6 is an information memory cell, and 7 is for inspection. Memory cells 11, 12, and 13 are each from multiple bit lines, bottom right.

Selectors for selecting vertical and horizontal bit line groups, 14, 15
．． 16 are selectors 17, 18, and 19 for selecting inspection broadcasts corresponding to the horizontal, vertical, and lower right bit line groups from the horizontal, vertical, parity, and lower right parity pit lines, respectively;
is a parity check circuit, 20 is a multiplexer, 21
is a 3-person AND gate, and 22 to 26 is a 2-person FOR game.
), 27 are gates that are turned on when the read enable is enabled and turned off when the write enable is enabled, and gates 28 to 31 are gates that are turned off when the read enable is enabled and turned on when the write enable is enabled. This memory operation will be explained below.

First, the stored information in all information memory cells and test memory cells is cleared. At the time of reading, the stored information of the information memory cell and the test memory cell connected to the selected word line, for example, the word line 5a, appears on the bit line and the test bit line.

Among them, three bit line groups are selected by selectors 11 to 13 and 14 to 16 from the bit line group and check bit line to which the output information to be corrected is related, and the stored information is stored in parity check circuits 17 to 19. is input and a parity check is performed. Then, only when the outputs of the three parity check circuits 17 to 19 are all "1'", that is, a parity error occurs, the logic gate 21
The output of the word line becomes "1", and the stored information is inverted (corrected) by the -EOR gate 22, read out to the output terminal OUT, and at the same time is re-stored to the original position via the gate 27. The same applies when 5h and 5(? are selected.

Further, during writing, the stored information of the write address before writing is read out in the same manner as during reading, and the EOR gate 23 compares that information with the write information applied to the input terminal IN. Then, using this comparison result, the EOR gates 24 to 26 are used to update the information stored in the test memory cell at the same time as writing information to the write address. Therefore, the contents of the information stored in the test memory cell are updated only when the read information and the hidden information are different.

FIG. 5 is an explanatory diagram of the principle of error correction in another embodiment of the present invention, and is an example of a case where individual information memory cells connected to each word line are assigned to four independent groups, For 16 data bits arranged on a 4x4 matrix, horizontal parity focus α, vertical parity pit b, lower right parity pit 'txt, lower left parity pit f, "O" fixed virtual data bit is set to 1. Indicated by

Virtual data bit 1 is added to maintain the independence of the horizontal, vertical, lower right, and lower left bit groups. The horizontal parity pit and the vertical parity pit are check information of bit groups in the horizontal direction and the vertical direction, similar to the horizontal and vertical parity codes. The lower right parity pit is check information for a bit group in the downward right direction as shown in FIG. 6 (2). The lower left parity pit is check information for a bit group in the downward left direction as shown in FIG.

If a 1-pit error occurs in the 16 data bits on this matrix, the location of the 1-pit error can be determined by comparing four independent bit groups with their parity focus as shown in Figure 8. can be detected. Furthermore, when a 2-bit error occurs in the data bits on the matrix, as shown in (α) and (Al in Figure 2), the horizontal and vertical parity codes cannot correct the 2-bit error. , the present invention corrects 2-bit errors.

FIG. 9 shows an example of an integrated structure of the present invention based on the principle shown in FIG. In this embodiment, a one-dimensional version of the two-dimensional matrix shown in FIG. 5 is associated with memory cells connected to word lines.

However, there is no memory cell corresponding to the fixed virtual data bit "Pa0". In the figure, 1 is an information pit line, 2 is a horizontal parity bit line, 6 is a vertical parity pit line, 4 is a lower right parity pit line, and 5 is a vertical parity pit line. is a word line, 6 is an information memory cell, 7 is a test memory sensor ν, 8 is a lower left parity pit line, 14, 15, and 16 are horizontal, vertical, and lower right pits from the horizontal parity, vertical parity, and lower right parity bit line, respectively. a selector for selecting test information corresponding to a group; 17.
18. 19 is a parity check circuit, 20 is a multiplexer, 22 to 26 are two-man EOR gates, 27 is a gate that is turned on when read enable and turned off when write enable, 28 to 32 are turned off when read enable is turned on, and turned on when write enable is applied. 41 is a selector that selects inspection information corresponding to the lower left pit group from the lower left parity bit line, 42 is a parity check circuit, and 46 is a two-man EO
The R gate 44 is a 3-act-op-4 majority logic gate. Reference numerals 50 to 56 are selectors for selecting lower left, lower right, vertical, and horizontal bit line groups from a plurality of focus lines, respectively. The selectors 50 to 53 not only select the pit line information corresponding to the data bits included in each pit group, but also select certain bit line information from the "0" fixed virtual data bit included in each pit group. As in (, the output is “0”
” The fusuma is made to look like this.

This memory operation will be explained below. First, the stored information in the entire information memory cell and test memory cell is cleared. At the time of reading, the stored information of the information memory cell and the test memory cell connected to the selected word line, for example, the word line 5a, appears on the pit line and the test bit line. From the pit line group and inspection bit line to which the output information to be corrected is related,
Four pit line groups are selectors 40.11-16. and 14
.about.16.degree. 41, and the stored information is input to parity check circuits 17 to 19.42 to perform a parity check. Then, among the outputs of the four parity check circuits 17 to 19.42, six or more outputs are “
1", that is, when the output of the logic gate 44 becomes "1", the stored information is inverted (corrected) by the EOR gate 22, and is read out to the output terminal OUT. At the same time, the output of the logic gate 44 becomes "1". will be re-stored at the location.

The same applies when other word lines 5b and 5C are selected.

Furthermore, during writing, the stored information before writing of the write address is successively read out in the same way as when reading, and the information is compared with the write information q EOR gate 26 applied to the input terminal IN. Using this comparison result, the EOR gates 24 to 26, 4 are simultaneously written to the write address.
3'r is used to update the storage information of the test memory cell. Therefore, the content of the information stored in the test memory cell is changed only when the successive information and the write information are different.

As described in detail, the present invention corrects errors in memory cells by assigning information memory cells to each of six or more independent groups and providing memory cells for inspection. It is possible to repair not only fixed defect focusing but also pit errors caused by the incidence of alpha rays, etc. Especially (compared to semiconductor memory devices that self-correct pit errors by applying two horizontal and vertical parity codes) This increases the correction ability and improves reliability.Furthermore, equipment level ECC (Error Checking)
There is also the advantage that the additional circuit scale can be kept small compared to the collecting method. In the embodiment, only a configuration in which the output information is one bit has been described, but the present invention has a configuration in which the output information has many pits and multiple bits are inspected and corrected at the same time. Year 7
The configuration shown in (2) can be easily applied, and also has the advantage that the additional circuit scale can be kept small.

Further, in the explanation, the basic form of the method of forming the lower left and lower right groups has been shown, but various modifications are possible by further adding dummy bits similar to y in FIG. 5.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of horizontal and vertical parity codes, Fig. 2 is a state diagram when a 2-pit error occurs in the data bits forming the code, and Fig. 3 is error correction in an embodiment of the present invention. 4 is a diagram illustrating a specific configuration example of the present invention based on the principle of FIG. 6, FIG. 5 is a diagram illustrating the principle of error correction in the embodiment of the present invention, and FIG. is an explanatory diagram showing the lower right parity bit, FIG. 7 is an explanatory diagram showing the lower left parity bit, and FIG. 8 is a state diagram when one pit error occurs in the data bits forming the code.
FIG. 9 is a diagram showing an example of an integrated configuration of the present invention based on the principle ratio shown in FIG. α...Horizontal parity bit, b...Vertical parity bit, C1d...Bit that may be incorrectly corrected,
6... Lower right parity bit, f... Lower left parity pit, 1... "0" fixed virtual data bit, 1...
Information bit line, 2...Horizontal parity bit line, 3...
・Vertical parity bit line, 4... Lower right parity bit line, 5α, 5b, 5c... Hood line, 6... Information memory cell, 7... Memory cell for inspection, 8... Lower left parity Bit line, 11-16...Selector, 17-1
9... Parity check circuit, 20... Multiplexer, 21... 3-man power AND gate, 22-26...
・Two-man EOR gate, 27...Gate that turns on with read enable and turns off with write enable, 28~
32...Gate turned off by read enable and turned on by write enable, 41...Selector, 42...
・Parity check circuit, 43...2 manual EOR zoot, 44...6 out op 4 majority logic gate, 50
~56... Selector patent applicant Nippon Telegraph and Telephone Public Corporation agent Patent attorney Gobe Tamamushi (2 others) Figure 1 (a) (b) Figure 2 (a) Figure 3 (a) Figure 4

Claims (1)

[Claims] In a semiconductor memory device having an information memory cell for storing information and a plurality of bit lines and word lines for selecting the cell, each of the plurality of bit lines belongs to six or more independent bit line groups, Test parity bit lines corresponding to the number of bit line groups when bit lines belonging to a common bit line group are grouped in units of a predetermined number, and the word line connected to each of the test parity bit lines. a plurality of test memory cells activated by a plurality of test memory cells, means for storing test information regarding a plurality of bit information to be stored in the information memory cells in the test memory cells, and a bit line related to the information to be tested. a selector for selecting a group of bit line groups and a parity bit line for inspection associated therewith from the plurality of bit line groups; and a plurality of parities for performing parity checks on the plurality of bit line groups using outputs of the selector. It is characterized by comprising a check circuit, a circuit that performs logical product or majority logic of the outputs of the parity check circuit, and means for correcting errors in the information on the bit line to be tested based on the output of the circuit. A semiconductor storage device.