JPS6240798B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device with an error correction function.

Prior Art and Problems Conventionally, as a semiconductor memory device equipped with an error correction function, there has been a structure in which horizontal and vertical parity checks are performed on multiple memory cells connected to a common word line, as disclosed in Japanese Patent Application No. 37223/1983. Disclosed in the issue. FIG. 1 is an explanatory diagram of the principle, in which horizontal parity bits for 16 data bits arranged on a 4×4 matrix are indicated by a, and vertical parity bits by b. Now, if the data bits and parity bits a and b are moved as shown by the broken lines in FIG.
It can be converted into a one-dimensional matrix such as Therefore, among the 24 bits in the one-dimensional matrix in Fig. 1b, the error in any one bit among the upper 16 bits can be determined by comparing the parity bits of the lower 8 bits for each group shown by the solid line in the figure. Erroneous bit positions can be detected. Therefore, even if a fixed defect or non-fixed defect occurs in any one of the upper 16 bits,
The position of the defective bit can be detected, and error correction can be easily performed accordingly.

An example of the configuration of a conventional self-correcting memory using the principle of FIG. 1 is shown in FIG. The second is a self-correcting memory when the data bit width is 1 bit, and in the figure, 1 is a memory cell section made up of memory cells 4 for storing information, 2 is a horizontal parity cell section made up of horizontal parity cells 5, and 3 is a self-correcting memory when the data bit width is 1 bit. is a vertical parity cell section composed of vertical parity cells 6, and these 2 and 3 constitute a memory cell section for inspection and correction. 7 is a word line, 8 is a 2-input AND gate, 9 is a 2-input EOR
gate; 10 is a selector for selecting K bits from (K×m) pieces of data bit line information; 11;
13 to 13-m, 17 is a selector that selects 1 bit from K bit line information, 16 is a selector that selects 1 bit from m bit line information, and 20 to 26 are selections of each selector. Signal generating circuits 27 and 28 are horizontal or vertical parity check circuits. Further, W indicates the number of vertical bit line groups, and m indicates the number of horizontal bit line groups. In this conventional example, there are (K×m) data bit lines and (K+m) horizontal and vertical parity bit lines.

(K×m) data bit lines form horizontal parity bit information in units of K bits, and are therefore grouped in units of K bits to form m groups of data bit lines. Furthermore, since the (K×m) data bit lines form vertical parity bit information in units of m bits, they are grouped in units of m bits to form K groups of vertical data bit lines. Then, m horizontal parity bit lines correspond to m groups of horizontal data bit lines for forming horizontal parity bit information, and K lines correspond to K groups of data bit lines for forming vertical parity bit information. A vertical parity bit line is provided to receive test information for each group of data bit lines.

In this conventional example, data bit information groups to which desired data bit information for performing horizontal parity check and vertical parity check belong are generated by dedicated selection signals in selectors 10 and 13-1 to 13-m, respectively. Circuit 20, 22-1
22-m, and are supplied to a horizontal parity check circuit 27 and a vertical parity check circuit 28. Also,
Horizontal parity bit information and vertical parity bit information regarding desired data bit information are also sent to select signal generating circuits 25, 17 in selectors 16 and 17.
26, and is supplied to a horizontal parity check circuit 27 and a vertical parity check circuit 28. If an error is detected in the desired data bit information, the output of the gate 8 becomes "1", and the data bit information is inverted or corrected at the gate 9 and output.

As described above, in this conventional example, the selectors 10 and 1 necessary for error correction of desired data bit information are
It is necessary to provide a dedicated selection signal generation circuit for 3-1 to 13-m, and therefore the circuit area occupied between the data bit lines or outside the data bit lines becomes extremely large, so it is necessary to reduce the circuit area. There was a problem with this.

The present invention has been made in view of the above-mentioned conventional drawbacks, and an object of the present invention is to provide a semiconductor memory device with a reduced circuit area.

Structure of the Invention In order to achieve the above object, the present invention divides the selection signal to be supplied to the selector in order to correct errors in desired data bit information into two blocks, an upper bit group and a lower bit group, by an address decoder. Then, the decoder output of the block whose input is the lower bit group is used as the selection signal of the horizontal group selector,
The decoder output of the block whose input is the upper bit group is used as the selection signal of the vertical group selector, and the AND signal of the decoder output of the block whose input is the lower bit group and the decoder output of the block whose input is the upper bit group. By using this as the selection signal of the multiplexer, a dedicated selection signal generation circuit for the selector is not required.

Embodiment of the Invention First, the principle of an embodiment of the present invention will be explained with reference to FIG. FIG. 3 shows a one-dimensional array of 16 pieces of data bit information and 8 pieces of parity bit information shown in FIG. 1b. In the figure, A ₀ -A ₃ are address decoder input signals specifying desired data bit information.

In FIG. 3, if we take advantage of the characteristics of the input signal pattern of the address decoder that specifies the data bit information of data and the parity bit of
It is possible to correspond to a desired horizontal bit group or vertical bit group, and therefore it is possible to use the decode signal as a selection signal for selecting a horizontal or vertical bit group. For example, to select the horizontal bit group consisting of A, B, C, and D, it is sufficient to set the upper bits of the address decoder input, that is, A ₂ and A ₃ to "00"; Li,
To select a vertical bit group consisting of 0, the lower bits of the address decoder input, ie, A ₀ and A ₁ , may be set to "00".

Also, other horizontal bit groups [H, H, G, CH],
[ri, nu, ru, wo], [wa, ka, yo, ta] and other vertical bit groups [ro, he, nu, ka], [c, t,
Similarly, ru, yo], [d, chi, la, ta] are A ₂ , A ₃
and can be uniquely associated with the characteristics of the patterns A ₀ and A ₁ . Therefore, the address decoder is divided into two blocks: a block that receives the lower bits A ₀ and A ₁ as input, and a block that receives the upper bits A ₂ and A ₃ as input, and each decode signal selects a horizontal or vertical bit group. It becomes possible to use it as a selection signal.

Although the above principle has been explained in the case of a 4.times.4 bit memory cell, it can also be applied to a general K.times.m bit memory cell.

An example of a K×m bit cell using the principle of FIG. 3 is shown in FIG. In the figure, the same components as in FIG. 2 are given the same reference numerals as in FIG. 2. That is, in FIG. 4, 1 is a memory cell section composed of memory cells 4 for storing information, 2 is a horizontal parity cell section composed of horizontal parity cells 5, and 3 is a vertical parity cell section composed of vertical parity cells 6. These 2 and 3 constitute a memory cell section for inspection and correction. 7 is word line, 10,1
8 is a selector for selecting horizontal or vertical data bit line information group; 16 and 17 are selectors for selecting horizontal or vertical parity bit line information; 29
is an address decoder, and 30 is a two-input AND gate to which bit line information and selection signals are input. In this configuration, there are (K×m) data bit lines and (K
+m) parity bit lines are provided. In addition, A ₀ to _{A i-1} , A _i , A _i+1 shown on the left side of the figure
~A _l indicates the address of the desired data bit line.

In this embodiment, the horizontal data bit line information group forms m groups in units of K bits, with addresses having the same upper bits A _i to _{A l} being grouped. Therefore, the selection signal of the selector 10 for selecting the horizontal data bit line information group may be a decode signal of the address upper bits A _i to _{A l} .

Further, the vertical data bit line information group forms K groups in units of m bits, with bits having the same address lower bits A ₀ to _{A i -1} being grouped.
Therefore, the selection signal of the selector 18 for selecting the vertical data bit line information group is the address lower bit _A0.
A decoder signal of ~A _i-1 is sufficient.

Similarly, the selection signals of selectors 16 and 17 for selecting horizontal and vertical parity bit line information are the upper address bits A _i to _{A l} or the lower bits A ₀ to _{A i}
This can be realized with a ₋₁ decoded signal. In order to generate these decoded signals, it is sufficient to separate the address into upper bits and lower bits in the address decoder and generate decoded signals for each.

Next, FIG. 5 shows the relationship between the selector multiplexer and address decoder focusing on an arbitrary data bit line in FIG. 4.

In FIG. 5, 10 is a selector for selecting a horizontal bit line information group, 18 is a selector for selecting a vertical bit line information group, 19 is a multiplexer, 29 is an address decoder, and 29a is an address lower bit A ₀
29b is the second block of the address decoder which receives address _upper bits A _i -A _l as input, 3
0 is the data bit line, 31 and 32 are the output lines of the selectors 18 and 10, respectively, 33 is the output line of the multiplexer 19, 34 and 35 are the first block diagram of the address decoder, and the output lines of the second block, 40-
43 is a two-input AND gate.

As described above, the decoded signals of the decoders 29a and 29b, which receive the divided addresses into two, are used as selection signals of the selectors that select the horizontal and vertical bit line information groups. Therefore, output 3 of 29a
4 is the selection signal of the selector 18, and the gate 40
Similarly, output 35 of 29b is input to selector 1.
It is input to the gate 41 as a selection signal of 0. Further, the logical product of the outputs 34 and 35 is taken by a gate 43, and the result is inputted to the gate 42 as a selection signal for the multiplexer 19.

As described above, when each selection signal becomes "1", data bit line information is transmitted to the output of each selector and multiplexer. With this configuration, although the circuit area of the address decoder is slightly increased, the dedicated selection signal generation circuit for each selector, which was conventionally required, can be omitted, so that the circuit area can be significantly reduced.

Effects of the Invention As explained above, the present invention provides a semiconductor memory device having a self-correcting circuit that automatically corrects bit errors occurring in a memory using an error correction code, in which a selector selection signal is generated from an address decoder. Because of this configuration, there is an advantage that the dedicated selection signal generation circuit for the selector, which was conventionally necessary, can be omitted and the circuit area can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of a horizontal/vertical parity check code, FIG. 2 is a configuration example of a conventional self-correcting memory using the principle of FIG. 1, and FIG. 3 is a principle diagram of an embodiment of the present invention. FIG. 4 is a block diagram of one embodiment of the present invention, and FIG. 5 is a block diagram showing the relationship among the selector, multiplexer, and column decoder focusing on one data bit line in FIG. 4. a...Horizontal parity bit, b...Vertical parity bit, 1...Memory cell section, 2...Horizontal parity cell section, 3...Vertical parity cell section, 4...Memory cell for information storage, 5...Horizontal parity cell, 6...Vertical parity cell, 7...Word line , 8...2-input AND gate, 9...2-input EOR gate, 10, 11, 13
-1 to 13m, 16 to 18... Selector, 19... Multiplexer, 20 to 26... Dedicated selection signal generation circuit for selector, 27, 28... Parity check circuit, 29... Address decoder, 30... Data bit line, 31... Output line of selector 18, 32... Output line of selector 10, 33... Multiplexer 19
output lines, 34, 35...output lines of address decoder, 40-43...2-input AND gate.

Claims (1)

[Claims] 1. On the same word line, a plurality of information storage memory cells that form horizontal and vertical parity codes, a memory cell for inspection and correction, an address decoder that specifies the information storage memory cell during reading and writing, and a A selector that selects an information storage memory cell and an inspection/correction memory cell based on a supplied selection signal, a multiplexer that selects information in an information storage memory cell during reading and writing, and a bit selector of an information storage memory cell. In a semiconductor memory device equipped with a self-correction circuit that corrects errors, an address decoder is divided into two blocks, an upper bit group and a lower bit group, and the decoder output of the block whose input is the lower bit group is used as a selection signal for a horizontal group selector. Then, the decoder output of the block whose input is the upper bit group is used as the selection signal of the vertical group selector, and the decoder output of the block whose input is the lower bit group and the decoder output of the block whose input is the upper bit group are ANDed.
A semiconductor memory device characterized in that a signal is used as a selection signal of a multiplexer.