JPS59213100A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To eliminate a private selecting signal generating circuit of a selector to reduce the circuit area by constituting a device so that a selecting signal of the sensor is generated from an address decoder. CONSTITUTION:Decoded signals of decoders 29a and 29b to which an address divided into two is inputted are used as the selecting signal of the selector which selects horizontal and vertical bit line information groups. Consequently, an output 34 of the decoder 29a is inputted to a gate 40 as the selecting signal of a selector 18, and similarly, an output 35 of the decoder 29b is inputted to a gate 41 as the selecting signal of a selector 10. AND between outputs 34 and 35 is operated in a gate 43 and is inputted to a gate 42 as the selecting signal of a multiplexer 19. When individual selecting signals become ''1'', data bit line information is transmitted to outputs of these selectors and multiplexer. By this constitution, the private selecting signal generating circuit of each selector is eliminated to reduce the circuit area though the circuit area is slightly increased with respect to the address decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device having an error correction function.

Prior Art and Problems Conventionally, as a semiconductor memory device equipped with an error correction function, a device having a structure that performs horizontal and vertical parity checks on multiple memory cells connected to a common word line was proposed in a patent application filed in 1973.
No. 6-37223. FIG. 1 is an explanatory diagram of its principle, in which horizontal parity pits (f a) and vertical parity pits (11b) for 16 data bits arranged on a 4x4 matrix are shown. Here, the data bit and the property bit a, blc Fig. 1 (, )
By moving the matrix as shown by the broken line, the two-dimensional matrix can be converted into a one-dimensional matrix as shown in FIG. 1(b). Therefore, among the 24 bits in the one-dimensional matrix in Fig. 1(b), an error in any one bit in the upper 16 pits can be compared with the parity pits in the lower 8 bits for each group shown by the solid line in the figure. Yoruru,
Erroneous sibit positions can be detected.

Therefore, even if a fixed defect or a non-fixed defect occurs in any one of the upper 16 bits, the defective pit position can be detected and error correction can be easily performed. .

An example of the configuration of a conventional self-correcting memory using the principle of FIG. 1 is shown in FIG. FIG. 2 shows a self-correcting memory when the data bit width is 1 bit. In the figure, 1 is a memory cell section made up of memory cells 4 for storing information, and 2 is a horizontal harness cell section made up of horizontal parity cells 5. , 3 is a vertical parity cell section composed of vertical parity cells 6, and these 2 and 3 constitute a memory cell section for inspection and correction. 7 is a word line, 8 is a two-man AND gate, 9 is a two-man EOR gate, 10 is a selector that selects a bit from among (KXm) data bit line information, 11.13-1 to 13
-m, 17 is a selector that selects one bit from among bit line information, and 16 is a selector that selects one bit from among m pieces of bit line information.
A selector for selecting bits, 20 to 26 are selection signal generation circuits for each selector, and 27 and 28 are horizontal or vertical parity check circuits. Further, K indicates the number of vertical bit line groups, and m indicates the number of horizontal bit line groups. In this conventional example, the data bit line is (J(Xm
), the horizontal and vertical parity lines are (K0m)
Consists of books.

(K x tn ) data bit lines form horizontal parity bit information on a bit-by-bit basis, so they are grouped on a K-bit basis to form data bit line groups of a total of K bits. In addition, since the (KXtrL) data bit lines form vertical parity bit information in units of bits, they are grouped in units of bath bits to form groups of vertical data bit lines. Then, one horizontal parity bit line corresponds to one group of horizontal data bit lines for forming horizontal parity bit information, and one group of data bit lines corresponds to one group for forming vertical parity bit information. A vertical parity bit line is provided for each data bit line group and receives test information for each data bit line group.

In this conventional example, the data bit information group to which the desired data bit information for performing horizontal parity check and vertical parity check belongs is selected by selector 10.13.
-1 to 13-, respectively, are selected according to the selection signals generated by the dedicated selection signal generation circuits 20.22-1 to 22-, and the horizontal parity check circuit 27.
．． The signal is supplied to the vertical parity check circuit 28.゛Horizontal parity bit information and vertical parity bit information regarding desired data bit information are also sent to the selector 16.1.
7, the selected signal is selected according to the selection signal generated by the selection signal generation circuits 25 and 26, and is supplied to the horizontal parity check circuit 27 and the vertical parity check circuit 28.

If an error is detected in the desired data bit information, the output from the gate 8 becomes "1", and the data bit information is inverted or corrected at the gate 9 and output.

As described above, in this conventional example, if the desired data bit information is
Selectors 10.13-1 to 13- necessary for making corrections
Since it is necessary to provide a dedicated selection signal generation circuit for each data bit line, the circuit area occupied between the data bit lines or outside the data bit lines becomes extremely large, which poses a problem in terms of reducing the circuit area. .

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the conventional art, and it is an object of the present invention to provide a semiconductor memory device with a reduced circuit area.

Structure of the Invention The present invention achieves the above object by configuring the address decoder to generate a selection signal to be supplied to the selector in order to correct errors in desired data bit information. The selection signal generation circuit is completely unnecessary.

Embodiment of the Invention First, the principle of an embodiment of the present invention will be explained with reference to FIG. Figure 3 shows the data bit information 1 shown in Figure 1 (b).
It is a one-dimensional array of 6 bits and 8 pieces of parity bit information. In the figure, Ao-A5 is an address decoder input signal that specifies all desired data bit information.

In Fig. 3, by taking advantage of the characteristics of the input signal pattern of the address decoder that specifies the data bit information (A) to (I) and the parity bits (0 to @), it can be made to correspond to a desired horizontal bit group or vertical bit group. It is possible,
Therefore, it is possible to use the decode signal as a selection signal for selecting a horizontal or vertical bit group. For example, (
To select the horizontal bit group consisting of (a), (b), (c), and (b), it is sufficient to set the upper bit of the address decoder input, that is, "% A2 t As t""00"; ), (e), (su), and ('7), the lower bits of the address decoder input, that is, A.+A1'fc''00'' may be set.

Also, other horizontal bit groups [(→, (to), (g), (to)], [(su)].

(2 mouths, ni), (b)], [(2 mouths, (2), (→, (
B)] and other vertical bit groups [(B), (F),
Qtsu, around Q], [(ha), ()), Clsu, (yo)]
, [ni), e9゜(,'), @), I are similarly A2.
It is possible to uniquely associate it with the characteristics of the patterns A3, Ao, and AH.

Therefore, the address decoder is changed to the lower bit Aa + Ai
It is possible to divide the circuit into two blocks: a block that receives k inputs and a block that receives upper bits A2 and A3 as inputs, and each decode signal can be used as a selection signal for selecting a horizontal or vertical bit group.

Although the above principle has been explained for the case of a 4×4 bit memory cell, it can also be applied to a general KXm bit memory cell.

An embodiment of a K X tn bit cell using the principle of FIG. 6 is shown in FIG. In the figure, the same components as in FIG. 2 are given the same reference numerals as in FIG. 2.

That is, in FIG. 4, 1 is a memory cell section made up of memory cells 4 for storing information, 2 is a horizontal parity cell section made up of horizontal parity cells 5, and 3 is a vertical parity cell section made up of vertical parity cells 6. Rashi in the cell part, these 2 and 3
constitutes a memory cell section for inspection and correction. 7 is a word line, 10.18 is a selector for selecting a horizontal or vertical data bit line information group, 16.17 is a selector for selecting horizontal or vertical parity bit line information, 29 is an address decoder, and 30 is a selection of bit line information. A two-man AND gate with a signal as input. In this configuration (KX
m) data bit lines and CK+rn) harness bit lines are provided. Also, A shown on the left in the figure
o~Ai-tr Ai+A←1~Aμ indicates the address of the desired data bit line.

In this embodiment, the horizontal data bit line information group forms groups of K bits each having the same address upper bits Ai to Afl. Therefore, the selection signal of the selector 10 for selecting the horizontal data bit line information group may be a decode signal of the upper address bit (At-Afl).

For the vertical data bit line information group, those with the same address lower bit A o = A i-+ are grouped,
Form groups in bit units. Therefore, the selection signal of the selector 18 for selecting the vertical data bit line information group may be the decode signal of the lower address bit (An-A).

Similarly, the selection signals of selectors 16 and 17 that select horizontal and vertical parity bit line information are the address upper hit A.
This can be realized by decoding signals of i-A°C or lower bits Ao to A1. In order to generate these decoded signals, it is sufficient to separate the address into upper bits and lower bits within the address decoder and generate decoded signals for each.

Next, FIG. 5 shows the relationship between the selector multiplexer and address decoder focusing on an arbitrary data bit line in FIG. 4.

In FIG. 5, 10 is a selector for selecting a horizontal bit line information group, 1B is a selector for selecting a vertical bit line information group, 1
9 is a multiplexer, 29 is an address decoder, 29
eL is the first block of the address decoder which receives the lower address bits Ao to At-1 as input.

29b is the second block of the address decoder which inputs the address upper bits Ai-Aflf, 30 is the data bit line, and 31.32 is the selector 18.10, respectively.
, 63 is the output line of the multiplexer 19, 34
．． 35 is the output line of the first block and second block of the address decoder, and 40 to 43 are two-manual AND gates.

As described above, the decoded signal of the decoder 29a+b inputted with the address divided into two is used as the selection signal of the selector for selecting the horizontal and vertical bit line information groups. Therefore, the output 34 of 29a is input to the gate 40 as the selection signal of the selector 18, and similarly the output 35 of 296 is input to the gate 41 as the selection signal of the selector 10.

In addition, the logical combination of the outputs 34 and 35 is processed by the gate 43 and is inputted to the gate 42 as a selection signal of the multiplexer 19.

As described above, when each selection signal becomes 1", data bit line information is transmitted to the output of each selector and multiplexer. With this configuration, although the circuit area of the address decoder is slightly increased, Since the necessary selection signal generation circuit dedicated to each selector can be eliminated, the circuit area can be significantly reduced.

FIG. 6 is a block diagram of another embodiment of the present invention, which is a self-correcting memory using a Mink code as an error correction code. In the figure, 1 is a memory cell section composed of memory cells 4, 7 is a word line, 29 is an address decoder, 29
α is the lower bit A of the address.

~Ai-+f, the first block of the address decoder as input; 29b; the second block of the address decoder as input; 29b; 2 blocks of output lines, 51 is a parity cell section composed of parity cells 54, 60 is a selector that selects one data bit line information from (IxN) pieces of data bit line information, 61 is (JXN) 62 is a selector that selects one data bit line information from among one data bit line information; 65 is a self-correction circuit; It comes out. I represents the number of data bit lines forming the Hamming code, J represents the number of parity bit lines forming the No-Mink code, and N represents the number of No-Mink code groups formed per word line.

In this embodiment, data bit lines (IxN).

It consists of parity bit lines (,7xN).

(1”IN) data bit lines are configured as data bits forming a norming code in I bit units, so N data bit line groups are configured in I bit units. 1 for each group corresponding to the N groups of data bit lines to be formed.
Two parity bit lines are provided, each receiving check information for data bits within a group in units of J bits.

Correcting a desired data bit requires all the bits of one group (one data bit information and one parity bit information) forming the Hamming code to which the data bit belongs.

Therefore, in this embodiment, the data bit lines forming the Hamming code form N groups in units of I bits, with those having the same address upper bits A (~Aλ) forming a group. A decode signal of Al to At may be sufficient. Furthermore, since the parity bit line group corresponding to the data bit line group forms N groups in units of J pits,
Similarly, the selection signal of the selector 61 is the address upper pin)A.
(It can be realized by the decode signal of ~Al. Then, one data bit line information selected by the selector 60゜61 and one
pieces of harrity bit line information are input to the self-correction circuit 65, and based on this information, one data bit line information is corrected simultaneously. Selector 62 selects desired data bit line information from among the corrected pieces of data bit line information. Further, the selection signal of the selector 62 can be realized by a decode signal of the address lower bits AO to At-H.

As mentioned above, the selection signal of each selector is a) Separate the address into upper bits and lower bits in the 'V Suff' coder,
Since it is sufficient to use each decode signal, the selection signal of the selectors 60 and 61 is the address upper bit At.
~Second block 2 of address decoder with Aλ as input
The output of the selector 9-b is set to 4, and the selection signal of the selector 62 is set to be the output of the first block 29-8 of the address decoder in which the lower address bits AO to At-t t- are manually input. Although this configuration slightly increases the circuit area of the address decoder, it is possible to eliminate the dedicated selection signal generation circuit for each selector, thereby significantly reducing the circuit area.

Effects of the Invention As described above, the present invention provides a semiconductor memory device having a self-correction circuit that automatically corrects bit errors occurring in a memory using a correction code. Since the configuration is such that the generation is performed from the gold address decoder, there is an advantage that the dedicated selection signal generation circuit for the selector, which was conventionally necessary, can be omitted and the circuit area can be reduced.

Note that although the above explanation describes the effects of self-correcting memory to which horizontal and vertical parity check codes and Hamming codes are applied, similar effects can be obtained with self-correcting memories to which other error-correcting codes are applied. .

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle of horizontal and vertical parity check codes, Figure 2
The figure shows a configuration example of a conventional self-correcting memory using the principle of Fig. 1, Fig. 6 is a principle diagram of an embodiment of the present invention, Fig. 4 is a block diagram of an embodiment of the present invention, and Fig. 5 4 is a block diagram showing the relationship among the selector, multiplexer, and column decoder focusing on one data bit line, and FIG. 6 is a block diagram of another embodiment of the present invention. a...Horizontal parity pit, b...Vertical parity bit, 1...Memory cell section, 2...Horizontal parity cell section, 3...Vertical parity cell section, 4...For information storage Memory cell, 5...Horizontal parity cell, 6...Vertical parity cell, 7...Word line, 8...2 Manual power A
ND Gate, 9...2-person EOE game), 10.1
1.13-1 to 13-rn, 16 to 18...Selector, 19...Multiplexer, 20 to 26...Selection signal generation circuit dedicated to selector, 27.28...Parity check circuit, 29 ...address decoder, 60
...Data bit line, 31...Output line of selector 18, 32...Output line of selector 10, 63...Output line of multiplexer 19, 54.55...Output line of address decoder, 40 ~43...Two-man power AND gate, 51...Parity cell unit, 54...Parity cell, 60-62...Selector, 65...Self-correcting circuit patent applicant Nippon Telegraph and Telephone Public Corporation agent patent attorney Shitama Mushiku Gobu (3 others)

Claims (1)

[Claims] A plurality of information storage memory cells, an address decoder that specifies the information storage memory cell during reading and writing, and a plurality of inspection/correction memories that store information for inspecting and correcting pit errors in the information storage memory cells. A selection signal supplied to the selector in a semiconductor memory device comprising a selector and a self-correction circuit that selects a memory cell for information storage and a memory cell for inspection/correction based on a selection signal supplied during reading and writing of the cell. is generated by an address decoder.