JPS62248198A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the size of the scale of an additional circuit by controlling a selecting switch so that the groups adjacent to memory cells and the groups adjacent to inspection cells of a semiconductor memory having a self-correcting function do not belong to the same horizontal/vertical group. CONSTITUTION:The titled device is constituted so that the cells in the four adjacent cell groups C1-C4, C5-C8, C9-C12, and C13-C16 belong to different horizontal/vertical groups. In case the cell information in the cell C6 is the object of correction, the cell information in the C2, C10, and C14 belonging to the same horizontal group are selected by a horizontal group selecting switch 10', and transmitted to nodes N12-N15. Similarly, the cell information in the C3, C9, and C16 belonging to the same vertical group with the cell C6 are selected by a vertical selecting switch 11', and transmitted to nodes N16-N19. Thereafter, a horizontal/vertical group parity check is executed with the cascade connection circuits of a one-input parity circuit 8, and by means of a resulting combination, the data from the output node N23 of a multiplexer 7 is corrected and outputted. In such a constitution, the size of the scale of an additional circuit can be made smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory having a self-correction function that automatically corrects bit errors within the memory.
In particular, the present invention relates to a self-correcting semiconductor memory that can reduce the scale of an additional circuit for error correction and contribute to improving manufacturing yield.

[Conventional technology]

A semiconductor memory having a self-correcting function to correct bit errors within the memory (referred to as self-correcting memory) is a semiconductor memory device in which horizontal and vertical parity codes are applied to multiple memory cells connected to one word line. (Japanese Patent Application No. 56-37223, Japanese Patent Application Laid-open No. 57-152597) and an improved structure (Japanese Patent Application No. 59-86930) that enables high-speed error correction operations have been proposed. An example of this improved configuration is shown in FIG. 3 (!L), and the correction principle is shown in FIG. 3 (b). Here, 1 is a memory cell, 2 is a parity cell that stores inspection information of memory cell information, 3 is a word line, 4 is a bit line, 5 is a parity bit line for the parity cell, 6 is a column decoder, and 6-1 is a Column address A.

r A lower column decoder to which AI is input, 6-2 is a column address Ax, 4 is an upper column decoder to which is input, 7 is a multiplexer, 8 is two reference voltages 1H"
9 is a horizontal group parity check circuit including 10 horizontal group selection switches, 1) is a vertical group selection switch, and 12 is one horizontal group selection switch. , 15 indicates one vertical group, p, INVj is an inverter, ANDi is an AND gate, and EORl is an exclusive OR gate.

Further, 01 to C16 indicate cell numbers.

First, the correction principle will be explained using FIG. 3 (b>). Seven parity cells 2 are prepared for nine memory cells 1, Parity cell information is stored in each parity cell so that even parity is established in each horizontal group and each vertical group.In this state, for example, 12 horizontal groups and 13 vertical groups shown in the figure are stored. If the parity of the group is checked and both parity results are 1)'', that is, a parity error has occurred, this means the tab of memory cell information located at the intersection of the 12th horizontal group and the 13th vertical group, so this Bit errors can be corrected by inverting the information.

A total of 16 cells are connected to one word line 3 as shown in FIG. The horizontal group selection switch is selected using the vertical group selection switch 1), and each parity check is performed by a cascaded circuit of one-person coverage circuits indicated by 8゛, and the result is obtained by the multiplexer 7. By correcting the output information to be corrected, the self-correcting semiconductor memory shown in FIG. 8 (8) can be obtained. In this improved configuration, a one-person coverage circuit, designated 8, i.e., node N1
, N2 and nodes #3 and N4 are connected to transistors Q+ and Qt using the input signal and its complementary signal.
, Qs - Q4 are used to cascade the circuits to be exchanged, and by arranging these circuits on pin M, a selector for selecting one horizontal group and one vertical group and a parity check for each group are performed. It is possible to integrate a parity check circuit for this purpose, which not only increases the speed of circuit operation but also reduces the size of additional circuitry.

[Problem that the invention seeks to solve]

However, in such a configuration, it is necessary to provide a one-person coverage circuit for each bit line to configure the horizontal group parity check circuit shown in 9. EA of
When applied to M, there was a problem with Louis Out. Furthermore, a horizontal group selection switch indicated by 10 is present;
Also, due to differences in wiring length between one-person coverage circuits, etc.
The speed balance between the horizontal group parity check and the vertical group parity check is not good, which is a factor that prevents speeding up of the error correction operation.

Further, in this configuration, since it is possible to correct only one bit error within the same code group that occurs in the word line, there is a drawback that, for example, defects in the word line system that occur during manufacturing cannot be repaired.

[Means for solving problems]

In order to eliminate these drawbacks, the present invention provides a system in which each of a plurality of memory cells and test cells located physically adjacent to each other is grouped in units corresponding to the number of pits forming one horizontal group or one vertical group. Horizontal group parity check and vertical group parity check are realized with exactly the same circuit configuration by controlling the horizontal group and vertical group selection switches so that the horizontal group and vertical group do not belong to the same horizontal group and vertical group. Furthermore, by adding redundant word lines, defects in the word line system can also be relieved.

[For production]

According to the basic configuration of the present invention described above, it is possible to provide a highly reliable and high-yield semiconductor memory having a small-scale, high-speed error correction circuit. Further, in the conventional structure, it is difficult to add a means for relieving word-related defects due to the complicated structure and layout problems, etc., but it is possible to easily add means for relieving word-related defects.

〔Example〕

FIG. 1 is an explanatory diagram of the principle that makes the present invention possible, (eL
) is a diagram in which nine memory cells 1 and seven parity cells 2 are connected to one word line 3, and cell numbers C1 to C16 are assigned according to their physical positions. Figure (b) is an example in which these 16 cells are expanded into a two-dimensional logical address space so that the same horizontal group and the same vertical group can be easily identified. This expansion method is the key to the present invention. . Looking at this figure (6), in the same figure (cL) there are four physically adjacent cell groups, namely C1~04.05~
CB, C9-CA2. In each group C15-C16, four cells belong to separate horizontal and vertical groups. When a horizontal group and a vertical group are formed in this configuration, the selection of the horizontal group and vertical group to which the cell to be corrected belongs is one from C1 to C4, and one from C5 to C4.
One from C8, one from C9 to C12, C15
-C16, one cell information is selected. For example, if the cell information of C6 in FIG. 6(b) is to be corrected, 1
2 horizontal group, i.e. (:'14. C2, C6, C10) and 13 vertical group, i.e. C9° C3, C16, the cells to be selected are the four cells mentioned above. Since there is one in each cell group, the horizontal group selection switch and the vertical group selection switch can be configured in exactly the same way.Furthermore, FIG. At the same time as (6) in the same figure, C1~
C4,05~CB, 09~(1'12.C15~C
This is an example in which each cell within 16 individual cell groups belongs to a separate horizontal and vertical group. In this example, the parity cells are C4, C5, C7, C1), C12, C1
5, C16 and the parity cell in (a) of the same figure, that is, C
4, C7, CB, C10, CI2°C13, CI6. Thus, it is clear that there are many other types of horizontal group and vertical group selection logic that would enable the present invention. FIG. 2 shows an embodiment of the present invention, which is based on the selection logic of FIGS. 1(a) and (b). 1-8. ．． 4#DI.

EORl is the same as in FIG. 3, 10' is a horizontal group selection switch, 1)' is a vertical group selection switch, 1' is an extra memory cell, 2' is an extra test cell, and 5' is an extra memory cell uniformly connected to 06
The operation of the two circuits will be explained by taking as an example the case where the cell information is to be corrected. C2. which belongs to the same horizontal group as the cell information of C6.
(:'10. The cell information of C14 is selected by the horizontal group selection switch 10' by the lower column decoder output A, ^ shown by 6-1, and the cell information of C14 is selected by the horizontal group selection switch 10'.
.

N14. /Conveyed to V15. On the other hand, in exactly the same way, C3. C9,
The cell information of CA6 is selected by the vertical group selection switch 1)' by the As As output of the upper column decoder 6-2, and the cell information of CA6 is selected by the vertical group selection switch 1)'. #17. N18. #
19 will be informed.

After this, the horizontal group high IJ integrity check and the vertical group integrity check are performed in exactly the same way in the cascade connection circuit of the one-person coverage circuit shown at 8, and the data at the node N'23 of the multiplexer output at 7 is corrected by the combination. and supplies it to the output terminal. Comparing this configuration with Fig. 3 (α) of the conventional configuration, we can see that 16
In other words, only four coverage circuits are required for each bit line, and the parity check circuit can be implemented using the same type of circuit as the vertical group parity check, and even if the bit line pitch is reduced, the layout can be made sufficiently, and errors can occur. This greatly contributes to reducing the size of the additional circuit for correction. Furthermore, since the horizontal group parity check and the vertical group parity check can be achieved using the same circuit format, high-speed error correction with good speed balance is possible.

Further, in this embodiment, in addition to the error correction function, a defect relief function using surplus word lines is added. This operation is as follows. For example, the address of a defective word line found in a test during manufacturing is registered in the word line switching circuit shown at 14 by means such as a laser program or an electric fuse, and when used, the row address (Xo
-Xi) and the registered defective word line address, and if they match, normal memory operation is performed by selecting the surplus word line instead of the defective word line. This defect relief using the surplus word line does not reduce the error correction function of the present invention and its speed performance at all, so it is possible to realize a highly reliable and high-yield semiconductor memory with this defect relief function and error correction function. .

In FIG. 2 showing this embodiment, the column decoder is shown at the top for convenience of drawing, but it goes without saying that it can also be placed in the play area adjacent to the horizontal group or vertical group selection switch. If this is possible, it is also possible to construct a structure in which the logical product of the upper column decoder output and the lower column decoder output is taken as a column decoder output signal, and the signal is input to a multiplexer, thereby realizing a more compact self-correcting memory.

〔Effect of the invention〕

As described above, the present invention provides a self-correcting semiconductor memory in which a plurality of physically adjacent memory cells and test cells are grouped in units corresponding to the number of bits forming one horizontal group or vertical group. Since the horizontal group and vertical group selection switches are controlled so that each of This has the advantage that it is possible to reduce the size of the additional circuit by reducing the number of single-person coverage circuits, and to balance and speed up circuit operation by checking horizontal group and vertical group parity in the same circuit configuration.

Furthermore, the present invention has the advantage that not only high reliability but also high yield can be achieved due to the defect relief function of the redundant word lines.

[Brief explanation of drawings]

Figure 1 (α) (b) (6) is a diagram explaining the principle of the present invention, Figure 2 is a circuit diagram of an embodiment of the present invention, and Figure 3 (a) (b) is a conventional self-correcting semiconductor memory. FIG. 1...Memory cell 1'...Surplus memory cell 2...Parity cell 2'...Surplus parity cell 3...Word line 3'...Surplus word line 4...Bit line 5 ... Parity bit line 6 ... Column decoder 6-1 ... Lower column decoder 6-2 ... Upper column decoder 7 ... Multiplexer 8 ... One-person coverage circuit 9 ... Horizontal group parity check circuit 10 .10'
...Horizontal group selection switch 1). 1) '...
Vertical group selection switch 12...Horizontal group 13...Vertical group 14... Word line switching circuit Patent applicant Nippon Telegraph and Telephone Corporation representative Patent attorney 4 Kugobe (2 others) (G') Diagram for explaining the principle of the present invention Fig. 1 A configuration diagram of an embodiment of the present invention

Claims (1)

[Claims] (1) A plurality of memory cells that store information, a plurality of test cells that store test information for correcting bit errors occurring in the memory using horizontal and vertical parity codes, and the plurality of memory cells and the plurality of test cells. A word line for selecting a test cell, a bit line for exchanging information with the memory cell, a test bit line for exchanging information with the test cell, and a surplus memory connected to the bit line in the same way as the memory cell. a redundant test cell connected to the test bit line in the same manner as the test cell; a redundant word line for selecting the redundant memory cell and the redundant test cell; and a defective word line among the word lines to be connected to the redundant word line. In selecting the bit line information and check bit line information belonging to the horizontal group and vertical group in the code group to which the memory cell specified by the external address belongs, Alternatively, a plurality of memory cells and test cells that are grouped in units corresponding to the number of bits forming a vertical group and are physically adjacent to each other are selected so that they do not belong to the same horizontal group or the same vertical group. Switches using column decode signals whose logic is controlled and means for switching paths for transmitting two reference voltages "H" level and "L" level are connected in multiple stages, and a plurality of signals from the switches are input. 1. A semiconductor memory device comprising: means for performing a parity check; and an error correction circuit for correcting bit errors using an output of the means for performing a parity check.