JPS60168676A - Rule image generator - Google Patents

Abstract

PURPOSE:To enable to reduce memory capacity and to enhance processing speed, by synthesizing an output character pattern with rule image data sequentially generated by a rule image generator, with one dot as a unit, in a printer for a word-processor. CONSTITUTION:In the case of printing a rule, when a command signal CM and a printing data signal DT are externally supplied, a printing-controlling part 1 controls a raster image forming part 2 so as to print the printing data DT in the manner based on the signal CM containing the rule command, and switches line buffers L1, L2, thereby driving a printing part 3. A character pattern stored in a font memory in the part 2 and a rule pattern generated in the part 2 are sequentially synthesized with each other with one dot as a unit, and the synthesized information is sequentially outputted to the line buffers L1, L2 as raster information RD for each scanning line. When one of the line buffers L1, L2 is inputted with the information RD, the other outputs the information RD to the printing part 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a ruled line image generation device for generating ruled line image data without using a ruled line font in a word processor, a personal printer, a line printer, etc. Regarding.

[Prior art]

Conventionally, when generating image data (video data) of ruled lines in word processors, etc., various 7 types of ruled line data have been used.
The ruled lines were printed by storing the onts in a memory and reading out the required one from among the stored seven onts using a predetermined code.

However, in this conventional method, there are at least 11 ruled lines (-, l, r, 1.J) for one type of ruled line.

L, T, -1. +, top) font, and if you try to realize ruled lines with different line thicknesses, line types (solid lines, dashed lines, etc.), line lengths, etc., the number of fins increases dramatically, and this This leads to an increase in memory capacity or cost. Furthermore, in this method, when one font is accessed, margin bits other than the bits in which ruled line data 2 are written must also be accessed, which results in wasted processing time.

[Purpose of the invention]

This invention was made in view of the above circumstances, and aims to reduce the amount of memory by realizing arbitrary ruled lines, especially horizontal broken lines with arbitrary printing cycles, without using 7 onts for ruled lines, and to achieve high-speed processing. The object of the present invention is to provide a possible ruled line image generation device.

[Structure of the invention]

The present invention is applied to a printer that performs printing by rask scanning for each scanning line. In this invention, various character patterns stored in a font memory are sequentially output dot by dot in accordance with input character information, and the output character patterns are combined with ruled line images generated sequentially for each dot in a ruled line image generation device. The data are combined dot by dot to create raster image data to be sent to the printer.

The specific configuration of the ruled line image generation device includes a first memory having a storage capacity corresponding to the number of dots for at least one lifetime scanning line, and into which horizontal ruled line image data generated when a write enable signal is input is written. an image buffer; a second image buffer having a storage capacity corresponding to at least the number of dots for a lifetime scanning line; and a second image buffer in which generated image data for vertical ruled lines is temporarily stored; an input/output port with a predetermined number of bits to which black data is stored, and sequentially transfer the black data in units of the predetermined number of bits from the input/output port to the first or second image buffer using a DMA method. When a horizontal broken line is specified, a write pulse signal generated in synchronization with data transfer in units of the predetermined number of bits of the DMA controller is intermittently selected and extracted according to preset selection contents. and sets a data transfer start address and a data transfer length corresponding to the input ruled line command information to the write control means and the DMA controller, and inputs the data transfer start address and data transfer length to the write enable signal terminal of the first image buffer. and control means for reading horizontal ruled line image data temporarily stored in the first or second image buffer a required number of times in accordance with the ruled line command information. Depending on the transfer mode of the black data from the input/output port to the first or second image buffer by the DMA controller, a basic image gloss pattern in the main scanning direction of horizontal ruled lines or vertical ruled lines to be printed, respectively. and the width of the horizontal ruled line to be printed is changed depending on the reading mode of the image data for the same horizontal ruled line or vertical ruled line stored in the first image buffer or the second image buffer by the control means, respectively. I am trying to change the line length and line type of vertical ruled lines. Furthermore, since the write control means can intermittently select and extract the write enable signal input to the first image buffer in an arbitrary manner, it is possible to print various horizontal broken lines as desired. Become.

〔Example〕

Hereinafter, the present invention will be described in detail according to embodiments shown in the accompanying drawings.

FIG. 1 shows the overall configuration of a printer device to which a ruled line image generating device of the present invention is applied.

Command signal CM and print data signal D input from a host computer or an external device such as an input/output device
T is input to the print control section 1 and the rask image printing section 2 in this printer device.

If ruled lines are to be printed, the command signal CM includes a ruled line command. The print control section 1 controls the rask image printing section 2 to print the print data DT in a manner based on the command signal CM, performs switching control of the liner 177 Ll + LM, and further controls the pivoting of the printing section 3. Do the following.

The rask image creation part 2 will be described in detail later, but the character pattern recorded in the font memory in the rask image creation part 2 and the ruled line arm turn generated in the rask image creation part 2 are sequentially created dot by dot. The data are combined and sequentially output to line buffers L1 and L2 as raster information RD for each scanning line. Line buffer L+, Lzld2 line buffer S is configured, and when raster information RD is input to one line buffer, the other line buffer prints the raster information RD of the previous scanning line that has already been input and outputs it to 113. is in a state of The printing unit 3 actually prints the raster information input from the line buffer onto the recording medium.

FIG. 2 shows an example of the internal 4'fli construction of the rusk image production bottom part 2, which is the main feature of the present invention.

The command signal CM and data (tK number DT) input from the external device 6 are input to the control device tlO in the task image creation section 2. Identification bits for ruled lines and vertical ruled lines, ruled line printing start position (x, y), ruled line printing end position (X/ , Y/ ), pits that specify line types such as broken lines and solid lines, and bits that specify line thickness. etc. are included.

The control device 10 and other components are coupled via a data bus DB, an address bus AB1, and a control path (not shown). The font memory 20 stores characters such as alphabets, numbers, and kanji characters so as to correspond to their actual shapes. The read character data and the character image buffer 4 are sent via the path selector 30.
Enter 0. The character image buffer 40 has a capacity to temporarily store image data for at least one raster line, and temporarily stores character data sequentially input from the font memory 20 for each raster line. , the temporarily stored character data is
pS via the bus selector 30 under the control of
(/#RAL/LE/SERIAL) is output to the converter 55.

Next, regarding the configuration for generating a ruled line image, first of all, the horizontal ruled line image buffer 41 has a capacity that can temporarily store horizontal ruled line image data corresponding to at least one raster line segment, and has a capacity that can temporarily store horizontal ruled line image data corresponding to at least one raster line segment. The horizontal ruled line data transferred from the port 60 in 1-byte units is stored in a predetermined area according to a designated address. Similarly, the vertical ruled line image buffer 42 has a capacity that can temporarily store vertical ruled line image data corresponding to at least l raster line segments, and the vertical ruled line data is transferred from the I10 boat 60 in 1-byte units. is stored in a predetermined area according to the specified address. Each of these image buffers 7
40.4], 42 and each lead-in enable terminal are provided with enable signals ENo and E, respectively.
Nl*FJNz and write enable signal WE6
r WEl * WB2 are each input,
Each image buffer 40, 41, 42 becomes active when enable signals EN6 + VNH, ErN@ are input, and enable signals EN, EN, IN and write enable signal WR6*WRI*
When both WRl are input, each enters a writable state.

Next, x7on-) 60 consists of one byte, and black data is set by the control device 10 when creating a ruled line image. This 1-byte black data has a line length of approximately 1 m in terms of the printing portion.

Ilo d? -) DMA (
Dynamic memory access) is executed at high speed by the controller 70.

The DMA controller 70 is a well-known DMA device for high-speed data transfer, and when there is a DMA request from the control device 10, it starts a DMA operation after holding the control device 10. The DMA controller 70 and the control device 10 are path-connected via a tri-state buffer (not shown), and the tri-state buffer allows the control device IO to control the data bus DB and address bus AB when the DMA controller 70 operates. It is designed to be suitably separated from the When a ruled line command is detected in the command signal, the control device 10 issues a DMA request to the DMA controller 70, and also outputs the print start position g(x, y) and print end position (x/, y) in the ruled line command.
/ ) and sets the data transfer start address and transfer byte length corresponding to the DMA controller 70 . Also,
When a horizontal broken line is designated, the horizontal broken line designation signal SL is set to a high logic level, and when a horizontal solid line is designated, the signal SL is set to a low level.

After this, the DMA controller 70 holds the control device 10 and disconnects it from the bus, and then, based on the data transfer start address and transfer byte length, l10s=-)60
The black data is transferred at high speed to the image buffer 41 for horizontal ruled lines or the image buffer 42 for vertical ruled lines.

Next, the write signal control section 80 sets the 1 write enable 4Fv to each image buffer 40, 41.42.
This is a circuit that outputs numbers WE6, WEI, and WB2,
FIG. 3 shows an example of its internal configuration. The configuration shown in FIG. 3 is particularly for controlling the write enable signal WE of the horizontal image buffer 41. In FIG. 3, 4? of the DMA controller 70? The pulse WR (see FIG. 4(a)) is input to the AND/DART 81, and is also input to the counter 82. This write signal WR is output in synchronization with the data transfer of the DMA controller 70 one byte at a time. Counter 82 becomes active upon receipt of DMA acknowledgment signal DMAC and performs a predetermined binary counting operation.

DMA acknowledgment signal DMAC is a signal output when the DMA controller 70 acknowledges a DMA request from the control units M and 10, and is at an active level during DMA operation. The multi-bit output of counter 82 is input to encoder 83. The encoder 83 has a predetermined combinational logic, and by encoding the output of the counter 82 in a predetermined manner, the encoder 83 generates a Norse signal in which high level and low level are repeated at a predetermined period. EC (see FIG. 4(c)) is output.

The internal logic within the encoder 83 has a configuration that allows arbitrary settings. This /fP pulse signal EC is input to the NAND dart 84, and the horizontal broken line designation signal SL is input from the control device IO at the NAND f-to 84 (see FIG. 4(b)).
After the AND is performed, the result is inputted to the AND gate 81. (When printing a yellow broken line, the horizontal broken line designation signal SL is at a high level, and the I?lus signal EC output from the encoder 83 is logically inverted and becomes an andgo 1-81.
However, when printing a horizontal solid line, the broken line designation signal SL is at a low level, so the output of the NAND gate 84 is at a high level, and the AND gate 81 (write)'? The route is output as is. Because of this configuration, the weekly enable signal WE1 outputted from the AND gate 81 becomes as shown in FIG.
), the high level and low level are repeated at a predetermined period. Therefore, the DMA controller 70 transfers data from the I10 boat 60 to the horizontal ruled line image buffer 41.
The black data transferred to is intermittently in a state where it cannot be written, and as a result, the image data stored in the horizontal ruled line image buffer 41 becomes horizontal broken line image data of a predetermined period.

Next, in FIG. 2, the address decoder 80 decodes the address signal on the address bus AB under the control of the control device 10, and transfers the decoded signal to the buffer selector 5.
Output to 0. The three image buffers 40 mentioned above,
The addresses assigned to 41 and 42 are different from each other, and by decoding the address signal on the address bus AB, it is possible to determine which image buffer is designated by the control device 10. When writing data to the image buffers 40, 41 and 42, the buffer selector 50 refers to the f:7-code result to determine which image buffer is to be made active for writing or reading. Further, when reading out the r-night image, which image buffer is to be selected is completely determined based on the selection signal Is inputted from the print control section 1 (see FIG. 1). The bus selector 30 controls each image buffer 40, 41 under the control of the control device 10.
The write address AB and the read address RA are used when storing data in ゜42 and when reading data.

The data buses DB and DB' are switched and connected as appropriate.

Next, three image buffers 40, 41, and 4 are transferred in 1-byte units when the PS converter 55 pieces of data are continuously output.
2 is serially converted into a memory booter/graler and outputted to the OR circuit 56 one pit at a time. The OR circuit 56 calculates the logical sum of these three outputs, thereby combining the characters and turns temporarily stored in the character image buffer 40 with the ruled line image output from the horizontal ruled line image buffer 41 or the vertical ruled line image buffer 42. The logical sum output is outputted as the final output of the raster image creation section 2 to the line buffers L1+L2 in FIG.

In this configuration, the operation when printing horizontal broken ruled lines will be described.

Upon receiving the ruled line command, the control device 10 sets white data in the I10 port 60 and issues a DMA request to the DMA controller 70.

After holding the control device 10 and disconnecting it from the bus, the DMA controller 70 sequentially transfers the 1-byte white data to the image buffer 41 for horizontal ruled lines and clears the image buffer 41 for horizontal ruled lines.

After that, the control device 10 sets black data in the Ekaport 60, and transmits the data transfer start address and the number of transfer bytes corresponding to the print position specified by the ruled line command signal using DMA.
Set it on the controller 70. In this case, since the horizontal broken line is designated in the ruled line command signal, the control unit M10 outputs the horizontal broken line designation signal SL.

is set to be high level at the logical level. Next, the DMA controller 70 holds the control device IO again, disconnects it from the path, and then starts transferring black data from I10 Potro 0 to the image buffer 41 for horizontal ruled lines. On this occasion,
It goes without saying that the address bus on the address bus AB is decoded by the address decoder 8o, and as a result, the horizontal ruled line image buffer 41 is selected by the buffer selector 50. During this data transfer, the DMA controller 70 attempts to transfer the required number of transfer bytes of black data one byte at a time to the storage area corresponding to the print position of the line image buffer 41.

On the other hand, the write signal control unit 80 intermittently extracts the write signal WR of the DMA controller 70 using the aforementioned νV, and also selects the write signal WR that is intermittently extracted. Image buffer for ruled lines 41-11
It is output as the 'include enable signal WR. As a result, I10 cod? -Black data is transferred from Toro 0 to the image buffer 41 for horizontal ruled line 1, but when the v1 inclusion enable signal WR is at a low level, black data is not written. It is possible to create a 4/4 broken image in which black data and white data are repeated at a predetermined period.

Next, the horizontal image stored in the image buffer 41 for several lines?
The reading of the 11ν-ray image data is performed by the print control section 1 (g', see Figure 1).

A buffer) 111 selection signal IS for M output and an address signal RA for start-up are input from the print control unit 1 to the raster image creation unit 2. Switch the address bus and data bus to the RA and DB' sides. A ruled line command is input to the print control unit 1, and the print control unit 1 decodes the information indicating the line thickness in the ruled line command to determine the required number of times to read the stored contents of the horizontal ruled line image buffer 41. Recognize. In the print control unit 1, there is a raster counter (either software or hardware) that indicates which line in one line (consisting of rask lines) is currently being printed. The print control unit l controls the image buffer 4 based on the count value of the raster counter.
0.41.42 The timing for sending the selection signal is for selection is determined. For example, when printing horizontal broken lines for 10 raster lines, when the raster current value reaches a value indicating the desired print start position, the image buffer 41 is selected and the read address is set so that the image buffer 41 is selected and a predetermined read operation is performed. The signal RA is sent to the hind limb image buffer 41.
By reading the same horizontal broken line image data stored in 10 times, a thin thick horizontal broken line is printed. The image data read out from the image buffer 41 for horizontal ruled lines at appropriate times is inputted to the ORDART 56'' via the ll''tp-sf conversion unit 55, and the ORDART 56 compares it bit by bit with other character pattern data or image data for vertical ruled lines. After the logical sum is taken, the printing section 3 (see Figure 1)
The final rask image data RD is input to the line buffer L1 or tjLt.

By the way, after the printing of one horizontal broken line is completed, the counter 82 in the push-in signal control section 80 retains the previous count value, and even if another horizontal broken line is printed again in this state, the horizontal The printing start position 16 of the broken line is the 51st g.
As shown in 1(a), they do not necessarily match. Therefore, in this embodiment, each time a horizontal broken line ruled line image is generated, an appropriate initial value is set in the counter 82, as shown in FIG.
), the horizontal broken lines with the same phase are printed.

When printing a horizontal solid line, the control device 10 sets the horizontal broken line designation signal SL to a low logic level, and then performs the same operations as described above to print any horizontal solid line.

In other words, when printing horizontal ruled lines, image buffer 4
The print position, print length, line pattern, etc. in the main scanning direction of the horizontal ruled line to be printed are changed depending on the difference in the memory contents of 1, and the thickness of the bond is changed depending on the number of times the same image data stored in the image buffer 41 is read. I'm trying to change the intensity.

Next, the case of printing vertical ruled lines will be briefly explained.

The case of vertical ruled lines is similar to the case of horizontal ruled lines, and the DMA controller 70 transfers the I/O data according to the data transfer start address and transfer byte length set by the control device 10.
By sequentially transferring the black data of the 10 ports 60 to the image buffer 42 for vertical ruled lines, basic image data for one rask line is stored in the image buffer 42. However, from X10 port 60 to vertical ruled line image buffer 4
The data transfer control to 2 may be performed by the DMA controller 70, or may be performed by the control device 10 itself. This is done by the control device 10 itself because image data for vertical ruled lines usually has less black data in one raster line than for horizontal ruled lines (often a few pytol, 10-odd bytes). This is because high speed performance is not hindered even when In this way, if the print control unit 1 reads out the vertical ruled line image data for one raster stored in the vertical ruled line image buffer 42 at the required time and the required number of times according to the ruled line command information, any vertical ruled line can be printed. will now be printed.

That is, when printing vertical ruled lines, the printing position f7'/ of the vertical ruled line to be printed in the main scanning direction, the thickness of the line, etc. are changed depending on the storage contents of the image buffer 42.
The line types, line lengths, etc. of the vertical ruled lines are changed depending on the manner in which the same stored content is extracted from the image buffer 42.

In the above embodiment, the write signal control unit 80 consisting of a counter 82, an encoder 83, etc. is used as a configuration for creating a horizontal broken line image, but the write signal control unit 80 is not limited to this, and may be implemented by other circuits. It may be configured as follows. In short, any circuit may be used as long as it can intermittently extract and output the write pulse signal input in synchronization with data transfer by the DMA controller at a predetermined cycle.

〔Effect of the invention〕

As explained above, according to the present invention, since it is possible to print arbitrary ruled lines without having a font for ruled lines, it is possible to print ruled lines with a high degree of freedom without increasing the number of fonts for ruled lines, that is, the memory capacity. Printing can be realized. In addition, a DMA system is adopted for transferring the ruled line image data, and since the ruled line image data generated only for the rask lines on which ruled lines are to be printed is read out, high-speed printing processing is possible. In particular, since the horizontal broken line can be printed only by the intermittent control of the write enable signal, it becomes possible to print the horizontal broken line with any printing cycle by simply setting the intermittent control mode appropriately.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the overall configuration of a Zolinta device to which the ruled line image generating device of the present invention is applied, FIG. 2 is a block diagram showing one embodiment of the ruled line image generating device according to the present invention, and FIG. 4 is a circuit block diagram showing an example of the internal configuration of the write signal control section, FIG. 4 is a time chart for explaining an example of the operation of the device of this embodiment, and FIG. 5 is a time chart for explaining an example of the operation of the device of this embodiment. It is an explanatory diagram. 1...Print control section, 2...Rask image printing section,
3...Printing section, lO...control device, 20...7 ont memory, 30...bus selector, 40...image buffer for characters, 41...image buffer for horizontal ruled lines, 42... Image buffer for vertical lines, 50...
・Buffer selector, 55...PS converter, 56...
・Ordart, 60...Ilo y15-), 70
DMA controller, 80 Write signal control unit, 82 Counter, 83 Encoder, 90 Address decoder. Figure 1 Figure 4 (0) WR. (b) SL: (C) ECL (d) WE L Figure 5 (G) (b)

Claims (1)

[Claims] A ruled line image generation device that sequentially generates predetermined ruled line image data for each lifetime scanning line in response to ruled line command information specifying ruled lines to be printed, which has a storage capacity corresponding to at least the number of dots for the lifetime scanning line. , an image buffer into which the horizontal ruled line image data generated when the write enable signal is input, and a predetermined number of input/output pits into which black data of a predetermined number of pits is set when the ruled line image data is generated/-) a DMA controller that sequentially transfers the black data from the input/output boat to the image buffer in units of the predetermined number of bits using a DMA method; and when a horizontal broken line is specified, the DMA controller transfers data in units of the predetermined number of bits. write control means that intermittently selects and extracts a write noise signal generated in synchronization with the DMA controller according to a set selection content and inputs the extracted signal to a write enable signal terminal of the image buffer; control means for setting a data transfer start address and a data transfer length corresponding to the ruled line command information, and reading out horizontal ruled line image data temporarily stored in the image buffer a required number of times in accordance with the ruled line command information. A ruled line image generator.