JPS60167395A - Printed circuit board - Google Patents

Printed circuit board

Info

Publication number
JPS60167395A
JPS60167395A JP60010856A JP1085685A JPS60167395A JP S60167395 A JPS60167395 A JP S60167395A JP 60010856 A JP60010856 A JP 60010856A JP 1085685 A JP1085685 A JP 1085685A JP S60167395 A JPS60167395 A JP S60167395A
Authority
JP
Japan
Prior art keywords
resistor
layer
printed circuit
circuit board
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60010856A
Other languages
Japanese (ja)
Other versions
JPS6346596B2 (en
Inventor
稔 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60010856A priority Critical patent/JPS60167395A/en
Publication of JPS60167395A publication Critical patent/JPS60167395A/en
Publication of JPS6346596B2 publication Critical patent/JPS6346596B2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は抵抗層付印刷回路基板に関し、特にその抵抗の
配線の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a printed circuit board with a resistive layer, and particularly to an improvement in the wiring of the resistor.

〔発明の背景〕[Background of the invention]

従来の抵抗層付印刷回路基板においては、基板上に搭載
された半導体集積回路(IC)等の部品と、基板の抵抗
層を用いてあらかじめ形成しておいた抵抗とを、基板の
信号層に設けた配線パターンによって配線接続し、所望
の論理回路を構成していた。
In a conventional printed circuit board with a resistive layer, components such as a semiconductor integrated circuit (IC) mounted on the board and a resistor formed in advance using the resistive layer of the board are connected to the signal layer of the board. Wiring connections were made using the provided wiring patterns to construct a desired logic circuit.

このように、抵抗との配線も信号層の配線パターンを用
いているため、搭載部品数が多くなると配線パターンが
混雑し、信号層を多くしなければならない等の問題が生
じた。
In this way, since the wiring pattern of the signal layer is also used for wiring with the resistor, problems such as the wiring pattern becoming crowded as the number of mounted components increases and the number of signal layers having to be increased arise.

この問題を解決するために、抵抗との配線は信号層の配
線パターンを用いず、例えば、通常、部品搭載用ランド
・パターン等を設けてそれを利用することが考えられる
。しかし、抵抗を配線接続すべき部品の端子は基板の品
種毎に異なるので、通常1種で良い、最上層用のマスク
を品種毎に用意しなければならない。このため、各品種
で抵抗と接続する可能性のある部品の端子は全て抵抗と
配線接続するような配線パターンを最上層に用意してお
くことが考えられるが、各品種毎に不要な配線パターン
を切断しなければならず、信頼性の低下や工数の増大を
招く。
In order to solve this problem, it is conceivable to use a land pattern for mounting components, etc., instead of using the wiring pattern of the signal layer for wiring with the resistor. However, since the terminals of the components to which the resistors are wired differ depending on the type of board, a mask for the top layer, which usually only requires one type, must be prepared for each type of board. For this reason, it is conceivable to prepare a wiring pattern on the top layer that connects all the terminals of components that may be connected to the resistor for each product type, but unnecessary wiring patterns for each product type may be prepared. must be cut, resulting in decreased reliability and increased man-hours.

〔発明の目的〕[Purpose of the invention]

かかる点に鑑み本発明の目的とするところは、上記の如
き従来技術およびその改良技術の問題点を除去すること
であり、マスクの種類数の増加や信頼性の低下や工数の
増大を招くことなしに、抵抗との配線パターンを実質的
になくせる抵抗層付印刷回路基板を提供することである
In view of the above, an object of the present invention is to eliminate the problems of the conventional technology and its improved technology as described above, and to eliminate the problem of increasing the number of types of masks, decreasing reliability, and increasing man-hours. It is an object of the present invention to provide a printed circuit board with a resistive layer that can substantially eliminate a wiring pattern with a resistor.

〔−発明の概要〕[-Summary of the invention]

かかる目的を達成するために、本発明は181戎部品の
端子で抵抗と接続する可能性のある全ての端子位置に抵
抗層を用いてあらかじめ抵抗を形成しておき、抵抗と接
続する必要のある端子位置にのみ、選択穴明して実際に
接続することを特徴とする。
In order to achieve such an object, the present invention uses a resistive layer to form resistors in advance at all terminal positions where there is a possibility of connecting to a resistor at the terminals of the 181-type component, and the resistors are formed in advance at all terminal positions that may be connected to a resistor. It is characterized in that selective holes are drilled only at the terminal positions for actual connection.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例につき図面を用いて詳細に説明す
る。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図(a)及び(b)は本発明の一実施例である抵抗
層付印刷回路基板の上面図及び断面図である。
FIGS. 1(a) and 1(b) are a top view and a sectional view of a printed circuit board with a resistive layer, which is an embodiment of the present invention.

基板】の表面に部品、例えはIC2が搭載さ九る。Components, for example IC2, are mounted on the surface of the board.

基板は絶縁基材20、導体層13〜J8、抵抗層19に
よって構成される。導体層にはエツチング技術等によっ
て必要なパターンが形成さ汎ており、その用途によって
信号配線層15.16、電源層14.1.7、キャップ
層13.18に分かJしる。
The substrate includes an insulating base material 20, conductor layers 13 to J8, and a resistance layer 19. A necessary pattern is formed on the conductor layer by etching technology or the like, and it is divided into a signal wiring layer 15.16, a power supply layer 14.1.7, and a cap layer 13.18 depending on its purpose.

抵抗層にはエツチング技術等によって必要な抵抗パター
ンか形成されている。抵抗パターンの詳細図を第2図(
a)及び(b)に示す。本図は第1図の11へ抗10を
拡大したものであり、第2図(ε」)はその平面図、第
2図(b)は、第2図(、)のX、 −X ’における
断面図である。導体17の所望の場所に所定の抵抗値の
抵抗10が形成される。キャップ層13にはICの端子
3を固着するためのランドパターン4と抵抗接続用パッ
ド5と信号配線接続用パッド6が設けられている。なお
、抵抗と接続する可能性のない端子に関しては抵抗接続
用パラ1へは当然不要である。抵抗接続用パッドの直下
には抵抗10,11が設けられている。配線接続用バッ
ト6はスルーホール(貫通孔)8を介し信号層の信号配
線パターン12と接続さ扛、必要な配線接続が行なわれ
る。抵抗と接続する必要のある端子に関しては抵抗接続
用パッドにスルーホール7を形成することによって抵抗
10と接続する。同じく、抵抗と接続してはいけない端
子に関してはスルーホールを形成せず、パッド9と抵抗
J]は接続されない。
A necessary resistance pattern is formed on the resistance layer by etching technology or the like. A detailed diagram of the resistance pattern is shown in Figure 2 (
Shown in a) and (b). This figure shows the resistor 10 enlarged to 11 in Figure 1, Figure 2 (ε'') is its plan view, and Figure 2 (b) is X, -X' in Figure 2 (,). FIG. A resistor 10 having a predetermined resistance value is formed at a desired location on the conductor 17. The cap layer 13 is provided with a land pattern 4 for fixing the IC terminal 3, a resistance connection pad 5, and a signal wiring connection pad 6. Note that terminals that have no possibility of being connected to a resistor are of course not required to be connected to the resistor connection terminal 1. Resistors 10 and 11 are provided directly below the resistance connection pad. The wiring connection bat 6 is connected to the signal wiring pattern 12 of the signal layer through a through hole 8, and necessary wiring connections are made. Terminals that need to be connected to the resistor are connected to the resistor 10 by forming through holes 7 in the resistor connection pads. Similarly, through holes are not formed for terminals that should not be connected to resistors, and pad 9 and resistor J] are not connected.

第3図(a)及び(b)は本発明の他の実施例を示す上
面図及び1祈面図であり、同一符号のものは前記実施例
と同一のものを示す。前記実施例との構成」二の相迫ば
、抵抗接続用パッドと配線接続用パッドを共通にして1
つのパッド30にもとめたこと、抵抗層を複数(36,
37)設けて、各バラ1〜の真下に複数の抵抗(38,
39)を設けたことである。パッド32はスルーホール
35を介して信号層とのみ接続され、パッド34はスル
ーホール34を介して信号層と1つの抵抗と接続され、
パッド33は信号層と2つの抵抗と接続される。このよ
うにして、必要な端子にのみ抵抗を接続し、かつその抵
抗値を変えることかできる。
FIGS. 3(a) and 3(b) are a top view and a front view showing another embodiment of the present invention, and the same reference numerals indicate the same parts as in the previous embodiment. If the second problem arises in the configuration of the above embodiment, the resistor connection pad and the wiring connection pad can be used in common.
One pad 30 is used, and a plurality of resistive layers (36, 36,
37), and a plurality of resistors (38,
39). The pad 32 is connected only to the signal layer through the through hole 35, and the pad 34 is connected to the signal layer and one resistor through the through hole 34.
Pad 33 is connected to a signal layer and two resistors. In this way, it is possible to connect a resistor only to the necessary terminals and change the resistance value.

〔発明の効果〕〔Effect of the invention〕

以上述べた如き構成であるから本発明にあっては、次の
如き効果を得ることができる。即ち■ 抵抗との配線パ
ターンを実質的になくせるので、部品の実装密度を上げ
ることができる。
With the configuration as described above, the present invention can obtain the following effects. That is, (1) Since the wiring pattern with the resistor can be substantially eliminated, the mounting density of components can be increased.

■ 基板の最上層の導体パターンを標準化できるので、
そのためのマスクを大巾に;威らせる。
■ The conductor pattern on the top layer of the board can be standardized.
The mask for that purpose is a big hood; it is intimidating.

■ 抵抗の接続の選択に当って、抵抗どの配線パターン
の切断を要しないので、悟顔性を向上させ工数を低減で
きる。
■ When selecting the resistor connection, it is not necessary to cut any wiring pattern of the resistor, so it is possible to improve the simplicity and reduce the number of man-hours.

■ 論理変更等により、部品の端子と信号配線パターン
との接続を切断し、がっ、端子と抵抗との接続はそのま
まにしておく必要が生じる例が多いが、特に第1図の実
施例ではパッド5,6の間の導体パターンを切断するこ
とにより容易に実現できる。
■ There are many cases where it is necessary to disconnect the terminals of a component and the signal wiring pattern due to changes in logic, etc., but leave the connections between the terminals and the resistor as they are, especially in the example shown in Figure 1. This can be easily realized by cutting the conductor pattern between the pads 5 and 6.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(5])及び(b)は本発明の一実施例の構成を
示喝用ヤ1.第2図(、)及び(b)はその一部拡犬図
、第3図(a)及び(b)は本発明の他の実施例のイ、
η成を示す図である。 Vil 図 (α) 第 2 図 (α) 聞 3I21 (α)
FIGS. 1(5) and 1(b) illustrate the configuration of an embodiment of the present invention. FIGS. 2(,) and (b) are partially enlarged views, and FIGS. 3(a) and (b) are views of other embodiments of the present invention.
FIG. Vil Figure (α) Figure 2 (α) 3I21 (α)

Claims (1)

【特許請求の範囲】[Claims] 複数層から成る印刷回路基板であって、該基板上に搭載
される部品の端子下の所定層には抵抗があらかじめ形成
され、該抵抗と所定の端子とが穴明により接続されてい
ることを特徴とする印刷回路基板。
A printed circuit board consisting of multiple layers, in which a resistor is formed in advance in a predetermined layer below a terminal of a component mounted on the board, and the resistor and a predetermined terminal are connected by a hole. Features printed circuit board.
JP60010856A 1985-01-25 1985-01-25 Printed circuit board Granted JPS60167395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60010856A JPS60167395A (en) 1985-01-25 1985-01-25 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60010856A JPS60167395A (en) 1985-01-25 1985-01-25 Printed circuit board

Publications (2)

Publication Number Publication Date
JPS60167395A true JPS60167395A (en) 1985-08-30
JPS6346596B2 JPS6346596B2 (en) 1988-09-16

Family

ID=11761994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60010856A Granted JPS60167395A (en) 1985-01-25 1985-01-25 Printed circuit board

Country Status (1)

Country Link
JP (1) JPS60167395A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519142A (en) * 1974-07-15 1976-01-24 Matsushita Electric Works Ltd Ototsumoyono renzokukeiseihoho

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519142A (en) * 1974-07-15 1976-01-24 Matsushita Electric Works Ltd Ototsumoyono renzokukeiseihoho

Also Published As

Publication number Publication date
JPS6346596B2 (en) 1988-09-16

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