JPS6016659B2 - Interrupt priority control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control system for interrupt priority in a digital processing device comprising one main control device and a plurality of sub-control devices.

Generally, when one main controller controls many sub-control devices, the main controller can only accept one interrupt at a time, so each sub-control device must be It is necessary to prioritize.

Conventionally, this type of priority order has often been fixedly determined in advance, and in most cases it has been determined by using a priority encoder or by wiring between control devices that have an interrupt generation mechanism. Ta.

FIG. 1 shows an example of the latter in a conventional embodiment, in which 1 is a main controller that performs interrupt processing, 2, 2a, 2b, 2i, 2
n is a priority control line, 3 is an interrupt signal line, 4a, 4b,
4i and 4n are sub-control devices, and in particular 4i' indicates that a plurality of similar sub-control devices are connected.

Reference numerals 5a, 5b, and 5n indicate interrupt request flip-flops, but their input conditions are omitted.

6a, 6b, 6n are interrupt request signal lines, 7a, 7b, 7
n is an AND gate whose output becomes logic "1" only when both of its inputs are logic "1"; 8a, 8b, and 8n are inverters having outputs that invert the logic of the inputs; 9a, 9b
, 9n is a logic register inversion gate having an output that is an inversion of the logic thin gate output, and since the output is an open collector, the wire-coupled output signal line 3 receives interrupt requests 6a, 6b, 6b, It becomes a logical value obtained by calculating the logical sum of 6n.

Here, priority control is performed by signal lines 2, 2a, 2b, 2i,
2n and gates 7a, 7b, 7n, 8a, 8b, 8n
It is carried out by

The sub-control unit to which you want to give the highest priority is main control unit 1.
Since this signal line 2 is always kept at logic "1" in the main controller 1, the priority control gate 7a in the sub controller 4a is always open. is maintained, and the interrupt request 6a in the sub-control device 4a is
When the logic is "1" (that is, when there is an interrupt request), the interrupt signal line 3 is driven through the gate 9a, the interrupt request is transmitted to the main controller 1, and the control gate 7a
is closed by the output of the inverter 8a, and the priority control line 2a is kept at logic "0".

When the logic is “0” (that is, when there is no interrupt request), the interrupt signal line 3 is not driven, and at the same time the inverter 8a
Since the output becomes "1", the priority control line 2a becomes logic "1".

Next, considering the priority of the sub-control device 4b to which the priority control line 2a is connected, when the priority control line 2a is logic "1", it can perform the same operation as the sub-control device 4a, but when the priority control line 2a is logic "0" At this time, even if the interrupt request signal line 6b is at logic "1", the interrupt signal line 3 cannot be driven and at the same time, the control gate 7b is closed, so its output 2b is kept at logic "0".

That is, the sub-control device 4b is the sub-control device counterfeit 4b, and the sub-control device counterfeit 4a is the sub-control device counterfeit 4a.
An interrupt request can be issued only when the sub-control device 4a is not generating an interrupt request, and therefore the priority order between the two devices is sub-control device 4a>sub-control device 4b.

Since the sub-control devices 4i and 4n also operate in the same way, the order of priority after the sub-control devices is ultimately sub-control device 4a>sub-control device 4b.
>Sub-control device 4i>Sub-control device 4n.

This indicates that the interrupt priority is uniquely determined by the wiring of the priority control line.

The characteristics of this control method are that it can be handled with a relatively simple circuit when the probability of simultaneous occurrence of interrupt requests from the sub-control device is low, and that there is no limit to the waiting time from when an interrupt request is generated until it is accepted. This is effective when there is no such system, or when it is okay to assign a priority order to all control devices.

However, if this type of priority control is performed, for example, when interrupt requests occur simultaneously in the sub-control devices 4a and 4n, and the main control device 1 is accepting and processing the interrupt from the sub-control device 4a, When an interrupt request is generated in the sub-control device 4b, the main control device 1 processes the interrupt request of the sub-control device 4b, which has a higher priority than the Liu control device 4n, after the interrupt processing of the sub-control device 4a. become.

Furthermore, if an interrupt from the sub-control device 4a occurs again while the interrupt processing by the sub-control device 4b is being performed, the main control device 1 will terminate the sub-control device 4a at the same time that the interrupt processing by the sub-control device 4b is completed. Enter interrupt processing. After all, sub-control device 4
The interrupt request of n is processed after all the interrupt requests of the sub-control devices 4a, 4b, 4i which have a higher priority are processed. When the probability of simultaneous occurrence of interrupt requests from 4n is high, the average waiting time from when an interrupt request is generated until it is processed is equal to This will be longer than the average waiting time until processing. In cases where each sub-control device requires equal interrupt processing services to perform the same type of processing, it is important to note that if the probability of duplicate interrupt requests (simultaneous occurrence probability) is high, priority This is undesirable because a difference occurs in the waiting time from when an interrupt request is generated until it is processed, making it impossible to achieve uniform interrupt processing services. The main controller recognizes the sub-control device number where an interrupt is occurring by driving the interrupt signal line 3 when the main controller executes an input command to each Hatake 8 control device. It is generally known that this can be easily done by waiting for a mechanism in which the sub-control device in question transmits its own device number to the main control device through the bus line, and therefore the explanation and drawings will be omitted here.

This invention enables the main controller to provide uniform interrupt processing services to each Hatamasa control device on average by sequentially changing the priority order of each sub-control device. This will be explained in detail.

FIG. 2 shows an embodiment of the present invention, in which 11 is a main controller that performs interrupt processing, 12a, 12b, 12i, and 12n are sub controllers, 13a, 13b, and 13n are interrupt request flip-flops, and 14a, 14b, and 13n are interrupt request flip-flops. 14n is a priority control device flip-flop; 15a, 15b, 15n are inverters with open collector outputs; 16 is a control data line in which the outputs of the inverters 15a, 15b, 15n are wire-coupled and logically summed; 17a; , 17b, 17n are OR gates, 18a, 18b, 18n are priority control lines, 19a, 19b, 19i, 19n are priority control data lines, and normally the next priority control flip-flops 14a, 14b, 14n data input.

20a, 20b, 20n are the outputs of the interrupt request flip-flops 13a, 13b, 13n, and 21 is a clock signal commonly connected to the clock input of each priority control flip-flop 14a, 14b, 14n. First, priority control flip-flops 14a, 14b
, 14n will be explained.

FIG. 3 shows priority control flip-flops 14a, 1.
FIG. 4, which is a diagram showing the portions 4b and 14n, is an example of the operating waveform of FIG. 3.

In FIG. 3, flip-flops 14a, 14b, and 14n are D-type flip-flops that latch the contents of the D input at the rising edge of the T input and output it to the Q output. The output 19n of the flip-flop located at the right end is not connected to the control data line 16.

In the logic circuit having such a configuration, only one of the D-type flip-flops 14a, 14b, and 14n has logic "1".
As shown in FIG. 4, a logic "1" signal appears at the output of only one flip-flop and is shifted synchronously with the clock.
This logic "1" signal is used in FIG. 2 as a signal indicating the highest priority.

For example, when the priority control data line 19a is logic "1", the OR gate 17a in the sub-control device 12a
The output becomes logic "1" regardless of the presence or absence of an interrupt request from another sub-control device, and the priority control AND gate 7a becomes open. In this state, the sub-control device 12
a means that the interrupt request will be transmitted to the main controller 11 with priority over the other sub-control devices 12b, 12i, and 12n, that is, the sub-control device 12a has the highest interrupt priority. It represents. At this time, each sub-control device 1
The priority order of 2a, 12b, 12i, and 12n is determined by the wiring as in the example of FIG.
becomes.

Next, when one clock pulse is output from the main controller 11 onto the clock line 21, the priority control data line 21
The logic "1" signal on 9a is read into the flip-flop 14b and output on the priority control data line 19b, so the sub-control unit 12b now has the highest interrupt priority. Become.

At this time, each sub-control device 12a, 12b, 12i, 12n
The priority of the rightmost sub-control device 12n is determined from the point where the priority control data line 18n of the right-most sub-control device 12n is connected to the sub-control device 12a through the main control device 11 to the sub-control device 12b.
>Sub-control device 12i>Sub-control device 12n>Sub-control device 1
It becomes 2a.

That is, the priority of the sub-control devices 12b, 12i, and 12n increases one by one, and the priority of the sub-control device 12a, which had the highest priority, becomes the lowest.

Here, if the clock pulse is applied each time one interrupt is processed or continuously at appropriate intervals, the above process will be repeated, and this can be explained by focusing on one sub-control device. FIG. 5 shows changes in the priority order of the device.

In FIG. 5, the numbers in circles represent priorities, with 1 being the highest and n being the lowest. n is equal to the number of connected subcontrollers. By the way, each Liu control device 12a, 12b, 1
If 2i and 12n each have a change in priority order as shown in FIG.

Considering a certain period of time during which a clock pulse exists, the priority given to each Liu controller is, on average,
be equal. This invention takes advantage of the above-mentioned effects,
This provides a priority control method in which the priorities are apparently equal.

As described above, in the priority control system according to the present invention, by equally changing the interrupt priority of each Hatakeyama control device from the highest priority to the lowest priority, it is possible to give equal interrupt priority to each Liu control device. Therefore, each field generated by the traditional method. It is possible to eliminate the situation in which the average time from the generation of an interrupt request of the control device until the interrupt processing is performed varies greatly depending on each sub-control device, and uniform interrupt processing can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional priority control system, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram of a priority control flip-flop and an open collector output inverter shown in FIG. FIG. 4 is a diagram showing an example of the operation waveform of the circuit in FIG. 3, and FIG. 5 is a diagram showing an example of the operation waveform of the circuit in FIG. 3, and FIG. FIG. In the figure, 1 is the main control device that performs interrupt processing, 2, 2a, 2b
, 2i, 2n are priority control lines, 3 is an interrupt signal line, 4
a, 4b. 4i and 4n are sub-controllers; in particular, 4i indicates that a plurality of similar sub-controllers are connected. 5a, 5b, 5n are interrupt request flip-flops, 6
a, 6b, 6n are interrupt request signal lines 7a, 7b, 7n are AND gates, 8a, 8b, 8n are inverters, 9a,
9b, gn are logic inverting gates with open collector output, 11 is a main control gate, 12a, 12b, 1
2i, 12n are sub-control units; 13a, 13b, 13n are interrupt request flip-flops; 14a. 14b, 14
n is a flip-flop for priority control, 15a, 15
b, 15n are inverters with open collector outputs, 16 is control data lines, 17a, 17b, 17n are OR gates 18a, 18b, 18n are priority control lines 19a, 19b, 19i, 19n are for priority control Data lines 20a, 20b, 20n are interrupt request fritubs.
Flop 13a. The outputs 13b and 13n, 21, are clock signals commonly connected to the clock inputs of each priority control flip-flop. In the drawings, the same or corresponding parts are denoted by the same reference numerals. Multiple diagrams, multiple Z diagrams, multiple diagrams, multiple 4 diagrams, multiple 5 diagrams

Claims (1)

[Claims] 1. In a device in which a main control device with an interrupt reception mechanism receives and processes multiple interrupts generated from a plurality of sub-control devices with an interrupt generation mechanism, each of the above-mentioned sub-control devices is assigned priority control one by one. A ring counter is constructed by connecting the flip-flops in series and setting only one of the flip-flops to logic "1" (or "0"). , the sub-control device having the logic "1" (or "0") flip-flop is given the highest priority, and each flip-flop constituting the ring counter is given the highest priority.
The logic held in the flip-flop is controlled by a pulse commonly applied to the flip-flop from the main controller.
1"4 (or "0"), and the sub-control device has an input, and an OR gate that logically ORs this input with the output of the flip-flop, and negates the interrupt request. It has a NOT gate, an AND gate that takes the logical product of the output of this NOT gate and the output of the above OR gate, and an output that sends the output of this AND gate from the above-mentioned sub-control device, and the above-mentioned output of each of the above-mentioned sub-control devices. The sub-control units are connected in a ring by connecting the sub-control unit to the input of the next sub-control unit, and the sub-control unit whose flip-flop is set to logic “1” has the highest priority. , the sub-control devices in the next stage have sequentially lower priorities, and the sub-control device whose output is connected to the input of the sub-control device with the highest priority has the lowest priority; The logic "1" held in each of the flip-flops is shifted by a pulse, so that the priority of each of the sub-control devices is sequentially changed cyclically from the lowest to the highest. Interrupt priority control method.