JPS59229643A - Sorting operation circuit - Google Patents

Abstract

PURPOSE:To sort data while inputting the data and to speed up the sorting operation by connecting uniform modules each of which has a single function like an array. CONSTITUTION:A sorting operation circuit 1 is constituted by connecting the necessary number of modules 11-1n each of which has a single function like an array, processes a sorting input IN by control signals T, C0, C1 through the adjacently connected module and generates a sorting output OUT. All the modules 11-1n constituting the sorting operation circuit 1 are the same and the circuit 1 compares the data stored in itself with the input data to decide the data to be processed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a sort calculation circuit that enables high-speed processing.

(2) Prior art and problems In general, logic circuits employ a sorting circuit that processes data in a predetermined order, but as the amount of data increases, the speed of data processing in this sorting circuit increases. is desired.

Conventional sort calculation methods include a method in which data is input to a buffer all at once and processed, and a method in which data is input individually one by one and processed.

However, in the former batch processing method, the input time and processing time are separate, that is, the sorting time is slow, so in order to speed up the processing, the basic calculation speed must be increased, whereas in the latter individual processing method, the processing speed is slow. Since processing cannot be performed unless the input speed falls within the input speed, there is a problem that the input speed is suppressed by the processing speed.

(3) Purpose of the Invention The purpose of the present invention is to speed up the sorting operation by connecting standardized modules having only a single function in an array so that data can be sorted while being input. There is a particular thing.

(4) Structure of the Invention According to the present invention, a comparator, a multiplexer, and logic modules necessary for the multiplexer are configured, and input data and data stored in the immediately preceding module and the immediately succeeding module are provided. Furthermore, there is provided a sort operation circuit characterized in that a plurality of modules having a single function of determining data to be processed by comparing their own data are connected in an array.

(5) Embodiments of the Invention The present invention will now be described by way of embodiments with reference to the accompanying drawings.

FIG. 1 is a circuit configuration diagram of a sort calculation method according to the present invention. The sort calculation circuit 1 shown in FIG. 1 is made up of a necessary number of modules 11...1rX having a single function connected in an array, and sort input crabs N are connected adjacently to each other by control signals T, OQ, and 01. The sort operation is processed through a module to generate a sort output 0υT.

Each module 11 constituting the sort calculation circuit 1...
・1rL are all the same, and module 1 is shown in Figure 2.
The configuration diagram is shown below. Go to module 1.

3 on chip 1, 4 on comparator 1, multiplexer 1kl
and logical modules 1 and 2 necessary for this.

The module 1 configured in this manner compares the data R it stores with the input data E, as will be described in detail below, and if the data R is correct, then it takes in R.

If work≧R and work R at 1(k-1), input data is taken in by itself, and work≧R and work R at 1(k-1).
If R is constructed in , the immediately preceding module 1 (k-1)
Get data from. Also, module 1 in this case
(k+1) is such a function that all modules 11...
- Same for 1n.

FIG. 3 is a detailed connection diagram of each module shown in FIG. 1. FIG. 4 is a diagram showing the configuration of logical modules necessary for the multiplexer forming each module.

The sort calculation circuit 1 according to the present invention having the above configuration will be explained with reference to FIG. 5 as follows. First, the beam set signal 001'-IJ (FIGS. 2 and 4) is input to initialize each module, and then data is input and calculations are performed.

In FIG. 5, each module 11.12 at time n-1.
...16 has numbers 6, 5, respectively, as shown in the diagram.
・1 is stored. Sort) The JIIT order is to arrange the sort inputs in descending order.

Assume that 3 is newly input as input data in this state (FIG. 5). This input data 3 is compared with the data currently stored in each module by a comparator 1 4 (FIG. 2).

6 is stored in the leftmost module 11' in FIG. Therefore, since there is a relationship (input data I) < (stored data R), comparator 1 has 4
The shift control output signal S becomes "0", and this "0"
is input to logic module 1 as input control input signal SO.
is input. Further, since this module 11 is not connected to the immediately preceding module, the shift control input signal S1 is "0". Therefore, the signals input to logic module 1 and 2 are such that both aO and 01 are "0" and SO is "0".
0'', Sl is 0, and in this case, the module 11 stores the number 6 stored at time n-1 as indicated by the broken line α.
is selected by a multiplexer at time n and stored. The relationship between the input signals aO101, SO and Sl, the output signals α, h, and the output Rn of the module regarding logic module 1 and logic module 2 at this time is shown in the uppermost part of Table 1.

As is clear from FIG. 4, the output signals a and h of the logic modules in Table 1 are as follows: As for the second and third modules 12 and 13, the stored data is 5 for input data 3, similar to module 11. , 4, there is a relationship of I<H, so SO is "0",
Also, the shift control input signal S from the left side is
1 becomes "0".

Therefore, it performs the same operation as module 11, and the result is shown in Table 1. Modules 12 and 13 are indicated by broken lines and do not perform any processing on their own data, as shown in c.

On the other hand, since the data stored in the fourth module 14 is 3, there is a relationship of ≦R.

Therefore, the shift control output signal S of 4 becomes "1" to the comparator 1, and this "1" is input to the logic module 1 as the input control input signal 5ol-IJ to the logic module 2, and the shift control input signal S from the previous module 13 Since S1 is "0", the operation is as shown in Table 1 (2). That is, the data 6 that has been stored so far, such as %d in FIG. 5, is transferred to the next stage module 15, and new data 3, such as %d, is taken in.

Since modules 15 and 16 have a relationship between new input data and their own data, the input control input signal SO to logic module 1 and 2 is "1", and the shift control input signal S1 from each previous module is "IJ". We obtain the logic shown in Table 1 (■).

Therefore, as shown by the dashed line f,1 in FIG.
5. Each data 2 and 1 of L6 is sent to the next stage module 16.1
7 respectively. In this way, 6, 5, 4,
When new data 3 is inputted, the data arranged as 3 and 2.1 can be sorted and output as 615 degrees 4.3, 3, 2.1.

FIG. 6 shows a state in which the modules connected in an array can be connected in multiple stages by connecting them to each other using a shift data signal and a shift control signal. When the data width is large, for example, the first The data width of the diagram is 8 bits,
The data width in FIG. 6 is 18 bits, which is effective for high-speed arithmetic processing.

(6) Effects of the Invention As described above, according to the present invention, by comparing newly input data and already stored data, the self-processing process is performed based on the relationship between the data of the immediately previous module and the data of the immediately following module. Single modules that determine the data to be calculated can be connected in an array to perform high-speed arithmetic processing while inputting data.

[Brief explanation of the drawing]

FIG. 1 is a sort operation circuit diagram according to the present invention, and FIG.
The configuration diagram of each module in the figure, Figure 6 is the connection diagram of each module, Figure 4 is the configuration diagram of the logic module, and Figure 5 is the configuration diagram of each module.
FIG. 6 is a diagram showing a modification of FIG. 1. 1... Sort calculation circuit, 11.12...1n...
Module, 1 to 1...Multiplexer, 1 to 2...
・Logic module, 1 to 3... U, chi, 1 to 4...
comparator. Patent applicant Fujitsu Ltd. Patent application agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akiyuki Yamaguchi

Claims (1)

[Claims] It consists of a comparator, a multiplexer, and a logic module necessary for the multiplexer, and determines the data to be processed by comparing the input data with the data stored in the immediately preceding module, the immediately succeeding module, and its own data. 1. A sorting operation circuit comprising a plurality of modules having a single function connected in an array.