JPS6016649B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a data processing device in which the length of data to be operated on and the result of operation are larger than the length of data to be computed by an arithmetic unit.

Conventionally, with this type of counterfeiting, it was necessary to perform special processing as an overflow check process by zeroing out the data area according to the size of the data area storing the calculation results.

For example, FIG. 1 shows an example of an arithmetic unit layer having a temporary storage device and two arithmetic registers. Using this device, the length of 2 words (1
Regarding the case of the first example (A+B→C), add data A and data B, which are packed type + hexadecimal data (3 lines), and store them in data C, which is packed type + hexadecimal data with a length of 3 words (24 digits). explain. For simplicity, it is assumed that each data has the same number of digits after the decimal point. Data A and data B are read from the storage device 1 via the storage register 2 and stored in the temporary storage device 3. During calculation, calculation register A6
The least significant word of data A indicated by the arithmetic address register A4 is stored in the arithmetic register B7, and the least significant word of the data B indicated by the arithmetic address register B5 is stored in the arithmetic register B7. The contents of both arithmetic registers are added by the arithmetic unit 8 and the result is stored in the word indicated by the arithmetic address register B5. Next, in both operation address registers 4.5, step forward to point to the higher order word following the lower word, in the example in Figure 1, the highest word, and as in the case of the lowest word, the operation result is transferred to the operation address. It is stored in the location indicated by the register 85. As a result, the calculation result will be stored in the second storage area in which data B in the temporary storage device 3 was stored. In order to store this calculation result in data C (3 words) in the storage device 1, it is necessary to pad the higher-order word with 0. This operation stores zero in the upper one word of the operation result in the temporary storage device 3 according to the receiving data (data C), and transfers the operation result from the temporary storage device 3 to the data C of the storage device 1 as the operation result of three words. This is done by outputting. Alternatively, the calculation result of two words can be stored in storage device 1.
This is achieved by detecting the need to transfer one more word to data C after storing it in data C, generating 0 in storage register 2, and performing control to add 0 to the higher-order word of data C. Ru. In the above-mentioned Ryoma, when storing calculation data, the receiving data is zero-filled by zero-filling processing in the temporary storage device 3 or zero-generating processing in the storage register 2, so special control is required. Efficiency during transportation deteriorates.

Next, data A is positive and has a data length of 3 words, and its valid data exists only in the lowest word, data B is positive and has a data length of 1 word, and the relationship between data A and data - B is A second example case in which A-B→C is performed when A×B.

In the apparatus shown in FIG. 1, the subtraction result is written to the data A area of the temporary storage device 3. In this subtraction, operations A and B regarding the least significant word are first performed, resulting in a borrow. In order to calculate the second hyponym, data B
Since there is only one word, it is necessary to store 0 in the arithmetic register B7 to perform subtraction. A
-B<o is found. When expressing numerical values by appending tens and ones signs instead of using complements as is used to express decimal data, it is necessary to calculate the orange number of the result of A-B above, so the calculation result It becomes necessary to perform three more subtractions for the three words. If the data lengths of the calculation target data are different in this way, and if the decimal point position is shifted and the word-by-word correspondence of the calculation target data is lost, the word shift is detected and the calculation register A6 or It is necessary to perform an operation by storing 0 in B7.

Furthermore, in the above subtraction, since the top two words of data A are zero, it is sufficient to perform one column number processing subtraction on the subtraction result of the lowest word (A-B). For this, three subtractions and three-times complement subtraction are performed. In this way, the control function during calculation and the number of calculations are increased. An object of the present invention is to provide an apparatus that efficiently transfers arithmetic results without performing special control to generate 0 when storing them in destination (receiving) data.

Another object of the present invention is to provide a device that efficiently performs calculations by eliminating the need for control to detect surpluses and deficiencies and generate 0s in order to compensate for calculation data when there is excess or deficiency in correspondence between data to be calculated. It is about providing.

Still another object of the present invention is to provide an apparatus that can improve the calculation speed by determining the calculation range according to the characteristics of the content of the data to be calculated and reducing the number of calculations as much as possible. .

That is, the data processing device of the present invention includes a storage device for storing instructions and data, a temporary storage device divided into a plurality of words for temporarily storing operation target data and operation results, and a storage device in the temporary storage device. an arithmetic address register that specifies a word; a content display that displays characteristics of each word in the temporary storage device and is indicated by the outside of the arithmetic address register;
a data checker that checks whether the content of the input data to the temporary memory bag is a specific value or not and outputs the test result to the content display; a selection circuit for selecting the content of the word in the temporary storage device or a specific content indicated by the content indicator according to a corresponding content indicator when a word in the storage device is to be discussed; an arithmetic unit that inputs data and outputs processing results to the temporary storage device; an arithmetic range determining circuit that determines a required arithmetic range by referring to the content display; and an output and arithmetic address of the arithmetic range determining circuit. an address comparison circuit that compares the contents of the register and generates a comparison signal necessary for arithmetic control; and a control device that controls a process of arithmetic operations and transfer of the arithmetic results stored in the temporary storage device to the memory bag hawk. It consists of

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. In this embodiment, the calculation target data always has the same digits after the decimal point. The external storage device I0 stores instruction sequences such as addition instructions and data. External storage device 1
The instruction stored in 0 is specified by the instruction address register 12 and read into the instruction register 14. The data stored in the external storage device 101 is specified by the data address register 16 and sent to the storage register 18. It is also possible to store the contents of the storage register 18 in the external storage device 10 designated by the data address register 16. The shift circuit 20 performs a shift to change the byte position of data in the external storage device 10 to a byte position of data that is easier to perform arithmetic processing. For example, in the temporary storage device A22, the lowest word is stored right-aligned, so the shift circuit 20 shifts the contents of the storage register 18 accordingly. In addition, when it is not possible to make all the 8-digit output of the shift circuit 20 into the data to be calculated, for example, when the data to be calculated is 3 digits, 0 is inserted into the remaining upper 5 digits. It also has a function to output digits. Also, when transferring the calculation results to an external storage device, byte alignment is required and the shift circuit 20 is used. This shift circuit 20 is generally used in a subordinate computer having an arithmetic function and a transfer function, and is mainly composed of data selection elements. The output from the shift circuit 20 is stored in a temporary storage device 22, and a data checker 24 checks whether all the data of one word is 0. If all the data is 0, it outputs 0.
If a number other than 0 exists, 1 is output. The data checker 24 is constituted by ordinary logic elements or comparison elements. The storage position of the calculation target data in the temporary storage device A22 is specified by the calculation address register 26. Additionally, the output of data checker 24 is also stored in the bit in content indicator 28 specified by arithmetic address register 26. The content display 28 consists of a number of flip-flops equal to the number of words in the temporary storage device A22. Therefore, each bit of content indicator 28 corresponds to each word of temporary storage 22 and indicates whether the content of the word is all zeros. Additionally, all bits of content indicator 28 can be cleared. When reading out the word specified by the operation address register 26 as operation target data, the information of the corresponding bit in the content display 28 is used as a selection signal of the selection circuit 30. In response to this selection signal, the selection circuit 30 selects the word or data equal to 0 in the temporary storage device A22 indicated by the arithmetic address register 26, thereby obtaining the data to be computed indicated by the arithmetic address register 26.
The selection circuit 30' is constituted by a data selection element that selects one of two inputs as an output. Selection circuit 3
The output of 0 serves as an input to the arithmetic unit 32. Arithmetic unit 32
The system uses a commercially available 4-bit ALU element and is configured to perform 8-digit calculations in one calculation clock. Also, selection circuit 3
The output of 0 is shifted by the shift circuit 20 to be suitable for storage in the receiving data and is sent to the storage register 18. The contents of storage register 18 can be written to external storage device 10. The other input data of the arithmetic unit 32 is the output of the shift circuit 20. This input data is also data that has been shifted by the shift circuit 20 so that the least significant digit of the data to be operated on is located at the right end of the word. The calculation result of the calculation unit 32 is stored in the storage device A22. The storage position at this time is the position indicated by the calculation address register 26. At the same time as the data is stored in the temporary storage device A22, the data checker 24 checks whether the input word is all 0 or 0 as a calculation result, and the data is stored in the corresponding content display 28. Each bit of the content display 28 is referenced by the calculation range determining circuit 34 and is used as an upper effective address signal ( (expressed in 3 bits and indicating addresses 0 to 7). The calculation range determining circuit 34 is constructed from a commercially available priority encoder. The address comparison circuit 36 increments each time the arithmetic target word is computed, and compares the contents of the arithmetic address register 26, which is incremented in order to sequentially perform arithmetic processing, with the upper effective word address. If word address≦operation address register contents, 1 is sent to the control device 38, otherwise 0 is sent to the control device 38. Since the address comparator 36 compares 3 bits of the operational address register 26 with 3 bits of the upper effective word address signal, it is constituted by a commercially available 4-bit comparison element. The control layer 38 is a device configured by a commonly used microprogramming technique and has a function of decoding instructions and performing processing according to the instructions. Note that the control system using a microprogram is already used in the computer 360 series sold by mm. As an example, a case will be described in which the computation represented by C=A+B, which can be specified in various languages, is performed using the bag counterfeit shown in FIG. Here, data A is an integer with one row of decimal packed data, data B is an integer with 7 digits of decimal packed data, and data C is an integer with 24 digits of decimal packed data. The processing content is to store the result of adding data A and data B in data C. The numerical contents of data A and data B are as shown in Figure 3, data A = 1230123, data B; 32.
It is 10321. The temporary storage device A22 is composed of 8 lines, each word being 4 bytes. When the addition instruction stored in the external storage device 101 is designated by the instruction address register 12, this instruction is stored in the instruction register 14.

The control device 38 refers to the instruction register 14 and controls the addition instruction as described below. Content display 2 at the start of calculation processing
8 is cleared, and the contents of the arithmetic address register 26 are set to 0 in order to store the least significant word of data A to be initially stored in the temporary storage device A 22 at address 0. The least significant word of data A is indicated by data address register 16 and read from external storage device 10 to storage register 18 . This data is shifted by the shift circuit 20 so that the least significant digit is located at the right end of the column, and is stored at address 0 of the temporary storage device A 22 designated by the arithmetic address register 26. At this time, the output of the shift circuit 20 is checked by a data checker 24 to see if all are 0. The output of the shift circuit 20 is 01
Since it is 230123, the output 1 of the data checker 24 indicating that it is not 0 is stored at address 0 of the content display 28. Subsequently, in order to store data A in the temporary storage device A22, the arithmetic address register is set to 11. Data address register 16 is also incremented to point to the second lower word (most significant word) of data A in external storage device 10. This second
The lower-order word is read into the storage register 8, the output of the shift circuit 20 is stored in address 1 of the temporary memory storage device A22, and the output of the data checker 22 is stored in address 1 of the content display 28 in the same manner as the lower-order word. The output of the data checker 24 is the shift circuit 2
Since the output of 0 is 0000000, it becomes 0. The resulting state set in the temporary storage device A22 and the content display 28 is shown in FIG. Note that × indicates 0 or 1. When the process of reading data A from the external storage device 10 is completed, the data address register 16 stores contents indicating data B in the external storage device 10.

Data B specified in this data address register 16
The least significant word of is stored in storage register 18. As a result, the shift circuit 20 outputs the least significant word of data B, which becomes an input to the arithmetic unit 32. The lowest word output of data B, which is the output of the shift circuit 20, is shown in FIG. Data A is also stored with 0 in the arithmetic address register 26 in order to perform addition processing starting from the least significant word. As a result, the 1 stored in the 0 field of the content display 28 is output as the selection signal of the selection circuit 30. With this selection signal, 01230123 stored at address 0 of the temporary memory Hishitaka A22 becomes the output of the selection circuit 30 as the lowest word of the data A, and is output to the arithmetic unit 32. The lowest word of B is added and the result (04440444) is stored at address 0 of temporary storage device A22. The input data at this time is checked by the data checker 24, and since the word to be stored is not 0, 1 is stored at address 0 of the content display 28. Data B is 7 digits and fits within one word, and no carry occurs in the arithmetic unit 32, so the addition of data A and data B is 1
It ends in times. FIG. 6 shows the contents of the temporary storage diamond A22 when the calculation results are stored. When a calculation result is obtained, this result is stored in data C occupying three words in the external storage device 10.

0 is stored in the calculation address register 26 to store from the lower word.
is stored, and the content 1 at address 0 of the content display 28 is output as a selection signal. Since the selection signal is 1, the contents of address 0 (0444) of the temporary storage device A22 are selected as the output of the selection circuit 30 and stored in the data C of the storage register 18 via the shift circuit 20. The data address register 16 stores contents indicating the least significant digit of the data C in the external storage device 10, so by referring to this, the least significant word of the operation result in the storage register 18 is stored in the external storage device 10. 10. Next, in order to store the operation result in the second lower word of data C, the operation address register 26 is
is 11, the content 0 at address 1 of the content display 28 is output as a selection signal, and a decimal number (allo) in which all eight digits are 0 is selected as the output of the selection circuit 30. This is a shift circuit similar to the lowest word. 20, stored in the second lower word of data C in the external storage device 10 via the storage register 18.
In order to store the operation result in the third lower word of data C, the operation address register 26 is set to 11 to indicate the contents of address 2 of the contents display 28, and outputs the contents 0 as a selection signal. At this time, the calculation result is not stored at address 2 of the temporary storage device A22, but since the selection signal is 0, the selection circuit 30 outputs allo to select the third lower word of the data C in the external storage device 10. (Since data C is 3-word data, it means the most significant word) and allo is stored, and the series of addition instruction processing is completed. In the embodiment of FIG. 2, C
A case in which the subtraction of =A-B is performed will be explained.

It is assumed that data A, data B, and data C have the same data length and value as the data used in the above description. A subtraction instruction is stored in the instruction register 14, and the control device 38 starts controlling the subtraction operation.

Similar to the addition instruction, data A is stored in the temporary storage device A22.
The two words are stored at addresses 0 and 1, and the contents are the same as in FIG. At this time, the calculation range determining circuit 34 refers to the contents of the content display 28 and outputs 0 as the upper effective word address since the highest address that is 1 is address 0. Operation address register 2 at the start of subtraction
6 is stored as 0, and the lowest word 012 of data A is sent to the arithmetic unit 32.
30123 is output from the selection circuit 30. Arithmetic unit 32
The other input of is sent the least significant word 03210321 of data B shown in FIG. 5 from the shift circuit 20 to perform subtraction.
As a result, Satoshi 01 Group 02 is stored in the temporary storage device A22 as the output of the arithmetic unit 32. This is shown in Figure 7. At this time, the arithmetic unit 32 generates a borrow. Here, the address comparison circuit 36 compares the higher-order effective word address with the contents of the arithmetic address register 26, and since 0=0, the magnitude comparison signal becomes 1. As a result, the control device 38 recognizes that there is no need to perform subtraction using a borrow on the second lower word of data A, and determines that data A<data B. In order to express the obtained result as an absolute value, 0 is stored in the arithmetic address register 26, and [0-selection circuit output]
Processing is performed by a computing unit 32. In other words, 01 group 01 scale 02 is calculated, and as a result, 01 and 01 group is stored at address 0 of the temporary storage device A22 as the output of the arithmetic unit. This is stored in the data C of the external storage device 10 in the same manner as the addition instruction. At this time, a negative code is stored in the code display data area. In the embodiment shown in FIG. 2, a case will be described in which the data length of data A is made up of a shorter number of words than the data length of data B. A situation arises in which the calculation corresponding to the data length of data A is completed and uncalculated data of data 8 remains. At this time, in order to calculate a word higher than data A, it is necessary to generate zero as data A corresponding to the remaining data B, but the content display 28 must be set to 0 before data A is stored. Autumn, no special control is needed to generate 0. As described above, according to the data processing device of the present invention, when data larger than the length of the calculation result is transferred when the calculation result is transferred, the control can be changed without changing the control depending on the data length of the calculation result. Let's do our best,
The transfer system becomes easier and the performance during transfer is improved.

Furthermore, when computing data stored in the temporary storage device whose word length is short, control for generating 0 for computing high-level words is not required, so computing performance is improved.

Furthermore, as shown in the subtraction process, by displaying the word-by-word contents of the data to be operated on, it is possible to detect the range where valid data is stored and reduce the number of operations, thereby improving computational performance. .

In addition, by using a register as an input to the selection circuit 30 of the embodiment shown in FIG. BLANK WHENZERO (
(Stores “blank” when data is 0)
Processing based on editing specifications can be easily performed.

In other words, when the content display 28 is all 0, all selection circuit outputs can be changed to blanks by storing blanks in the register.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional data processing device, Figure 2 is a block diagram showing a conventional data processing device.
The figure is a block diagram showing one embodiment of this invention, and FIG.
4 is a diagram showing the contents when the first data to be calculated is stored in the temporary storage device A, and FIG. 5 is a diagram showing the contents of the data to be calculated by the second data from the shift circuit. 6 is a diagram showing the contents when the addition result is stored in the temporary storage device A, and FIG. 7 is a diagram showing the contents when the subtraction result is stored in the temporary storage device A. . In the figure, 10...external storage device, 12...
...Instruction address register, 14...Instruction register, 16...Data address register, 18...
...Storage register, 20...Shift circuit, 22
...Temporary Memory Magic A, 24...Data Examiner, 26
......Arithmetic address register, 28...Content display, 30...Selection circuit, 32...
Arithmetic unit, 34...Arithmetic range determination circuit, 36...
. . . Address comparison circuit, 38 . . . Control device are shown respectively. Figure 0 Figure 2 Figure 3 Figure 4 Figure 5 Figure Power 6 Figure 7

Claims (1)

[Claims] 1. A storage device that stores instructions and data, a temporary storage device that is divided into a plurality of words that temporarily stores operation target data and operation results, and an operation address register that specifies words in the temporary storage device. , a content indicator that displays the characteristics of each word in the temporary storage device and is indicated by the arithmetic address register, and checks whether the content of the input data to the temporary storage device is a specific value. a data checker for outputting the test result to the content display; and a data checker for outputting the test result to the content display; a selection circuit for selecting a particular content whose word content in a temporary storage device is indicated by the signal of the content indicator;
an arithmetic unit that inputs the data selected by the selection circuit and outputs the processing result to the temporary storage device; an arithmetic range determining circuit that determines the required arithmetic range by referring to the content display; an address comparison circuit that compares the output of the range determination circuit and the contents of the calculation address register to generate a comparison signal necessary for calculation control; and an address comparison circuit that transfers the calculation and the calculation result stored in the temporary storage device to the storage device. A data processing device comprising a control device for controlling processing, efficiently performing calculations, and efficiently transferring the calculation results according to the data length of receiving data in which the calculation results are stored.