JPS60163822U

JPS60163822U - Daylay line

Info

Publication number: JPS60163822U
Application number: JP5215084U
Authority: JP
Inventors: 義昭赤地
Original assignee: ティーディーケイ株式会社
Priority date: 1984-04-10
Filing date: 1984-04-10
Publication date: 1985-10-31

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図はディレィラインの電気的等価回路図、第２図は
従来のディレィラインの具体的な構造を示す部分断面図
、第３図は同じく要部の斜視図、第４図は別の従来例に
おける部分断面図、第５図は本考案に係るディレィライ
ンの部分断面図、第６図は要部の斜視図である。９・・・・・・回路基板、１０・・・・・・回路部品、
１１・・・・・・ＩＣパッケージ、１２・・・・・・リ
ードフレーム、１３・・・・・・絶縁外装体、１５・・
・・・・切欠。Figure 1 is an electrical equivalent circuit diagram of a delay line, Figure 2 is a partial sectional view showing the specific structure of a conventional delay line, Figure 3 is a perspective view of the same main part, and Figure 4 is another conventional delay line. FIG. 5 is a partial sectional view of the delay line according to the present invention, and FIG. 6 is a perspective view of the main part. 9...Circuit board, 10...Circuit parts,
11...IC package, 12...Lead frame, 13...Insulating exterior body, 15...
...notch.

Claims

[Scope of utility model registration request]

An integrated circuit package having a plurality of stages of delay circuits, the delayed output of at least one of the stages is taken out through an integrated inverter circuit, and the inverter circuit is built in on the lower surface side of the circuit board on which the delay circuit is mounted. At the same time, a lead frame serving as an input/output terminal is placed on the lower surface of the integrated circuit package, and the pins provided on the integrated circuit package are connected to the conductor pattern on the circuit board and the lead frame to connect the circuit. In the configured delay line, the lead frame is bent toward the integrated circuit package and then bent in the opposite direction, and one of these lead frames faces the pinot of the integrated circuit package, The pins,
A delay line characterized by having a cutout to prevent contact with the delay line.