JPS60163521A - Digital filter - Google Patents

Abstract

PURPOSE:To decrease the capacity of a ROM and also to attain the use of a low-speed multiplier by using an odd number of output lines of delay elements led out of a shift register and providing an adder to the pre-stage of a multiplication means to decrease the number of times of multiplication. CONSTITUTION:An input signal A of an adder AD is extracted in the order of ...M2, M1,M0... in synchronization with a clock signal phi1, and an input signal B is extracted in the order of ...M7, M6, M5... in synchronizing with a clock signal phi2 (M0-M7; coefficients of multiplication). Since the output of the adder AD is A+B, the outputs are outputted in the order of ...(M2+M7), (M1+M6), (M0+M6), (M0+M5)..., the multiplication coefficients A1, A2 corresponding to them are switched alternately in synchornization with the signals phi1, phi2, inputted to a multiplier m1, the sum P, Q of the coefficients of the odd number order and the even number order are outputted alternately. Similar operations are executed for other multiliers m2-m4 and the operation corresponding to P+Q is obtained as an output of the adder AD.

Description

[Detailed Description of the Invention] Technical Field> The present invention relates to a digital filter, and more specifically, the present invention relates to a digital filter.
Related to phase linear acyclic digital filters.

<Problem to be solved> In digital audio equipment, an analog low-pass filter is used in combination to remove harmonic components contained in the output of the digital-to-analog converter. FIG. 1 shows a circuit block diagram in that case, and FIG. 2 shows a frequency characteristic diagram. In order to pass the original signal A and block the harmonic components B, C, and D, a low-pass filter having the characteristics shown by the dotted line E must normally be used. However, if a filter with such steep characteristics is used, distortion will occur in the treble part of the audio signal, which is undesirable.

Therefore, as shown in the block diagram of Fig. 3, a digital filter is provided before or after the digital-to-analog converter, and as shown in Fig. 4, this digital filter converts the harmonics closest to the audio band to be reproduced. If component B can be removed, that is, if a digital filter with the characteristics shown by the dotted line F is used, only the harmonic component C shown in FIG. 5 remains, and this harmonic component C
can be removed by an analog low-pass filter with relatively gentle frequency characteristics G, making it possible to reduce waveform distortion and reproduce a signal faithful to the original sound.

FIG. 6 shows the circuit configuration of a conventional acyclic digital filter in which the output sampling frequency is twice the input sampling frequency. DI~D13 are delay elements with equal delay time T, Al~AI4 are coefficients, m1~
m14 is a multiplier, and a is an adder. Furthermore, when the digital filter is phase linear, there is an Al
=AI4. A2 = AI9. A3 = AI2. A4
“An, As = A+o.

A6 = A9, A? There is a relationship of =Ae.

In such a digital filter, for example, as shown by the dotted line F in Fig. 4, the band centered at 44.1 KHz is attenuated and removed, and in order to pass the original signal A, the frequency band centered at 88.2 X Hz, which is twice that frequency, is removed. In other words, when making the output sampling frequency twice as high as the input sampling frequency, the method usually involves inserting data representing zero at predetermined intervals T between the input data of the digital filter. is used. In this system, as shown in FIG. 6, at a certain time t, even-numbered multiplier m2. The input data of m4, -.m+4 becomes 0, and at time (t+T) after time T, the odd-numbered multiplier m1. The input data of m3...m13 becomes 0.

Therefore, in order to reduce the number of multipliers by half, the circuit configuration shown in FIG. 7 can be considered. The seven multipliers m1---m7 each have coefficients AI+Aa and As at time t.
, A? , As , Att, Ala and the output data of the delay element are executed, and the next time (t+7)
In the case of coefficient A2. A4. A6. AEl, AIO.

Al2. Multiply Al4 by the output data of the delay element. In this way, by alternately performing multiplication on odd-numbered coefficients and even-numbered coefficients, the same output as the digital filter of FIG. 6 can be obtained.

However, the number of multiplications cannot be reduced any further.

In general, multiplication requires a longer calculation time than addition and subtraction, and if it were to be executed in a short time, the hardware would be complicated and expensive. Therefore, in data processing of digital audio equipment, it is important to reduce the number of products in the product-sum operation.

<Object of the Invention> Therefore, an object of the present invention is to provide a method for reducing the number of multiplications as much as possible in a phase linear acyclic digital filter.

<Structure of the Invention> The digital filter of the present invention configures a shift register by continuously connecting a predetermined number of delay elements having a predetermined delay time, and performs a product-sum operation on the output of each delay element.
In a phase-linear acyclic digital filter in which the output sampling frequency, which is the product-sum operation output, is twice the input sampling frequency, which is the input of the shift register, the number of frequency lines of the delay element derived from the frequency register is set to an odd number. The present invention is characterized in that a pre-stage adder is provided in the pre-stage of the multiplication means for performing the product-sum calculation.

<Example> FIG. 8 shows an example of the present invention. In the figure DI D
7 is a delay element, φ1 and φ2 are two-phase clock signals, A
Dr-A Da represents a previous-stage adder, ml---m4 represents a multiplier, AD represents an adder, and A I-A 7 and 0 represent multiplication coefficients.

9 and 10 are modified versions of FIG. 8 to explain the operation of this embodiment. FIG. 9 is a diagram corresponding to FIG. 6 of the conventional example, and compared to FIG. 6, the final stage delay element D13, the multiplier m14 related to its output, and the multiplication coefficient AI4 are missing, and as a result, , the difference is that the output lines from the delay element array are odd numbers. In FIG. 9, the input data and zero data are input alternately, and the multiplication for zero data is omitted in FIG. 1θ. In FIG. 1θ, calculations are performed in synchronization with the sampling frequency, and odd-numbered coefficients (Al, Aa, As, A?, A9°A11 .
Al3) and even-numbered coefficients (A2.A4.A6゜Ae
, /Ha, Al2) are performed alternately.

Here, since the digital filter is phase linear, Al
=A113. A2 = AI2. Aa=Ao, A4=
A+o.

The following relationships hold: As = A9, A6 = A[3. What should be noted here is that pairs with equal coefficients are either odd-numbered or even-numbered.

Therefore, the timing of executing the multiplications coincides, and it becomes possible to first add pairs of equal ζ coefficients and then execute the multiplication.

That is, in FIG. 10, if the content stored in each delay element is M1--M7, the sum P of multiplication of odd-numbered coefficients is P = M+ ・AI + M2 ・Aa + M3 ・A5
+M4・A? +M'5 ・A9 +M5 ・All+
M7 ・Ata Al = Ata, Aa = Ao, As = As, so P = (Ml +M?) AI + (M2 +M6
) A3+ (Ma +Ms) As +M4 A
?・-(l) The sum Q of multiplication of even-numbered coefficients is: Q=M+ −A2+M2 ・A4+M3 ・A60M4
・Ae +Ms ・A+o+M6 ・Al2A2 =
AL2. Since A4 = A+o, Aa = Ae, Q = (Ml +M6) A2 + (M2 +MS
) A4+ (Ma +M4) Ae −(2)(
As can be seen from the comparison between Equation 11 and Equation (2), the groups to be added are different in the multiplication of odd-numbered coefficients and the multiplication of even-numbered coefficients. Therefore, by using two-phase clock pulses φ1 and φ2, M
In the embodiment shown in FIG. 8, l.-M4 and Ms-M7 are taken out at different timings.

FIG. 11 shows a time chart of the arithmetic processing of the part related to the multiplication coefficients AI and A2 in the embodiment of FIG.

One input signal A of adder AD1 is clock signal φl.
In synchronization with...-M2. M1, Mo- are taken out in this order, and the other input signal B is -M7. Ma, Ms-- are taken out in this order. Since the output C of the adder AD+ is (AlB),
-, (M2 +M7), (Ml +M7).

(Ml + Ma), (Mo + Me), (Mo + Ms
)-, and the multiplication coefficients for it are output as the signal φ1. A1 and A2 are alternately switched and input to the multiplier m1 in synchronization with φ2. As a result, the multiplier ml
(The first term of Equation 11 and the first term of Equation (2) are output alternately. Similar operations are performed for the other multipliers m2, m3, and m4, and the output of the adder AD corresponds to P+Q. You can obtain the operation that

FIG. 12 shows a second embodiment of the invention. This embodiment differs from the previous embodiment in that the delay element array is shifted by a common clock signal φ1, and the pre-stage adder A D 1-A
A switch S1.D synchronizes the input signal of D a with the timing of multiplication. The configuration is such that switching is performed by S2 and S33.

FIG. 13 shows a third embodiment of the present invention, FIG. 14 shows the internal configuration of the first delay element DA of FIG. 13, and FIG. 15 shows the internal configuration of the second delay element DB.

1st. Both second delay elements DA and DB have a memory 11 having a predetermined delay time, a control input line 12, a gate circuit 13 for switching, and a circulation circuit 14, and when the control signal SEL is "1" The contents of the memory are retained in a circular manner, and the contents of the memory can be serially output to the outside. When the control signal SEL is 10'', the circulation loop is broken and the shift input data from the shift input line 15 is transferred to the memory 11. The data previously stored in the memory is shifted from the shift output line 16 to the next stage.The data output line 17 for the pre-stage adder is connected to the first delay element D.
A is derived from the output terminal of the memory 11, and second delay element DB is derived from the input terminal of the memory 11.

FIG. 14 is a time chart showing the operation of this third embodiment.

Now, when 5EL-“1”, data r1234J is stored and held in the memory of the first delay element DA and is derived, and then when 5EL-“0”, new data r5678J is shifted in. The old data r1234J is derived accordingly, and 5EL="
It is assumed that data r5678J is stored and derived when the value becomes 5EL-1" and is derived while being stored. In addition, data rabcdJ is initially stored and retained in the memory of the second delay element DB when the value is 5EL-1". When that data is derived and the next time it becomes 5EL-0'', new data refghJ is shifted in and at the same time the data ``
efghJ is derived, and when 5EL=“1” again, data refgh” is derived while being stored and held.

In that case, the two input lines E of the first pre-stage adder AD+,
F signal, its adder AI]1's output line G signal, multiplier m1's multiplication coefficient A1. A2 changes as shown in FIG. 14, and the same calculation results as in the embodiment described above are obtained. This embodiment is an effective method when processing data serially.

FIG. 15 shows a fourth embodiment of the present invention. In this embodiment, the plurality of multipliers m l -1n 14 and one adder a shown in FIG. 6 are omitted, and the ROM 21 and the accumulator 2
This is an application of the technical concept of the present invention to a known method for realizing the same function in No. 2. All multiplication results are written in this ROM 2L, and the multiplier and multiplicand are used to designate the address of the ROM so that the previously written product can be read out.

<Effects of the Invention> According to the present invention, since the number of multiplications is reduced, it is possible to use a multiplier that is slower than the conventional one, and the multiplier can be made smaller. Also, in the method using ROM shown as the fourth embodiment, the number of types of multiplication coefficient values is reduced, so the RO
M capacity can be significantly reduced.

[Brief explanation of drawings]

Figure 1 is a block diagram explaining the demodulation system of digital audio equipment, Figure 2 is a frequency characteristic diagram explaining the demodulation, Figure 3 is a block diagram when a digital filter is used in the system in Figure 1, 4 and 5 are frequency characteristic diagrams illustrating demodulation of the system shown in FIG. 3. FIGS. 6 and 7 are circuit configuration diagrams showing conventional examples of digital filters. 8 to 17 are all drawings related to embodiments of the present invention, in which FIG. 8 is a circuit diagram showing the first embodiment, and FIG. 9 and FIG. 10 are diagrams explaining the principle of the present invention. , Figure 11 is the first
12 is a circuit diagram showing the second embodiment, FIG. 13 is a circuit diagram showing the third embodiment, and FIGS. FIG. 13 is a circuit diagram showing the internal configuration of the first and second delay elements A and H, FIG. 16 is a time chart explaining the operation of the embodiment shown in FIG. 13, and FIG. 17 is a fourth embodiment. FIG. D, DA, DB - Delay element A D - Adder in the previous stage ml, m2 "' - Multiplier Patent applicant Sharp Corporation Representative Patent attorney Arata Nishida 1 Figure 3 Figure 4 Figure 11 Figure 12 Figure 13 Figure 16, EL Figure 17 Procedural amendment stamp button 3, Person making the amendment Relationship to the case Patent applicant address Name (50) 22-22 Nagaike-cho, Abeno-ku, Osaka
4) Sharp Corporation Gen Representative: Saeki Asahi 4, Agent address: Miyuki Building, 15-13 Usagano-cho, Kita-ku, Osaka Telephone: (06) 315-7481-26 Subject of amendment Description and drawings 7 Contents of amendment Attached Contents of the correction (11 Delete “or the latter part” on page 1, line 12 of the specification. (2) “Frequency register” on page 5, line 14 of the specification.
Correct it to "shift register." (3) Change the "frequency line" on page 5, line 14 of the specification to [output line -
I am corrected. (4) Change “Figure 14” on page 11, line 6 of the specification to “Figure 16”
"Fig." is corrected. (5) Change “14th” on page 11, line 5 of the specification to “16th”
” he corrected. (6) “Figure 15” on page 11, line 9 of the specification
Figure 7” is corrected. (7) “Delay elements A, BJ” on page 12, line 20 of the statement box
is corrected as [delay elements DA, DBJ. (8) The drawings, Figures 7, 8, and 13 will be corrected as shown in the attached sheet. Figure 7

Claims (1)

[Claims] A shift register is configured by continuously connecting a predetermined number of delay elements having a predetermined delay time, and by performing a product-sum operation on the output of each delay element, the output sampling frequency, which is the product-sum operation output, can be determined by the output sampling frequency of the shift register. In a phase-linear acyclic digital filter whose input sampling frequency is twice as high as the input sampling frequency, the number of output lines of the delay element derived from the shift register is an odd number, and the filter is used at the front stage of the multiplication means for performing the product-sum operation. A digital filter characterized in that a pre-stage adder is provided in the filter.