JPH0468709A - Digital filter - Google Patents

Abstract

PURPOSE:To attain filter processing for a multiplex signal with the scale of the hardware almost equal to that of an FIR filter having the same tap number with respect to a signal not multiplexed by providing a coefficient register outputting two coefficients alternately to one input of a multiplier synchronously with the input of a data at each tap and a delay register retarding an output of an adder by two cycles, and outputting the result to a succeeding tap adder to the filter. CONSTITUTION:When a signal A1 is inputted at first, a 1st tap MPY 3-1 multiplies the input data (A1) with the output HA1 of a coefficient register 2-1, and the result (HA1*A1) is inputted to the pre-stage of a delay register 5-1 of the 1st tap. When a signal B1 is received, the 1st tap MPY 3-1 multiplies the input data (B1) with the output HB1 of the coefficient register 2-1, and the result (HB1*B1) is inputted to the pre-stage of the delay register 5-1 of the 1st tap. Simultaneously the data (HA1*A1) stored in the pre-stage of the delay register 5-1 is shifted to its post-stage.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital filter in digital signal processing.

(Prior Art) FIG. 2 is a block diagram showing an example of the configuration of a conventional FIR type filter circuit, in which 1 is an input register (IN) for inputting input data, and 6-1 to 6- are each tap. Coefficient registers that store coefficients, 7-1 to F- are multipliers (MPY) that perform multiplication in each tag, and 8-2 to g- add the multiplier output and the previous stage addition result in each tap. The adders 9-1 to 9- are delay registers (D) that store the adder results of the previous tap, and the number of taps is y.

This FIR type filter circuit performs the filter operation shown in equation (1).

However, Yn: Output data Xn-1' Input data Hl: Tap coefficient = q-p+1 In other words, in FIG. The input data is multiplied by the coefficients stored in each coefficient register 6-1 to 6-k. The multiplication result of the first tap, ie, the output of MPY 7-1, is directly input to *D9-1. Multiplication result of other taps, i.e. MPY 7-2
The outputs of ~7- are input to adders 8-2~B-k, and are added to the data of the previous taps D9-1~9-(k-7), respectively, and are added to the data of D9-2~9- of each tap. It is input to k.

By repeating the above operations every time input data is input, the calculation results of equation (1) are sequentially output from the final output.

In addition, as shown in Fig. 3, two beliefs -% (hl, also
The multiplexed signal, in which the
When performing the filter operation shown in Fig. 4, the multiplexed signal is separated into two signals Ai and Bi, and each separated signal Ai and B is filtered by a separate FIR type filter. Perform calculations. It should be noted that each of the above-mentioned FIR type filters has the same configuration as the FIR type filter shown in FIG.

(Problem to be Solved by the Invention) However, since the configuration shown in FIG. 4 has two FIR filters, the hardware scale is greater than that of an FIR filter with the same number of taps and non-multiplexed signals. The present invention has the problem that when performing FIR filter calculation on each signal in the multiplexed signal described above, the FIR type filter with the same number of tags on the non-multiplexed signal is used. Therefore, in order to eliminate the problem of increased hardware scale, it is possible to perform filter processing for multiplexed signals on a hardware scale that is approximately equivalent to that of an FIR type filter with the same number of taps for non-multiplexed signals. The purpose is to provide a digital filter that can.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides an F'IR type digital filter that performs FZR filter operation for each multiplexed signal on an input signal in which a plurality of signals are multiplexed. , a coefficient renostar that stores the same number of coefficient data as the multiplexed signal and outputs the corresponding coefficient data in synchronization with the signal; and a multiplier that multiplies the coefficient data from the coefficient register by the data of the input signal. , an adder that adds the data from the multiplier and the data from the delay register of the previous tag, and a delay register that delays the data from the adder by a number of cycles equal to the number of multiplexed signals. This is provided for each tap.

(Operation) In the FIR type digital filter, the coefficient register of each tap sequentially outputs corresponding coefficient data to the multiplier in synchronization with the multiplexed signal. Therefore, each multiplier multiplies each multiplexed signal with the corresponding coefficient data.

Furthermore, the data output from the adder is delayed by the same number of cycles as the number of signals multiplexed by the delay register, and then input to the adder of the next tap.

Therefore, each adder adds signals of the same type for each multiplexed signal. Thereby, each of the multipliers and adders can be used in common for each multiplexed signal, and it is possible to realize a circuit of approximately the same scale as the hardware of an FIR type filter for non-multiplexed signals.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.
The FIR filter operation is performed on a signal in which various types of signals are multiplexed.

In FIG. 1, 1 is an input register (IN) that inputs an input signal, 2-1 to 2- are coefficient registers that store two types of tap coefficients for each tap, and 3-1 to 3- are coefficient registers that store two types of tap coefficients for each tap.
is a multiplier (MPY) that performs multiplication at each tap, 4
-2 to 4- are adders that perform addition in each ship, 5
-1 to 5- are delay registers for delaying data by two cycles at each tap and outputting the data (however, delay register 5- at the last tap is delayed by one cycle).

The output of INI is connected to the input of MPY 3-1 to 3- of each tap, and the output of coefficient register 2-1 to 2-3 of each tap is connected to the input of MPY 3-1 to 3- of each tap.
The output of 2- is connected to the coefficient input of each MPY 3-1 to 3-, and the output of each MPY s-z-: s-k is connected to the two inputs of each adder 4-2 to 4-. connected to one of the inputs. However, the output of MPY 3-1 is connected to the input of delay register 5-1. In addition, the output to each adder 4-2 to 4- is output to each delay register 5-2 to
5-, each delay register 5-1 to 5-
The output of (k-2) is connected to the other input of the adder 4-2 to 4-4- of the next tap. However, the output of the final tap to the delay register 5- is connected to the output terminal.

Further, when the signal Ai is inputted to the MPY 3-1 to 3-n, the coefficient registers 2-1 to 2- in each step output coefficients HA i (HA1 to HAk),
When signal B is input, coefficient)(Bi()n31~
HBk).

Next, signal A1. The operation of this embodiment when a Bi multiplexed signal is input will be described.

[1] First, when signal A1 is input, the first tap M
In PY 3-1, the input data (A1) is multiplied by the output HAI of the coefficient register 2-1, and the result (HAI
*A 1 ) is input to the front stage of the first tag delay register 5-1.

[2] Next, when signal B1 is input, the first tap M
In PY 3-1, the input data (B1) is multiplied by the output HBI of coefficient register 2-1, and the result (HB1*
B1) is input to the previous stage of the first tap delay register 5--1. At the same time, the data (HAI *Al) stored in the previous stage of the delay register 5-1 is shifted to the subsequent stage.

[3] Next, when signal A2 is input, the second tap M
In PY 3-2, the input data (A2) is multiplied by the output HA2 of the coefficient register 2-2, and the result (HA2
*A 2 ) is input to the adder 4-2, and is added to the data (IAI*A1) at the subsequent stage of the delay register 5-1 of the previous tap, and the result is (HAI *A 1 +HA2*A
2) is input to the previous stage of the second tap delay register 5-2. At the same time, the data (HBl*B 1 ) stored in the previous stage of the l-th tap delay register 5-1 is shifted to the subsequent stage.

[4] Next, when signal B2 is input, the second tag M
In PY 3-2, the input data (B2) is multiplied by the output HB2 of the coefficient register 2-2, and the result (HB2*
B2) is input to the adder 4-2, and is added with the data (HBff*B1) at the subsequent stage of the delay register 5-1 of the previous tap, and the result (HBI*B1+HB2*B2) is 2
It is input to the stage before the tap-th delay register 5-2. At the same time, the data stored in the previous stage of the delay register 5-2 (HAI * A 1 + HA2 * A 2 )
is shifted to the subsequent stage.

As the above operations are performed, the output terminals receive the signals Ai and B.
The filtered results of , are output alternately. That is, the calculation results are output in a multiplexed state.

(Effects of the Invention) As described above in detail, the present invention provides a circuit that performs FIR filter operation on each signal when two types of signals are multiplexed, and the data is processed at each tap h. 1 of the multiplier alternately by two coefficients in synchronization with the input.
Since we have provided a coefficient register that outputs to human input and a delay register that delays the output of the adder by two cycles and outputs it to the next tap adder, it is equivalent to the hardware of an FIR type filter for non-multiplexed signals. It is possible to realize circuits of this scale.

Note that by increasing the number of coefficients that can be stored in the coefficient register and the amount of delay in the delay register, the present invention can also be applied to a case where three or more signals are multiplexed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of a conventional FIR type filter, Fig. 3 is an explanatory diagram of a multiplexed signal, and Fig. 4 is a conventional FIR type of multiplexed signal. FIG. 2 is a block diagram of a filter. 1... Input register, 2-1 to 2-k-... Coefficient register, 3-1 to 3-k... Multiplier, 4-2 to 4-k
...Adder, 5-1 to 5-k...Delay register.

Claims (1)

[Claims] In an FIR type digital filter that performs FIR filter operation for each multiplexed signal on an input signal in which a plurality of signals are multiplexed, the same number of coefficient data as the multiplexed signals are stored. , a coefficient register that outputs corresponding coefficient data in synchronization with the signal; a multiplier that multiplies the coefficient data from the coefficient register by data of the input signal; and a delay register for the data from the multiplier and a previous tap. and a delay register for delaying the data from the adder by the same number of cycles as the number of multiplexed signals.