JPS60163459A - Solid-state image pickup element - Google Patents

Solid-state image pickup element

Info

Publication number
JPS60163459A
JPS60163459A JP59018312A JP1831284A JPS60163459A JP S60163459 A JPS60163459 A JP S60163459A JP 59018312 A JP59018312 A JP 59018312A JP 1831284 A JP1831284 A JP 1831284A JP S60163459 A JPS60163459 A JP S60163459A
Authority
JP
Japan
Prior art keywords
electrode
shift register
cod
ccd
horizontal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59018312A
Other languages
Japanese (ja)
Inventor
Norio Koike
小池 紀雄
Kayao Takemoto
一八男 竹本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59018312A priority Critical patent/JPS60163459A/en
Publication of JPS60163459A publication Critical patent/JPS60163459A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14831Area CCD imagers

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To improve the transfer efficiency of horizontal CCD's in a CCD type element by a method wherein the area of a CCD electrode at the part that receives signal charges from a vertical CCD shift register is made larger than that of another electrode. CONSTITUTION:When two receiving openings are provided, a the electrode dimensions L1'' and L2'' of two CCD electrodes 9''-1 and 9''-3 becomes larger than those of the other electrodes 9''-2, 9''-4-9''-6. If the dimensions L1'' and L3'' of the electrodes 9''-1 and 9''-3 corresponding to the two receiving openings are (P-3XIImin)/2, the dimensions of the L1'' and L3'' become the maximum in six CCD electrodes. The electrode capacitance of the receiving opening can be increased to approx. 1.5-2 times of that in the conventional element: it becomes possible to restrict charges for a potential increase VS in the case of their transfer to this electrode to 1/1.5-1/2, thus enabling those for an increase VY to be reduced; accordingly, inflow of charges to projections 11 is prevented.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体基板上に光電変換素子、および各素子
の光学情報を取出す電荷転送素子(ChargeCou
pled Devices 、以下CCDと略称する。
Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a photoelectric conversion element on a semiconductor substrate and a charge transfer element for extracting optical information of each element.
Pled Devices, hereinafter abbreviated as CCD.

)あるいはMOSシフトレジスタを集積化した固体撮像
素子に関するものである。
) or relates to a solid-state image sensor with an integrated MOS shift register.

〔発明の背景〕′ 固体撮像素子は、テレビジョン放送で使用されている撮
像用電子管と同等程度の解像力を備えることを必要とす
る。このためには、垂直方向に500個、水平方向に8
00〜1000個を配列した絵素(光電変換素子)マト
リックスと、それに相当する走査素子が必要である。し
たがって、固体撮像素子は、高集積化が可能なMO8大
規模回路技術を用いて作られ、半導体基板上に光電変換
素子および各素子の光学情報を取出す電荷転送素子(C
harge Coupled Devices、以下C
CDと略称する)あるいはMOSトランレジスタを集積
化して作られる。
[Background of the Invention]' A solid-state image sensor is required to have a resolving power equivalent to that of an imaging electron tube used in television broadcasting. For this we need 500 pieces vertically and 8 pieces horizontally.
A matrix of 00 to 1000 picture elements (photoelectric conversion elements) and a corresponding scanning element are required. Therefore, solid-state image sensors are manufactured using MO8 large-scale circuit technology that allows for high integration, and are equipped with a photoelectric conversion element and a charge transfer element (C) for extracting optical information from each element on a semiconductor substrate.
Harge Coupled Devices, hereafter C
(abbreviated as CD) or by integrating MOS transistor registers.

第1図は、従来の低雑音を特徴とするCCD型固体撮像
素子の基本構成図である。
FIG. 1 is a basic configuration diagram of a conventional CCD type solid-state image pickup device characterized by low noise.

1は光ダイオード等からなる光電変換素子、2および3
は光電変換素子群に蓄積された光信号電荷を出力回路4
に取り出すための垂直CCDシフトレジスタおよび水平
CCDシフトレジスタ、5゜6は各々垂直および水平の
CODシフトレジスタを駆動するクロックパルスを発生
するクロックパルス発生器である。ここでは、2相のク
ロックパルス発生器を示しているが、3相あるいは4相
のクロックを採用することもできる。7は、光ダイオー
ドに蓄積された電荷を垂直CODシフトレジスタ2に送
り込む転送ゲートである。この固体撮像素子は、このま
まの形態では白黒撮像素子となり、上部にカラー・フィ
ルタを積層すると各光ダイオードは色情報を備えること
になり、カラー撮像素子となる。
1 is a photoelectric conversion element consisting of a photodiode, etc.; 2 and 3;
outputs the optical signal charge accumulated in the photoelectric conversion element group 4
a vertical CCD shift register and a horizontal CCD shift register for taking out data; 5 and 6 are clock pulse generators that generate clock pulses to drive the vertical and horizontal COD shift registers, respectively. Although a two-phase clock pulse generator is shown here, a three-phase or four-phase clock may also be used. Reference numeral 7 denotes a transfer gate that sends the charges accumulated in the photodiodes to the vertical COD shift register 2. This solid-state image sensor becomes a monochrome image sensor in its current form, but if a color filter is laminated on top, each photodiode is provided with color information, making it a color image sensor.

固体撮像素子は、小型、軽量、メインテナンス・フリー
、低消費電力等の利点を有し、次期撮像デバイスとして
期待されているが、CCD型固体撮像素子においては、
電荷が1000段以上に及ぶCODシフトレジスタ内を
一方向に転送されるため充分な転送効率の確保が必要で
ある。しかし乍ら、現在のCCD型素子では構成および
構造上の問題により転送効率は実用上未だ十分な値に達
していない。特に垂直CODシフトレジスタに較べて3
桁速い転送速度が要求される水平CODシフトレジスタ
は転送効率が低く、混色、水平解像度子の劣化など画質
は著しく劣化する。
Solid-state imaging devices have advantages such as being small, lightweight, maintenance-free, and low power consumption, and are expected to be the next generation imaging device.
Since charges are transferred in one direction within the COD shift register, which has more than 1000 stages, it is necessary to ensure sufficient transfer efficiency. However, the transfer efficiency of current CCD type elements has not yet reached a value sufficient for practical use due to configuration and structural problems. Especially compared to vertical COD shift registers, 3
Horizontal COD shift registers, which require an order of magnitude higher transfer speed, have low transfer efficiency, resulting in significant deterioration in image quality such as color mixing and deterioration of horizontal resolution.

第2図は現在のCCD型素子において水平CCDシフト
レジスタの転送効率を悪くする要因となっている垂直C
ODシフトレジスタと水平CODシフ1−レジスタの結
合部分を示している。
Figure 2 shows the vertical CCD, which is a factor that deteriorates the transfer efficiency of horizontal CCD shift registers in current CCD type devices.
A combined portion of the OD shift register and the horizontal COD shift 1-register is shown.

点線で示した8の内側は電荷を転送し得る領域、すなわ
ちチャンネルである。9−1.9−2.9−3.9−4
は水平CODシフトレジスタを構成する電極、10−1
.10−2.10’ −1゜10’−2は垂直CODシ
フトレジスタを形成する最終段の電極を示している。垂
直CODシフトレジスタと水平CODシフトレジスタは
上方へ伸ばされた水平COD電極9−1により結合され
ている(この結合領域を通して垂直CODシフトレジス
タにより送られてきた電荷が水平CCDシフトレジスタ
内に送り込まれる)にの為、水平CODシフトレジスタ
の上側には突起した領域11が形成される。水平COD
シフトレジスタ内に送り込まれた電荷は水平CCD内に
矢印12の方向に向って高速で転送される(水平方向に
並ぶ絵素の数を11個とすると垂直CODシフトレジス
タの転送速度のn倍の速度が必要となる)。ここで、転
送電荷は領域13のみを流れるならば問題はないが、矢
印14で示されるように電荷の一部は突出領域11にも
迷い込む。一旦、領域11へ迷い込んだ電荷は領域毎に
所定の時間内で抜は出すことができず、各段毎に突起領
域11に相当数残ることになる。この結果、転送効率が
低くなり、水平方向の解像度が低化する。混色が発生す
る。
The area inside the dotted line 8 is a region where charges can be transferred, that is, a channel. 9-1.9-2.9-3.9-4
are electrodes forming a horizontal COD shift register, 10-1
.. 10-2.10'-1°10'-2 indicates the final stage electrode forming the vertical COD shift register. The vertical COD shift register and the horizontal COD shift register are coupled by a horizontal COD electrode 9-1 extending upward (through this coupling region, the charge sent by the vertical COD shift register is sent into the horizontal CCD shift register). ), a protruding region 11 is formed above the horizontal COD shift register. Horizontal COD
The charge sent into the shift register is transferred at high speed into the horizontal CCD in the direction of arrow 12 (assuming the number of pixels lined up in the horizontal direction is 11, the transfer rate is n times the transfer speed of the vertical COD shift register). speed is required). Here, there is no problem if the transferred charges flow only through the region 13, but some of the charges also stray into the protruding region 11 as shown by arrows 14. Once the charge has strayed into the region 11, it cannot be extracted within a predetermined time for each region, and a considerable number remains in the protrusion region 11 at each stage. As a result, the transfer efficiency decreases and the horizontal resolution decreases. Color mixing occurs.

等画質は著しく劣化する。The image quality deteriorates significantly.

突起領域11に迷い込む電荷をなくすために領域11に
不純物原子を打込む、あるいは、領域11のチャンネル
輻15を極端に狭くする、等によって領域11のポテン
シャルを上げることが考えられる。(但し、このポテン
シャル上昇分AVは、垂直CCDシフl−レジスタから
水平CODシフトレジスタに電荷を送り込む時の動作を
考慮すると、無限に大きくすることはできなくて限度が
ある)しかし乍ら、転送電荷量が多い場合には、前記有
限ポテンシャル上昇分AVを乗り込え、電荷はやはり領
域11に迷い込むことになる。これにより転送効率は従
来の場合より向上するが、未だ十分とはいえず、実用的
な画質を得るに到っていない。
It is conceivable to increase the potential of the region 11 by implanting impurity atoms into the region 11 to eliminate charges straying into the protrusion region 11, or by extremely narrowing the channel radius 15 of the region 11. (However, this potential increase AV cannot be increased infinitely and has a limit, considering the operation when sending charges from the vertical CCD shift register to the horizontal COD shift register.) However, the transfer If the amount of charge is large, the above-mentioned finite potential increase AV will be added, and the charge will still stray into the region 11. Although this improves the transfer efficiency compared to the conventional case, it is still not sufficient to achieve practical image quality.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上記の問題点を解消し、CCD型素子に
おける水平CODの転送効率を向上するための具体的手
段を提供することにある。
An object of the present invention is to provide specific means for solving the above problems and improving the horizontal COD transfer efficiency in a CCD type device.

〔発明の概要〕[Summary of the invention]

本発明は上記目的を達成するため、水平CODシフトレ
ジスタを構成するCOD電極のうち、垂直CODシフト
レジスタからの信号電荷を受け入れる部分のCOD電極
の面積を他の電極に較べて大きくすることにより(実際
には受け入れ部のCOD電極の転送方向の電極寸法を大
きくする)、電荷が該部分の電極下に送り込まれた際に
上昇するポテンシャルの持ち上りを減らすようにするも
のである。
In order to achieve the above object, the present invention increases the area of the COD electrode of the part that receives signal charges from the vertical COD shift register among the COD electrodes constituting the horizontal COD shift register, compared to other electrodes. (Actually, the size of the COD electrode in the receiving part in the transfer direction is increased) to reduce the rise in potential that occurs when charges are sent under the electrode in that part.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を実施例を用いて詳細に説明する。 Hereinafter, the present invention will be explained in detail using examples.

第3図は本発明の固体撮像素子を構成する水平CODシ
フトレジスタ領域の構成を示す図である。
FIG. 3 is a diagram showing the configuration of a horizontal COD shift register area constituting the solid-state imaging device of the present invention.

9’−1,9’−2,9’−3,9’ −4は水平CO
Dシフトレジスタ3を構成するCOD電極であり、例え
ば9′−1および9′−3を第1層目のPo1y−3i
で形成すると、9′−2および9′−4は第2層目のP
o1y −Siで形成される(勿論、9′−1,9’−
3を第2層目、9’−2,9’ −4を第1層目のPo
1y−5iで形成してもよい)。本発明の固体撮像素子
では信号電荷は受け入れ口に相当する水平CODシフト
レジスタの電極9′−1の寸法り、/ が他のCCD電
極9’ −2(L2’ )。
9'-1, 9'-2, 9'-3, 9'-4 are horizontal CO
These are the COD electrodes constituting the D shift register 3. For example, 9'-1 and 9'-3 are the COD electrodes that constitute the D shift register 3.
9'-2 and 9'-4 are the P of the second layer.
o1y -Si (of course, 9'-1, 9'-
3 is the second layer, 9'-2, 9'-4 is the first layer Po
1y-5i). In the solid-state image sensing device of the present invention, the signal charge has the dimensions of the electrode 9'-1 of the horizontal COD shift register corresponding to the receiving port, and / is the size of the other CCD electrode 9'-2 (L2').

9’ 3(L3 ’、)、9’ 4(L’ 4)に較べ
て大きくなっている。一方、第2図に示した従来素子の
場合においては電極9−1と9−3の寸法はLlyL3
は同じ値に設計され(L I=L3)m9−2と9−1
4の寸法L 2 t L 4も同一値になっており(L
2=L4)、受は入れ口の電極寸法L1が他に較べて大
きな値とはなっていない。
It is larger than 9' 3 (L3', ) and 9' 4 (L' 4). On the other hand, in the case of the conventional element shown in FIG. 2, the dimensions of electrodes 9-1 and 9-3 are LlyL3.
are designed to have the same value (L I = L3) m9-2 and 9-1
The dimension L 2 t L 4 of 4 is also the same value (L
2=L4), and the electrode dimension L1 at the inlet of the receiver is not a large value compared to the others.

(従来素子といえども電荷の一時蓄積に使用される一層
目の電極寸法LI+L3は電荷のシフトだけに使用され
る二層目の電極寸法L2tL4に対して大きくとられる
の普通であり、通常I、1=L 3 > L 2 = 
L 4なる関係を持つよう設計される。) ここで、本発明の固体撮像素子の水平CCDの電極寸法
L+ ’ + L2’ v L3’ p L12につい
て一番望ましい関係をめてみる。先ず、電荷のシフトだ
けに使用される2層目電極9−2.9−4の寸法L 2
 ’ HL 4 ’は製作加工技術で許される最小寸法
II minに選ぶ(L2 ’ =L4 ’ =I[m
1n)。続いて1層目電極のうち9−3の寸法をやはり
製作技術で許される最小寸法1 minに選ぶ(L3 
’ = I min 、また、一般にlm1nは11m
1nより大きくなる)。受は入れ口の1層目電極9−1
の寸法L1を絵素のくり返しピッチPがらし7′。
(Even in conventional devices, the first layer electrode size LI+L3 used for temporary charge accumulation is usually larger than the second layer electrode size L2tL4 used only for charge shifting, and usually I, 1=L3>L2=
It is designed to have the relationship L4. ) Here, we will examine the most desirable relationship regarding the electrode dimensions L+' + L2' v L3' p L12 of the horizontal CCD of the solid-state imaging device of the present invention. First, the dimension L 2 of the second layer electrode 9-2.9-4 used only for charge shifting.
'HL4' is selected as the minimum dimension II min allowed by manufacturing technology (L2' = L4' = I[m
1n). Next, the dimension of 9-3 of the first layer electrode is selected to be the minimum dimension of 1 min allowed by the manufacturing technology (L3
' = I min, and generally lm1n is 11m
(becomes larger than 1n). The receiver is the first layer electrode 9-1 at the entrance.
The dimension L1 is defined as the repetition pitch P of picture elements 7'.

L12.L12を差し引いた値としくL+’=PL2 
’ L3 ’ −L4 ’ ) 、寸法り、を4電極の
うち最大とする(L+ ’ >L3 ’ >L2 ’ 
=L4′ ) 前述のようし;受は入れ口の電極寸法を他電極に較べて
大きくした場合の効果について、第4図を用いて説明す
る。同図(a)は水平CODシフトレジスタの断面構造
を表わす図であり、16は例えばP型のSi基板、17
はチャンネルを埋込み型にするために設けた濃度の薄い
n型層(チャンネルを表面型する場合、木屑はなくてよ
い)、18は1層目と2層目のPo1y−5il!極の
間に電位差をつけるために注入した例えばP型の不純物
層、19は基板16とPo1y −Si電極9′−1〜
9′−4を絶縁分離するための絶縁!I!(一般にSi
O2膜が利用される)である。同図(b)は電荷転送時
における各電極下のポテンシャルを表わした図であり、
入射光量に相当する大小の信号電荷Qn。
L12. The value after subtracting L12 is L+'=PL2
'L3'-L4'), dimension, is the largest among the four electrodes (L+'>L3'>L2'
=L4') As described above, the effect of making the size of the electrode at the receiving inlet larger than that of other electrodes will be explained with reference to FIG. FIG. 3(a) is a diagram showing a cross-sectional structure of a horizontal COD shift register, where 16 is a P-type Si substrate, 17 is a
18 is the thinly concentrated n-type layer provided to make the channel a buried type (if the channel is a surface type, there is no need for wood chips), and 18 is the first and second layer Po1y-5il! For example, a P-type impurity layer 19 is implanted to create a potential difference between the electrodes, and the substrate 16 and the Po1y-Si electrode 9'-1~
Insulation for separating 9'-4! I! (Generally Si
(O2 membrane is used). Figure (b) is a diagram showing the potential under each electrode during charge transfer.
A signal charge Qn of magnitude corresponding to the amount of incident light.

Q n ++が18によって形成された電位差VB内に
次の転送まで一時貯蓄される。同図(C)は受け入れ部
に相当する電極9′−1の構成を示した図、同図(d)
は電極9′−1下のポテンシャルを示す図である。信号
電荷が電極9′−1下に転送されてくると9′−1下の
ポテンシャルは(d)に示したようにvsだけ上昇する
。この上昇分Vsは電極9′−1の備える容量Cと信号
電荷Qに依存し、V s = Q / C,で表わすこ
とができる。従来の固体撮像素子においては、大きな信
号電荷が転送されてきた場合、上昇分■8が予め前述の
イオン打ち込みあるいは狭チャンネル効果によって設け
ていたポテンシャル壁vAを越えると電荷は突起領域1
1にも流れ込むことになり、転送効率の低下を招く。こ
こで、通常vAは前記のVBより大きくなるように設計
される。もし■。をVaより小さく設計すると、突起領
域11への電荷の流れ込みは増々多くなる。一方、本発
明の固体撮像素子においては、電極9′−1の寸法の寸
法L 、 −1を大きくした分だけ容量Cが大きくなり
、その結果、ポテンシャル上昇分Vsを小さく抑えるこ
とができる。すなわち、上昇分C5をV^より小さく抑
えることが可能となり、突起部11への電荷の流人を防
ぐことができる。本発明の場合においても、勿論VAは
v6より大きくなるように設計されるものとする。本発
明のように受け入れ部の電極寸法を極力大きくとり、受
は入れ部以外の電極寸法を極力小さく抑えるようにする
と、寸法り、/ は従来素子における寸法り、の3倍程
度まで高めることができる。したがって1本発明の素子
における電極容量は従来素子の3倍程度まで大きくする
ことができ、上昇分Vsを従来素子の1/3程度に抑え
ることが可能となる。
Q n ++ is temporarily stored in the potential difference VB formed by 18 until the next transfer. Figure (C) is a diagram showing the configuration of electrode 9'-1 corresponding to the receiving part, Figure (d)
is a diagram showing the potential under electrode 9'-1. When the signal charge is transferred below the electrode 9'-1, the potential below the electrode 9'-1 rises by vs as shown in (d). This increase Vs depends on the capacitance C of the electrode 9'-1 and the signal charge Q, and can be expressed as Vs=Q/C. In a conventional solid-state image sensor, when a large signal charge is transferred, the charge is transferred to the protruding region 1 when the rising amount (8) exceeds the potential wall vA that was previously provided by the ion implantation or the narrow channel effect.
1 as well, leading to a decrease in transfer efficiency. Here, vA is usually designed to be larger than the above-mentioned VB. If ■. If it is designed to be smaller than Va, the amount of charge flowing into the protrusion region 11 increases. On the other hand, in the solid-state imaging device of the present invention, the capacitance C increases by an amount corresponding to the increase in the dimension L, -1 of the electrode 9'-1, and as a result, the potential increase Vs can be suppressed to a small value. That is, it is possible to suppress the increase C5 to be smaller than V^, and it is possible to prevent the charge from flowing to the protrusion 11. In the case of the present invention, it is of course assumed that VA is designed to be larger than v6. By making the electrode dimensions in the receiving part as large as possible as in the present invention and keeping the electrode dimensions outside the receiving part as small as possible, the dimension / can be increased to about three times the dimension in conventional elements. can. Therefore, the electrode capacitance in the element of the present invention can be increased to about three times that of the conventional element, and the increase Vs can be suppressed to about 1/3 of that of the conventional element.

第3図の実施例は水平CODシフトレジスタを2相のク
ロックパルスで駆動する場合を示している(例えば電極
9’−4,9’ −1に1相目のクロックを電極9’−
2,9’ −3に2相目のクロックを印加する)。第5
図に水平CODシフトレジスタを3相のクロックパルス
で駆動する場合の実施例を示す。9’−1,9’−2,
9’ −3゜9“−4,9’−5,9’ −6は水平C
ODシフトレジスタ3を構成するCCD電極であり、例
えば9’−1,9’−3,9’ −5を第1層目のPo
1y −Siで形成すること、9’−2,9“−4゜9
’−6は第2層目のPo1y −Siで形成される。本
実施における水平CCDは3相クロツクパルスで駆動す
るので、9”−6と9’ −1には例えば第1のクロッ
ク、9′−2と9“−3には第2のクロック+ 9y−
4と9#−5には第3のクロックを印加する(図示せず
)。また、本実施例においては、水平C0D1段当り2
個の電荷骨は入れ口を設ける場合を記載したが、第3図
の場合のように1個の受け入れ口を設ける場合であって
も構わない。この様に2個の受け入れ口を設ける場合、
2個のCCD電極9’−1,9’ −3の電極寸法Ll
’yL2#が他の電極9“−2,9“−4〜9′−6に
較べて大きくなる。具体的には電極のシフトだけに使用
される電極9’−2,9“−4゜9#−6の寸法L 2
 ’ t’L4 ’ F Ll3 ’は製作加工技術で
許される信心寸法If winに選び(L2”=L4 
’ =L6 ’ =IImin ) 、 9’ −5の
寸法L 、 71も製作加工技術で許される最小寸法1
 winに選ぶ(Ls ’ = lm1n )。2個の
受け入れ目に相当する電極9’−1,9′−3の寸法L
at1eL3′を(P−3XIImin ) /2とす
る。この結果、Ll“PL3′の寸法は6個のCCD電
極のうち最大となり、L’ I =L3 ’ >Ls 
’之L 2N== L 4# =L 6Ifなる関係が
成立することになる。
The embodiment shown in FIG. 3 shows a case where the horizontal COD shift register is driven by two-phase clock pulses (for example, the first phase clock is applied to electrodes 9'-4 and 9'-1).
Apply the second phase clock to 2,9'-3). Fifth
The figure shows an embodiment in which a horizontal COD shift register is driven by three-phase clock pulses. 9'-1, 9'-2,
9'-3°9"-4, 9'-5, 9'-6 is horizontal C
These are the CCD electrodes that constitute the OD shift register 3, and for example, 9'-1, 9'-3, and 9'-5 are the first layer Po.
1y-Si, 9'-2,9"-4°9
'-6 is formed of the second layer of Po1y-Si. Since the horizontal CCD in this embodiment is driven by three-phase clock pulses, for example, the first clock is applied to 9''-6 and 9'-1, and the second clock + 9y- is applied to 9'-2 and 9''-3.
A third clock is applied to 4 and 9#-5 (not shown). In addition, in this embodiment, each level of horizontal C0D has 2
Although the case where each charging bone is provided with an inlet has been described, a case where one inlet is provided as in the case of FIG. 3 is also applicable. When installing two reception ports like this,
Electrode dimensions Ll of two CCD electrodes 9'-1 and 9'-3
'yL2# is larger than the other electrodes 9''-2, 9''-4 to 9'-6. Specifically, the dimension L 2 of electrode 9'-2, 9"-4°9#-6 used only for electrode shifting
't'L4' F Ll3' is selected as the faith dimension If win that is allowed by the manufacturing technology (L2"=L4
'=L6'=IImin), 9'-5 dimension L, 71 is also the minimum dimension 1 allowed by manufacturing processing technology
Select win (Ls' = lm1n). Dimension L of electrodes 9'-1 and 9'-3 corresponding to two receiving eyes
Let at1eL3' be (P-3XIImin)/2. As a result, the dimension of Ll"PL3' is the largest among the six CCD electrodes, and L' I = L3 '> Ls
The following relationship holds true: 'no L 2N==L 4#=L 6If.

第6図(a)は第5図の水平CODシフトレジスタの断
面構造を示す図、同図(b)は電荷転送時における(a
)に示した電極下のポテンシャルを示す図、同図(c)
は受け入れ部に相当する電極9′−1あるいは9R−3
の構成を示す図、同図(d)は電極91−1あるいは9
#−3下のポテンシャルを示す図である。電極9′−1
および9′−3の寸法を極力大きくとるようにすると寸
法L1′。
FIG. 6(a) is a diagram showing the cross-sectional structure of the horizontal COD shift register in FIG. 5, and FIG. 6(b) is a diagram showing the (a)
) Figure showing the potential under the electrode shown in (c)
is the electrode 9'-1 or 9R-3 corresponding to the receiving part.
The figure (d) shows the configuration of the electrode 91-1 or 9.
It is a diagram showing the potential under #-3. Electrode 9'-1
If the dimensions 9'-3 and 9'-3 are made as large as possible, the dimension L1' is obtained.

L12は従来素子における寸法L1の1.5倍〜2倍程
度まで高めることができる。したがって、本実施例の場
合における受け入れ口の電極容量は従来素子の1.5〜
2倍程度まで大きくすることができ、本電極下に電荷が
転送されてきた場合のポテンシャル上昇分Vsを従来素
子の1/1.5〜1/2に抑えることが可能となる。こ
の結果。
L12 can be increased to about 1.5 to 2 times the dimension L1 in the conventional element. Therefore, in the case of this example, the electrode capacitance of the receiving port is 1.5 to 1.5 of the conventional element.
It can be increased to about twice the size, and the potential increase Vs when charges are transferred under the electrode can be suppressed to 1/1.5 to 1/2 of that of the conventional element. As a result.

上昇分VYはVAより小さく抑えることが可能となり、
突起部11への電荷の流入を防ぐことができる。
It is possible to keep the increase VY smaller than VA,
It is possible to prevent charges from flowing into the protrusion 11.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の固体撮像素子によれば、
水平CCDシフ1〜レジスタを構成するCCD電極のう
ち、垂直CCDシフトレジスタから信号電荷を受け入れ
る部分のCCD電極の面積を他の電極に較べて大きくす
ることにより、信号電荷の水平CCDCD内転送電荷が
該CCD電極下に転送された際ポテンシャルの持ち上り
分を減らすことが可能になる。この結果、水平CODに
おいて電荷を転送する際、突出領域へ流れ込む電荷をな
くすことができ、水平CODシフトレジスタの転送効率
を著しく向上することができる。また、将来線ls@が
増えると垂直CODシフトレジスタから電荷を水平GC
Dシフトレジスタに受け入れる突出領唯のチャンネル幅
等に与えられる寸法が著しく少なくなり、事実上電荷の
送り込みが出来なくなるという問題点の発生を考えるこ
とができるが、本発明においては受け入れ部分の水平C
OD電極の寸法を大きく取るため上記の問題の発生は防
止することができる。さらに1本発明は素子、設計時の
レイアウトパターンの変更によって実現することができ
、従来と全く同一の製作技術を用いて素子を作ることが
できるので素子の製作歩留りを低下させる心配もない。
As explained above, according to the solid-state image sensor of the present invention,
By making the area of the CCD electrode that receives the signal charge from the vertical CCD shift register larger than that of other electrodes among the CCD electrodes forming the horizontal CCD shift 1 register, the transfer charge of the signal charge within the horizontal CCDCD is increased. It becomes possible to reduce the rise in potential when transferred under the CCD electrode. As a result, when transferring charges in the horizontal COD, charges flowing into the protruding region can be eliminated, and the transfer efficiency of the horizontal COD shift register can be significantly improved. Also, when the future line ls@ increases, the charge is transferred from the vertical COD shift register to the horizontal GC.
It is conceivable that the dimension given to the channel width of the protruding region to be received in the D shift register will be significantly reduced, and a problem may arise in which it becomes virtually impossible to send charge, but in the present invention, the horizontal C of the receiving portion
Since the OD electrode is made large in size, the above problem can be prevented from occurring. Furthermore, the present invention can be realized by changing the layout pattern at the time of device design, and the device can be manufactured using exactly the same manufacturing technology as in the past, so there is no need to worry about lowering the manufacturing yield of the device.

なお、」二記の説明は固体撮像素子の中でも最も有力と
されているC、CD型撮像素子を対象にして行ってきた
が、もう1つの有力素子とされているCPD撮像素子(
Charge Priming Devices)にも
本発明を適用できることは自明である。CPD型素子は
MOSトランジスタのソースを光ダイオードとして利用
した絵素部、水平CODシフトレジスタ、および絵素部
の信号を水平CCDシフトレジスタに送り込む結合部の
3つの領域から構成されており、該水平CODシフトレ
ジスタを構成するC OD 11!極のうち電荷受は入
れ部に相当する電橋の面積を他に較べて大きくすればよ
い。CPD型素子に本発明を適用した場合の水平COD
シフトレジスタの構成、構造は実施例第3図〜第6図と
同じであり、図面は省略する。
Note that although the explanations in section 2 have been made with reference to C and CD type image sensors, which are considered to be the most promising among solid-state image sensors, CPD image sensors, which are considered to be another promising element (
It is obvious that the present invention can also be applied to Charge Priming Devices. A CPD type element consists of three regions: a picture element section that uses the source of a MOS transistor as a photodiode, a horizontal COD shift register, and a coupling section that sends the signal from the picture element section to the horizontal CCD shift register. COD 11 that constitutes the COD shift register! Among the poles, for the charge receiver, the area of the electric bridge corresponding to the insertion part may be made larger than the other parts. Horizontal COD when the present invention is applied to a CPD type device
The configuration and structure of the shift register are the same as those in the embodiments shown in FIGS. 3 to 6, and illustrations thereof are omitted.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の固体撮像素子の構成を示す図、第2図は
前記従来素子の構成およびその問題点を説明する図、第
3図は本発明の固体撮像素子の構成例を示す図、第4図
は第3図に示した本発明の素子の構造および動作を説明
する図、第5図は本発明の固体撮像素子の第3図とは別
の構成例を示す図、第6図は第5図に示した本発明の素
子の構造および動作を説明する図である。 1・・・光電変換素子、3・・・水平CCDシフトレジ
スタ、9’−1,9’−2,9’−3,9’ −4・・
・水平CCDシフトレジスタの電極、10−1゜10−
2.10’−1,10’ −2・・・垂直CCDシフト
レジスタの電極。 第1図 第 Z 図 第 3 口 ノ 扁 4 ロ ー\−16 児 5 図 第2図 〜16
FIG. 1 is a diagram showing the configuration of a conventional solid-state image sensor, FIG. 2 is a diagram explaining the configuration of the conventional device and its problems, and FIG. 3 is a diagram showing an example of the configuration of the solid-state image sensor of the present invention. 4 is a diagram illustrating the structure and operation of the device of the present invention shown in FIG. 3, FIG. 5 is a diagram showing an example of a configuration different from that shown in FIG. 3 of the solid-state image sensor of the present invention, and FIG. 5 is a diagram illustrating the structure and operation of the element of the present invention shown in FIG. 5. FIG. 1... Photoelectric conversion element, 3... Horizontal CCD shift register, 9'-1, 9'-2, 9'-3, 9'-4...
・Horizontal CCD shift register electrode, 10-1°10-
2.10'-1, 10'-2... Electrodes of vertical CCD shift register. Figure 1 Figure Z Figure 3 Mouth flat 4 Low\-16 Child 5 Figures 2 to 16

Claims (1)

【特許請求の範囲】[Claims] 同一半導体基板上に、光電変換素子群と、光信号の読出
し走査を行う垂直走査用のCCDシフトレジスタ群ある
いは単一のMOSシフ1−レジスタと、水平走査用のC
CDシフトレジスタ群とを集積化した固体撮像素子にお
いて、該水平CODシフトレジスタを構成するCOD電
極のうち該垂直CODシフトレジスタないしは該MOS
シフトレジスタにより送られてきた信号電荷を受け入れ
る部分に相当する該COD電極の電荷転送方向に相当す
る部分の電極寸法を同一工程で作られた同層の他の該C
OD電極の寸法より大きくしたことを特徴とする固体撮
像素子。
On the same semiconductor substrate, a group of photoelectric conversion elements, a group of CCD shift registers for vertical scanning or a single MOS shift register for reading and scanning optical signals, and a CCD shift register for horizontal scanning.
In a solid-state imaging device that integrates a group of CD shift registers, the vertical COD shift register or the MOS of the COD electrodes constituting the horizontal COD shift register
The electrode dimensions of the part of the COD electrode corresponding to the charge transfer direction, which corresponds to the part that receives the signal charges sent by the shift register, are set by other COD electrodes of the same layer made in the same process.
A solid-state imaging device characterized in that the size is larger than that of an OD electrode.
JP59018312A 1984-02-06 1984-02-06 Solid-state image pickup element Pending JPS60163459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59018312A JPS60163459A (en) 1984-02-06 1984-02-06 Solid-state image pickup element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59018312A JPS60163459A (en) 1984-02-06 1984-02-06 Solid-state image pickup element

Publications (1)

Publication Number Publication Date
JPS60163459A true JPS60163459A (en) 1985-08-26

Family

ID=11968089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59018312A Pending JPS60163459A (en) 1984-02-06 1984-02-06 Solid-state image pickup element

Country Status (1)

Country Link
JP (1) JPS60163459A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164807A (en) * 1988-03-15 1992-11-17 U.S. Philips Corp. Charge-coupled devices with locally widened electrodes

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164807A (en) * 1988-03-15 1992-11-17 U.S. Philips Corp. Charge-coupled devices with locally widened electrodes

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