JPS60163456A - Semiconductor ic - Google Patents

Abstract

PURPOSE:To minimize the unbalance of the titled circuit by changing all transistors into self-alignment by a method wherein the gate electrodes of the first and second transistors are formed in open loop form, and those of the third and fourth transistors in loop form. CONSTITUTION:Transistors Q6 and Q7 are formed in the region surrounded by the gate electrodes G4 and G5 of latch transistors Q4 and Q5. The gate electrodes G6 and G7 are formed in loop form; the regions surrounded by the respective gates G6 and G7 serve as the source regions of the transistors Q6 and Q7, and the outsides of the regions serve as the drain regions, also the source regions of the latch transistors Q4 and Q5. All the transistors can be prepared in self-alignment, and the source and drain regions of each transistor always comes into the same area even when a mask slides. The unbalance of capacitances C3 and C4 does not generate, and then a dynamic flip-flop circuit stable and high- sensitive can be realized.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit including a flip-flop circuit constituted by MrS transistors formed on a semiconductor substrate, and particularly to a semiconductor integrated circuit that realizes a high-performance dynamic flip-flop circuit. The present invention relates to improvements in pattern layout for the purpose of

[Prior art]

FIG. 1 shows this type of general dynamic flip-flop circuit, and in the figure, 110. 71 are complementary data lines, Q1 to Q7 are MO3I-Ranjisku,
C1 and C2 are data lines I10. Capacity of I10,
C3 and C4 are transistors Q4. Q6, transistor Q5. Capacitance such as diffusion capacitance and wiring capacitance between Q7,
φP is a precharge signal, φE is a data line I10. I1
The equalize signal of 0 and φS are flip-flop activation signals. Note that N1 to N4 and N2° indicate nodes in this circuit.

Next, the operation of this circuit will be explained with reference to the timing chart of FIG. First, data lines I10. Precharge I10 to the same VCC potential. Here, in the figure,
vp is below the above signal i.

This is the high level potential of φE, and is expressed by Vp=Vcc+Vth, where vth is the threshold potential of each transistor. Then this data line I10. I1
A small signal is applied to 0 from another circuit (not shown),
As a result, the potential level of the data line 10°Ilo changes. Here, when the data line F1 is set to the high level side (solid line in the figure) and the data line I10 is set to the low level side (broken line in the figure), the potential of each data line I10 is Vcc.
(precharge potential), data line I10 is Vcc-Δ■
becomes. Δ■ indicates both data lines I10. This is the potential difference between the signals applied to I10.

Next, the flip-flop activation signal φS is input to turn on the transistor Q6. When Q7 is turned on, this flip-flop is activated, and the signals on the data lines I10 and Ilo are amplified, and their respective potentials become Vcc and O.

Therefore, when constructing such a flip-flop circuit using Mis) transistors formed on a semiconductor substrate, it is necessary to take sufficient measures in the pattern layout to prevent imbalance in the circuit. There is.

FIG. 3 is a conventional example of a pattern layout when the dynamic flip-flop circuit of FIG. 1 is constructed of M■S transistors. The symbols in the figure are the same as those in FIG. 1. Also, A1-A12 are aluminum wiring, 03-G7 and G12 are polysilicon gates, F
1 indicates a field portion in which the N+ area is located, and 01 to 018 indicate contacts. In this pattern layout, each wiring capacitance, transistor size, etc. are almost symmetrical, and transistor Q3. Q4. In the portion constituting Q5, slight pattern deviations (deviations within 6% in the figure) are self-lined.

However, conventional pattern layouts do not sufficiently take into account the pattern deviations that occur during photolithography in each process step. In other words, the manufacturing process of MO3I-transistor is not all self-line, especially transistor Q4. Q6 and transistor Q5. Q7 cannot be self-lined in a plane, so if field pattern F and polysilicon gate pattern G are misaligned, transistors Q4. Capacitance C3 between Q6 and transistor Q5. There was a risk that the capacitance between Q7 and C4 would become unbalanced.

[Summary of the invention]

The present invention has been made in view of this point, and the first . The gate electrodes of the second transistors are respectively formed in a closed loop shape, and the gate electrodes of the first transistors are formed in a closed loop shape. a third transistor for activating the second transistor; The gate electrode of the fourth transistor is connected to the gate electrode of the first transistor. All the transistors constituting the MOS dynamic flip-flop circuit are made into a self-line by forming them in a loop shape in a region surrounded by each second gate electrode or outside the region so as to surround each gate electrode. It is possible,
It is an object of the present invention to provide a semiconductor integrated circuit that can minimize circuit imbalance caused by mask displacement during its manufacturing process.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Fourth
Like FIG. 3, this figure shows a pattern layout diagram of the circuit of FIG. 1, and in the figure, the same reference numerals as in FIGS. 1 and 3 indicate the same or corresponding parts.

In this embodiment, launch transistors Q4. Q5 polysilicon gate (gate electrode) G4. G5 is formed into a two-dimensional closed loop shape, and each gate G4. The region surrounded by G5 is the source region of the transistors Q4 and G5, and the outside region is the drain region. And each gate G4. G
5 is connected to the aluminum wiring A5.5 as data line lower 10 and Ilo by contacts C5 and C6, respectively. A4, each source region is connected to each other via contacts C12, C13 and aluminum wiring A6, and each drain region is connected to data line I10.
Aluminum wiring A4 as I10. Connected to A5.

Also, the launch transistor Q4. Gate electrode G of Q5
4. In the region surrounded by G5, the transistor Q4 is
．． Transistor Q6 for activating Q5. Q7 is formed. This transistor Q6. Each gate electrode G6°G7 of Q7 is formed in a loop shape, and each gate electrode G6. The area surrounded by G7 is the source area of the transistors Q6 and G7, and the area outside the area is the launch transistor Q4. This is the drain region which is also the source region of Q5. And each gate G6. ,G
7 is connected to the aluminum wiring A10 to which the activation signal φS is applied through contacts C17 and C18, each source region is connected to the power supply Vss (ground) via contacts C15 and C16 and the aluminum wiring A7, and each drain region is connected to the (contact) C12, C13 and aluminum wiring via 6.

In this embodiment, transistors Q6 . Q7 is a launch transistor Q4.
Gate electrode G4 of Q5. Since it is formed in the region surrounded by G5 and its gate electrode is formed into a loop, all transistors constituting the flip-flop can be created using self-aligned lines, and even if mask misalignment occurs, each transistor can be easily The source and drain regions have approximately the same area. Therefore, an unbalance between the capacitance C3 and the capacitance C4 does not occur, and a more stable and highly sensitive circuit can be realized.

Note that in the above embodiment, the transistor Q6. Q7 is a transistor Q4. Although formed in a region surrounded by the gate electrode of transistor Q5. Q7 is formed outside the above region, and each gate electrode thereof is connected to a transistor Q4. It may be formed in a loop shape so as to surround the gate electrode of Q5, and the same effect as in the above embodiment can be obtained.

Further, the present invention is not limited to the above-mentioned embodiments, but can be applied to all general MOS dynamic flip-flop circuits, and its practical value is enormous.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit according to the present invention,
The first step forming a flip-flop. The gate electrode of the second transistor is a closed loop type 4-channel transistor, and the gate electrode of the second transistor is a closed loop type 4-channel transistor. Second
The gate electrode of the third transistor and the fourth transistor are connected to the gate electrode of the fourth transistor.

Since the second transistor is formed in a loop shape within a region surrounded by each gate electrode of the second transistor or outside the above region so as to surround each gate electrode, even if the mask is misaligned during the manufacturing process, the first Name A and the source of the fourth transistor,
The area of the drain region is always the same, making it possible to realize a more stable and highly sensitive dynamic flip-flop circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a general MOS dynamic frimbflop circuit, Figure 2 is a timing chart of each signal to explain the operation of the circuit, and Figure 3 is a pattern layout of the circuit in Figure 1. FIG. 4, a diagram showing a conventional example, is a diagram showing a pattern layout of a semiconductor integrated circuit according to an embodiment of the present invention. G4. G5... 1st. Second transistor, G6°G
7...3rd. Fourth transistor, 03~GV. G12...Polysilicon gate (gate electrode). Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 2134 Figure 1 Continued 0 Inventor Hiroshi Miyamoto 4-cho Mizuhara Eye Research Institute, Itami City 0 Inventor Tsuyoshi Morooka - 4-cho Mizuhara Eye Research Institute, Itami City Inside the office

Claims (1)

[Claims] (11 Mis formed on a semiconductor substrate) In a semiconductor integrated circuit including a flip-flop circuit constituted by transistors, each gate electrode is formed in a two-dimensional closed loop shape, and a first
．． a second transistor; The first transistor has a loop-shaped gate electrode formed in a region surrounded by the closed-loop gate electrode of the second transistor or so as to surround the loop-shaped gate electrode. 3. activates the second transistor; A semiconductor integrated circuit comprising: a fourth transistor.