JPS6016074A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To attain elimination of high light afterimage and blooming by impressing a voltage having different magnitude depending on the 1st period and the 2nd period to a transparent electrode during the presence of a high frequency transfer pulse in a laminated solid-state image pickup device. CONSTITUTION:The laminated type solid-stage image pickup element providing a transparent electrode 53 onto a photoelectric converting film 35 is used and a voltage phiITO having a different magnitude depending on the 1st period and the 2nd period is impressed to a transparent electrode terminal 43 corresponding to the period where high frequency transfer pulses S1, S2 exist in the vertical blanking V, BLK. Thus, high light afterimage and blooming are eliminated completely even if a voltage within a range of a dielectric strength of the image pickup element is used to a strong light in this way.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a solid-state imaging device, in particular a photoelectric conversion film in an LSI
This relates to a so-called stacked solid-state imaging device in which layers are stacked on a scanning surface.Conventional structure and its problemsComposed of a combination of a photosensitive element such as a photodiode and a charge transfer element such as a MOS two-place transistor or COD. Solid-state image sensor (hereinafter referred to as Si single type)
A stacked solid-state image sensor (hereinafter referred to as a stacked type) has been proposed in which a photoconductive film is three-dimensionally stacked on the scanning plane with the main purpose of improving sensitivity. ing. In addition to the major problem of so-called highlight afterimage, in which afterimage components are emphasized when the subject light is strong, this laminated type also has problems such as the occurrence of a pluming phenomenon, which will be described later. The causes of these problems and countermeasures that have been proposed so far will be described below.

A well-known Si single type is interline WC.
CD, frame transfer type CCD.

MOS x-y address type or MO8i in the imaging surface area
There is a CPD type that uses COD for the horizontal line. Here, for clarity of explanation, a case will be described in which an interline type COD among the above-mentioned types is used as a stacked type scanning surface.

FIG. 1 shows a plan view of an interline type COD. 11
12 is a region corresponding to the imaging surface, 12 is a Si single element 3 : : This is a source end electrode that sometimes functions as a photodiode, and the signal charge obtained at this electrode is transferred to a vertical line 14 via a gate 13, as shown in the figure. The signal charge is further transferred in the direction of arrow 15 and read into the horizontal output line 16, and the signal charge is further transferred in the direction of arrow 17 and output ○ut.
It is well known that .

In the case of a stacked type, the photodiode does not have a photoconductive conversion function, and this function is performed by a photoelectric conversion film newly formed on this area via a metal electrode,
The photodiode only functions as a source end electrode of the gate electrode. By providing the photoelectric conversion film three-dimensionally on the source end electrode in this manner, a photoelectric conversion region corresponding to one picture element, which is larger in plan than the area of the source end electrode indicated by diagonal lines in the figure, can be obtained. For clarity of explanation, such a photoelectric conversion area corresponding to one pixel when laminated is shown as a dotted line 18 in the figure.

As can be seen from this figure, in the case of the stacked type, the area that contributes to photoelectric conversion is larger than that of a single Si element.
16074(2) Although the width is greatly increased and the sensitivity is greatly improved, the amount of saturation charge also becomes greatly increased, resulting in the following drawbacks.

That is, it is well known that the signal charge obtained from the photoelectric conversion film corresponding to one picture element is transferred to each one bit of the COD when the vertical line 14 is configured by CCP. If this signal charge is larger than the maximum charge amount of one pit of the CCD, that is, the maximum transferable charge amount QCCD, it becomes impossible to transfer all the signal charge amount to the CCD side every field (or every frame), that is, surplus charge remains at the source end. It takes several fields (one field is 16.6 m11) to completely transfer the image, and an afterimage corresponding to this time is generated.

As is well known, the scanning plane of interline type COD is 2:1.
The pixel signals obtained from the photoelectric conversion film during the vertical blanking period are used to form a vertical line once every two fields during interlacing and once every one field when non-interlaced. Load into COD. Now, the electric charge Qs of the pixel signal generated by light irradiation is the maximum transferable electric charge QCC mentioned above.
If it is 5 times as large as D, an afterimage will occur for a time period of 10 fields (approximately 166 m5) during interlace operation. The amount of charge Qs increases as the brightness of an object that shines strongly in the subject increases, and therefore the time and amount of afterimages increase, resulting in the phenomenon of so-called highlight afterimages.

In addition to this highlight afterimage, the amount of signal charge is QCC.
When it is a dog from D, the data cannot be transmitted through the CCD and overflows, resulting in a false signal shown as a diagonal line below a high brightness object 21 such as a light bulb in a part of the playback screen 20 shown in FIG. There was a problem that a pluming component 22 was generated.

In order to alleviate such highlight afterimages and blooming problems, a method that has been proposed in the past is to provide six high-frequency transfer pulses during the vertical blanking period in the vertical transfer lock pulse train. The method of sweeping out the excess charge is
For example, Japanese Patent Application No. 55-43951 (Japanese Unexamined Patent Publication No. 56-14
No. 0773). Although this method alleviates the above-mentioned problem, highlight afterimages and pluming still occur when the amount of light increases, for example, to several tens of times the saturated amount of light possessed by the image sensor. The reason for this is that the more the amount of light increases, the more the excess charge increases.
The problem lies in not being able to sweep it all away. The reason why the signal charge is not completely swept out is that when only the signal charge equivalent to the excess charge at the source end is discarded to the CCD side via the gate, the amount discarded is the voltage applied to the gate, that is, the amount that the level of the empty layer directly under the gate is pushed down. Depends on.

In order to increase the amount thrown away, the gate voltage must be increased, which would require a voltage that far exceeds the withstand voltage of the LSI, resulting in destruction of the image sensor.

OBJECTS OF THE INVENTION It is an object of the present invention to easily configure a high-7 light afterimage and remove blooming in strong light, and to obtain high-quality images. Furthermore, the present invention eliminates the above-mentioned drawbacks, that is, it is possible to completely eliminate highlight afterimages and blooming even when using a voltage within the range that protects the withstand voltage of the image sensor against intense light. With the goal.

Structure of the Invention The present invention differs from the conventional method of sweeping away excess charge;
Using the advantage of a stacked solid-state image sensor in which a transparent electrode is provided on a photoelectric conversion film, a special pulse, that is, the first Voltages of different magnitudes are applied during the period and the second period.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 is a timing chart showing the main parts of the drive voltage used in the device of the present invention, and FIG. 4 is a timing chart showing the operating state of the solid-state image sensor at each timing. φ■2 is a two-phase drive type C that forms a vertical line.
CD transfer lock, period t. is an optical signal accumulation period, and the accumulated signal charge is read into the CCD side by a pixel reading pulse vcH, and two-phase transfer pulses with different phases 1. ■Transferred vertically by 2.

S present during the vertical blanking period V, BLK
4. As will be described later, the pulse train S2 is a high frequency transfer pulse for discarding excess charge, and is also a pulse having different phases.

φITO indicates a pulse applied to a transparent electrode on a photoelectric conversion film, which is the basis of the present invention.

FIG. 4 schematically shows an example of a plan view of a layered type region corresponding to one picture element used in the present invention.

Reference numeral 31 denotes a source end electrode region 32 in which optical signal charges are accumulated, which is a COD transfer channel region, and region 32 includes a storage region 33 indicated by diagonal lines and a transfer region 3 indicated by dots.
It is configured as one bit of C0D from two areas of 4. A region 36 indicated by a dotted line is connected to the photoconductive film region 9 corresponding to one pixel, which is provided in electrical contact with the upper part of the north end electrode 31. A region 036 indicates a region 36 that connects the signal charge of the source end electrode to the COD. This is the gate area for reading into the storage area 33, and the gate electrode on this area is also used as the transfer electrode of the COD. A cross-sectional view taken along the line X-X/ in the figure is schematically shown for each period t of the clock pulse.

What is shown in FIG. 5 corresponds to t6. In addition, in FIG. 4, the transfer electrode and the reading gate electrode in the COD channel region are omitted.

Below - Before detailed description of this figure, a description of the common parts of each section along the line x-x' from period 10 to 16 o'clock will be given for period t. This will be explained using time as an example.

The electrode 41 is a COD transfer electrode to which a P-type St substrate 42 is applied, and a read gate electrode that is shared with these.
It is led to clock terminal V.

Area C (l-j: CCD (vertical line) area (
4), the signal charge in the n+ region 31, which is the source end electrode, is read into the COD region C through the gate channel region q directly under the n- impurity region 36. There is. A charge conversion film 36 is laminated on the end electrode n region 31, and a transparent electrode ITO terminal 43 is stacked on the end electrode n region 31 in order to have a photoelectric conversion function by applying a reverse bias voltage to this film 36. Signal charges obtained in the film 36 are read into the n+ region 31 in response to the intensity of light.

In the P-type Si 2 substrate 42 in the figure, a portion indicated by a dotted line 44 schematically shows the depletion layer level.

Hereinafter, the states of the signal charge, surplus charge, depletion layer level, etc. in each period to-t6 will be sequentially explained.

In addition, in the depletion layer in each figure, the hatched area is the excess charge 45, and the crosshatched area is the QCCD described above (the amount of charge smaller than the amount that can be accumulated at the depth d of the bucket in the figure, that is, the correct amount). It is assumed that a normal charge 46 is reproduced as an image.

Clock pulse v1. Although the depletion layer level 44 varies according to v2, the depletion layer level is shown in one steady state for clarity of explanation.

1) 18:00 (K91 Kinuta) Light enters the photoelectric conversion film 36, and signal charges corresponding to the amount of light are accumulated in this film during this period, and are distributed in the region 31 in accordance with the amount of signal charges. Provides potential fluctuations. Now, if this film 36 is a heterojunction film such as Zn5e-ZnxCdl-xTo, known as 11-Bicon, the signal charge obtained is an electron. Therefore, the signal charge obtained is an electron. When the light is intense, excess charges 45 (shaded area in the figure) are stored in the depletion layer directly under the n-region 31 in addition to normal charges 46 (cross hatched area) as shown in the figure.

1i) At the time of tI (jaw Gkt'hb) At this time, when the potential φITO of the terminal 43 on the ITo side is set to a low voltage vL as shown in FIG. 3, the level of the depletion layer directly under the n+ region 31 becomes shallow. Become. This is because the photoelectric conversion film 35 has capacitance, so the ITO terminal 43 is capacitively coupled to the n+ region 31, and the IT
This is because when the O potential φITO decreases, the potential of the n+ region 31 also decreases.

On the other hand, the high-frequency transfer pulse trains S1, . Due to S2, the depletion layer level immediately below the n- region 36 increases from the potential level ψ2 shown at 10 o'clock to ψ4 shown at tl, and the n+ region 31
The potential level immediately below (the potential when the signal charge is zero) is t
. At the time, it was ψ1, but at the time of tl, the ITO voltage is lowered to vL (for example, 8V) as described in -, so the potential level immediately below the region 31 is also reduced to ψ3.

A method for discarding excess charge that has been proposed in the past.”
; Then, the bottom of the bucket in which signal charges are accumulated (the potential level ψ1 directly below the n+ region 31 described above) is deep t.
Therefore, only the surplus charge q is transferred to the CCD side by the above-mentioned high frequency transfer pulse S1. To use S2 as a gate pulse and discard it, set the ψ2 level to ψ6 as shown in the 10 o'clock diagram.
The level must be deepened. In order to deepen the ψ2 level in this way, the gate voltage needs to be about 30V or more considering the normal LSI design level, and as a result, the withstand voltage of the element is far exceeded (usually 30V or more in LSI).
- Maximum voltage is about 20V), which may cause element destruction.

However, in the present invention, even if the potential level directly under the gate is shallow as shown by ψ4, for example, by lowering the voltage on the ITO side to vL, the bottom of the bucket in which the signal charges are accumulated is set to ψ3(t).

By making it as shallow as ψ1), only the excess charge can be easily transferred to the CCD side, as shown by the arrow in the figure.

1ii) t2 time 0 loss 1 sword C) tl As shown by the arrow marked at time, the state is shown after the surplus charge is transferred to the CCD side. The time required to complete the transition is mainly determined by the conductance qm in the gate region q. Usually, several n8 to several hundred ns is sufficient. That is, t2 may be a time at most after this amount of time has elapsed since time tl.

As can be seen from the figure, the signal charges 46 remaining in the depletion layer region directly below the n+ region 31 (hereinafter referred to as the picture element side) remain as normal charges less than the QCCD charge amount. The surplus charge 46 transferred to the depletion layer region on the transfer CCD side is transferred to the above-mentioned QC shown by dotted areas a in the figure.
The amount is the sum of the amount equivalent to the CD charge amount and the amount of charge shown in the shaded area that causes the pluming described above. That is, the sum of a and b corresponds to the above-mentioned surplus charge 46.

Since this surplus charge 46 is swept away to the outside of the element by a mechanism to be described later during the vertical blanking period, blooming and highlight afterimages do not appear on the playback screen.

Song) 13:00 (1st d) At this time, by changing the ITO voltage φrroff: high voltage vH to, for example, 20 V, the bottom of the bucket of the picture element 31 becomes deeper again, and the normal charge 46 as the signal charge becomes Even if the COD transfer lock is applied, it is maintained without leaking to the transfer CCD side. Further, when the ITO voltage is increased in this way, the bias voltage applied to the photoelectric conversion film 35 is reduced to about 5V, and the amount of charge generated in the photoelectric conversion film 35 during this high period can be suppressed. That is, even if the amount of light is strong, the amount of surplus charge generated during this high period does not increase beyond a certain level.

After time t3, both of the above-mentioned surplus charges a and b are transferred to two consecutive high-frequency transfer pulses S1. S
2, the signal is transferred through the CCD constituting the vertical line, and is discharged to the outside of the device via the horizontal transfer line.

1■) Time t4 (calculation) At this time, as mentioned above, all the excess charge is discharged to the outside of the element, the amount of charge existing in the COD region becomes zero, and normal signal charge 46 is generated only on the picture element side. remains.

V) 15:00 (No. S-Ro) At the moment when the pixel reading pulse ■cH is applied to the clock terminal ■, the signal charge 46 is transferred from the pixel side to the CC as shown by the arrow.
This shows what is about to be read into the D side.

vi) t6 o'clock (budding) From 15 o'clock, for a certain period of time (several tens of ns to several hundred nanoseconds as mentioned above)
After s), the signal charges 4646 indicate a state where they have all been read from the picture element side to the CCD side.

At subsequent times, the transfer pulse v1. ■2 (usually T
Frequency 15,75k corresponding to one horizontal scanning period 1H of V
It is well known that signal charges, that is, normal charges, are transferred in vertical lines by tlz), are sequentially taken out to the outside of the device, and become video signals.

With such a simple driving method, highlight afterimage blooming can be removed even in the case of intense light, and it is possible to obtain good image quality. In addition, in the case of an image sensor in which a Newbun film is laminated on an interline type COD such as a double series, the conventional sweeping method has a high suppression ratio (expressed as a multiple of the saturated light amount) of highlight afterimages and blooming.
was about 10 to 20 times at most, but with the present invention
11, set φITO to ■L, and set “3 f9'ITOe
``H (!: Both sults show the specific cross-sectional structure of the drive voltage within the lateral pressure range of about 20V or less, 50 is the gate acid 17 film, 51 is the thick S 102 film, and 52 is the region 31 and a metal electrode interposed between the photoelectric conversion film 35 and a transparent electrode 53 on the film 35.

Effects of the Invention As described above, the present invention can easily remove highlight afterimages and pluming even against intense light at a voltage within the withstand voltage range of the solid-state imaging device, and provides a high-performance solid-state imaging device. This will greatly contribute to the realization of the device.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of a solid-state imaging device, FIG. 2 is a structural diagram, and FIG. 6 is a cross-sectional view of the main structure of the device. 31... Electrode region, 32... Transfer channel region, 35... Photoelectric conversion film, 41...
...Transfer and read gate electrode, 42...
Si substrate, 43... Transparent 18 base: Cut electrode terminal, 53... Transparent electrode, Sl, S2...
- Group/sho frequency transfer pulse, φI To"'"'Pulse applied to the transparent electrode. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 2 f Figure 3 t Figure 4 X' Figure 5 Figure 6 Figure 43 (IT

Claims (1)

[Claims] A photoelectric conversion film and this - F is provided with a transparent electrode, and voltages of different magnitudes are applied to the transparent electrode in a first period and a second period corresponding to the period in which the high frequency transfer pulse is present. Imaging device.