JPS60160656A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS60160656A
JPS60160656A JP1560684A JP1560684A JPS60160656A JP S60160656 A JPS60160656 A JP S60160656A JP 1560684 A JP1560684 A JP 1560684A JP 1560684 A JP1560684 A JP 1560684A JP S60160656 A JPS60160656 A JP S60160656A
Authority
JP
Japan
Prior art keywords
nicr
substrate
film
thin
electrode film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1560684A
Other languages
Japanese (ja)
Inventor
Shinji Yoshida
真治 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1560684A priority Critical patent/JPS60160656A/en
Publication of JPS60160656A publication Critical patent/JPS60160656A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To reduce the solder intrusion of an electrode film by heating a substrate at a specific temperature or higher and forming the electrode film consisting of NiCr-Au on the surface of the substrate through a sputtering method. CONSTITUTION:NiCr atoms and Au atoms collide with a residual gas (mainly, steam) in a process of sputtering. Consequently, weakening adhesion between a thin-film 3 consisting of NiCr and a thin-film 4 composed of Au is strengthened in such a manner that the thin-film 3 consisting of NiCr and the thin-film 4 composed of Au mutually diffuse by heating the temperature of a substrate at 250 deg.C or higher and a diffusion layer 6 for NiCr and Au is formed. Accordingly, the solder intrusion section of an electrode film consisting of NiCr-Au formed through a sputtering method can be reduced to the same extent as an electrode film shaped through a vacuum evaporation method.

Description

【発明の詳細な説明】 (al 発明の技術分野 本発明は混成集積回路の製造方法に係り、特にスパッタ
法により基板表面にNiCr−^Uよりなる電極膜を生
成する、混成集積回路用基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a method for manufacturing a hybrid integrated circuit, and in particular to a method for manufacturing a hybrid integrated circuit substrate, in which an electrode film made of NiCr-^U is formed on the surface of the substrate by sputtering. Regarding the manufacturing method.

(b) 技術の背景 抵抗体としてタンタル(T112 N)の薄膜を用いた
混成集積回路の製造において、一般に配線パターンの表
面に半田ディップ法等1田を付着せしめ、抵抗体の電極
や配線導体部を形成している。
(b) Background of the technology In manufacturing hybrid integrated circuits using thin films of tantalum (T112N) as resistors, solder is generally attached to the surface of the wiring pattern using a solder dip method, and the electrodes of the resistor and the wiring conductor are bonded to the surface of the wiring pattern. is formed.

かかる混成集積回路は配線パターンの表面に一様に半田
が付着していることが要求され、部分的に半田が付着し
ない個所(以下半田クワレ部と称する)があってはなら
ない。
Such a hybrid integrated circuit is required to have solder uniformly adhered to the surface of the wiring pattern, and there must be no portions where solder does not adhere (hereinafter referred to as solder cracks).

一方かかる配線パターン(以下電極膜と称する)は一般
にNiCr−Auの薄膜よりなり、従来は真空蒸着法に
よって生成されていた。しかし真空蒸着法によって生成
された電極膜は均一性に欠は歩留りが悪いという問題が
あり、スパッタ装置の高速化に伴って最近は均一な電極
膜の得られるスパッタ法による生成に置き変えられてい
る。
On the other hand, such a wiring pattern (hereinafter referred to as an electrode film) is generally made of a NiCr-Au thin film, and has conventionally been produced by a vacuum evaporation method. However, the electrode film produced by vacuum evaporation method lacks uniformity and has a problem of poor yield, and as sputtering equipment becomes faster, it has recently been replaced by sputtering method, which can produce a uniform electrode film. There is.

電極膜の生成を真空蒸着法からスパッタ法に置き変える
ことで均一な電極膜が得られ歩留りは向上したが、スパ
ッタ法により生成された電極膜は真空蒸着法によって生
成された電極膜に比べ、半田クワレ部が増加する傾向に
あるという新たな問題が発生した。そこで半田クワレ部
が真空蒸着法によって生成された電極膜と同等まで低減
でき、且つ均一な電極膜が得られるスパック条イ9の確
立が望まれている。
By replacing the vacuum evaporation method with the sputtering method to generate the electrode film, a uniform electrode film was obtained and the yield was improved; A new problem has arisen in that solder cracks tend to increase. Therefore, it is desired to establish a spackle strip 9 in which the solder cracks can be reduced to the same level as an electrode film produced by vacuum evaporation, and a uniform electrode film can be obtained.

TCI 従来技術と問題点 第1図は抵抗体としてタンタル(Ta2N)の薄膜を用
いた混成集積回路の断面を表す図で、第1図(alは正
常な混成集積回路、第1図181は半田クワレ部が生じ
た混成集積回路である。
TCI Prior Art and Problems Figure 1 is a cross-sectional view of a hybrid integrated circuit using a thin film of tantalum (Ta2N) as a resistor. This is a hybrid integrated circuit with cracked parts.

セラミック等よりなる基板1の表面にTa2Nよりなる
抵抗体2が生成されており、抵抗体2の表面両端にはN
iCrの薄膜3および^Uの薄膜4よりなる電極膜が生
成されている。かかる基板に半田層5を付着せしめると
Auの薄IJ4は半田層5に拡散し、NiCrの薄11
1!3の上に直接半田N5が付着することになる。そこ
でNiCrの薄McJ43に対する11uの薄膜4の密
着力が強いと、Auの薄11!1!4を介して第1図1
81の如<NiCrの薄膜3と半田層5が密着するが、
NiCrの薄膜3に対する^Uの薄膜4の密着力が弱い
とNiCrの薄膜3と半田1層5が密着せず、第1図1
b+に示した如く半田クワレ部が生じる。
A resistor 2 made of Ta2N is formed on the surface of a substrate 1 made of ceramic or the like, and N is formed on both ends of the surface of the resistor 2.
An electrode film consisting of a thin film 3 of iCr and a thin film 4 of ^U has been produced. When the solder layer 5 is attached to such a substrate, the Au thin IJ4 diffuses into the solder layer 5, and the NiCr thin IJ4 diffuses into the solder layer 5.
Solder N5 will be directly attached on top of 1!3. Therefore, if the adhesion of the 11u thin film 4 to the NiCr thin McJ43 is strong, the thin film 4 of Fig. 1
As shown in 81, the NiCr thin film 3 and the solder layer 5 are in close contact with each other,
If the adhesion of the ^U thin film 4 to the NiCr thin film 3 is weak, the NiCr thin film 3 and the solder 1 layer 5 will not be in close contact with each other, and as shown in FIG.
As shown in b+, solder cracks occur.

真空蒸着法による電極膜の生成は1O−6Torrとい
う高真空の中で行われるために、NiCr原子およびA
u原子が残留ガスに衝突する確率は低いが、スパッタ法
による電極膜の生成は1O−3Torrという比較的低
い真空中で行われるために、NiCr原子およびAu原
子が残留ガス(主として水蒸気)に1!1突する確率が
高く、基板上に生成されるNiCrの薄膜3と^Uの薄
膜4との密着力が弱くなり半田クヮレ部が生じやすくな
る。
Since electrode films are produced by vacuum evaporation in a high vacuum of 1O-6 Torr, NiCr atoms and A
Although the probability of U atoms colliding with residual gas is low, since electrode films are produced by sputtering in a relatively low vacuum of 1O-3 Torr, NiCr atoms and Au atoms collide with residual gas (mainly water vapor). !1 The probability of collision is high, and the adhesion between the NiCr thin film 3 and the ^U thin film 4 formed on the substrate becomes weak, and solder cracks are likely to occur.

fdl 発明の目的 本発明の目的はスパック法により生成したNlCr−A
uよりなる電8ilIy!の半田クヮレ部を、真空蒸着
法によって生成された電極膜と同等まで低減させる、混
成集積回路用基板の製造方法を提供することにある。
fdl Object of the Invention The object of the present invention is to obtain NlCr-A produced by the spacking method.
8ilIy from u! An object of the present invention is to provide a method for manufacturing a substrate for a hybrid integrated circuit, which reduces solder cracks to the same level as an electrode film produced by a vacuum evaporation method.

tel 発明の構成 そしてこの目的は半田付性を改善するために基板の温度
を250℃以上に加熱し、スパック法により基板表面に
NiCr−Auよりなる電極膜を生成することで達成し
ている。
tel Structure of the Invention This object is achieved by heating the substrate to a temperature of 250 DEG C. or higher to improve solderability, and forming an electrode film of NiCr--Au on the surface of the substrate using the spacing method.

if) 発明の実施例 以下添付図により本発明の詳細な説明する。if) Examples of the invention The present invention will be described in detail below with reference to the accompanying drawings.

第2図は基板を加工する際の基板温度と半田クヮレによ
る不良率の関係を示す図、第3図は本発明の詳細な説明
するための図である。、 第2図によれば真空蒸着法によって生成された電極膜の
半田クワレによる不良率は、基板温度が室温近傍では約
50%と高いが150℃近傍まで加熱すると皆無にまで
低下することがわかる。それに対しスパック法により生
成された電極膜の半田クワレによる不良率は、基板温度
が室温近傍では約90%と極め°C高く、真空蒸着法に
よって生成された電極膜の半田クワレによる不良率が皆
無になる150℃近傍においても約30%の不良が発生
ずる。
FIG. 2 is a diagram showing the relationship between the substrate temperature and defective rate due to solder cracking when processing the substrate, and FIG. 3 is a diagram for explaining the present invention in detail. According to Figure 2, the failure rate due to solder cracks in electrode films produced by vacuum evaporation is as high as about 50% when the substrate temperature is around room temperature, but it drops to zero when the substrate temperature is heated to around 150°C. . On the other hand, the failure rate due to solder cracks in electrode films produced by the sppack method is extremely high at approximately 90% when the substrate temperature is near room temperature, and the failure rate due to solder cracks in electrode films produced by the vacuum evaporation method is extremely high. Approximately 30% of defects occur even at temperatures near 150°C.

これを皆無にするためには基板温度を250℃以上に加
熱する必要がある。
In order to completely eliminate this, it is necessary to heat the substrate temperature to 250° C. or higher.

これはスパックの過程でNiCr原子およびAu原子が
残留ガス(主として水蒸気)に衝突することによって、
弱くなっていたNiCrの薄l!l13と^Uの薄膜4
との密着力が、基板温度を250℃以上に加熱すること
で第3図に示す如(NkCrの薄膜3とAuの薄膜4が
相互に拡散し、NiCrと^Uの拡散M6を群成するこ
とによって強くなるためである。
This is caused by NiCr atoms and Au atoms colliding with residual gas (mainly water vapor) during the spuck process.
NiCr thin l that had become weak! Thin film 4 of l13 and ^U
When the substrate temperature is heated to 250°C or higher, the adhesion between the NkCr thin film 3 and the Au thin film 4 diffuses into each other, forming a group of NiCr and ^U diffused M6, as shown in Fig. 3. This is because it makes you stronger.

(gl 発明の効果 以上述べたように本発明によれば、スパック法により生
成したNiCr−Auよりなる電極膜の半田クワレ部を
、真空蒸着法によって生成された電極膜と同等まで低減
させる、混成集積回路用基板の製造方法を提供すること
ができる。
(gl) Effects of the Invention As described above, according to the present invention, the solder cracks of the NiCr-Au electrode film produced by the spuck method are reduced to the same level as those of the electrode film produced by the vacuum evaporation method. A method for manufacturing an integrated circuit substrate can be provided.

【図面の簡単な説明】 第1図は抵抗体としてタンクル(Ta2N)の薄膜を用
いた混成集積回路の断面を表す図で、第1図181は正
常な混成集積回路、第1図(blは半田クヮレ部が生じ
た混成集積回路、第2図は基板を加工する際の基板温度
と半田クヮレによる不良率の関係を示す図、第3図は本
発明の詳細な説明するための図である。 図において1ば基板、2はTa2Nよりなる抵抗体、3
はNiCrの薄膜、4はAuの薄膜、6はNiCrとA
uの拡散層を示す。
[Brief explanation of the drawings] Fig. 1 is a cross-sectional view of a hybrid integrated circuit using a thin film of tankur (Ta2N) as a resistor. Fig. 1 181 is a normal hybrid integrated circuit; A hybrid integrated circuit with solder cracks, FIG. 2 is a diagram showing the relationship between the substrate temperature during substrate processing and the defective rate due to solder cracks, and FIG. 3 is a diagram for explaining the present invention in detail. In the figure, 1 is a substrate, 2 is a resistor made of Ta2N, and 3 is a resistor made of Ta2N.
is a thin film of NiCr, 4 is a thin film of Au, and 6 is a thin film of NiCr and A.
The diffusion layer of u is shown.

Claims (1)

【特許請求の範囲】[Claims] 混成集積回路の製造において、半田付性を改善するため
に基板の温度を250℃以上に加熱し、スパッタ法によ
り基板表面にNiCr−八Uよりなる電極膜を生成する
ことを特徴とする混成集積回路の製造方法。
In the production of hybrid integrated circuits, the temperature of the substrate is heated to 250°C or higher to improve solderability, and an electrode film made of NiCr-8U is formed on the surface of the substrate by sputtering. Method of manufacturing circuits.
JP1560684A 1984-01-31 1984-01-31 Manufacture of hybrid integrated circuit Pending JPS60160656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1560684A JPS60160656A (en) 1984-01-31 1984-01-31 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1560684A JPS60160656A (en) 1984-01-31 1984-01-31 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS60160656A true JPS60160656A (en) 1985-08-22

Family

ID=11893372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1560684A Pending JPS60160656A (en) 1984-01-31 1984-01-31 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS60160656A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2307595A (en) * 1995-11-21 1997-05-28 Mitsubishi Electric Corp Optical semiconductor device and method of manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2307595A (en) * 1995-11-21 1997-05-28 Mitsubishi Electric Corp Optical semiconductor device and method of manufacture
GB2307595B (en) * 1995-11-21 1997-11-05 Mitsubishi Electric Corp Optical semiconductor device and method of manufacturing thereof

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