JPS60160644A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS60160644A
JPS60160644A JP59015197A JP1519784A JPS60160644A JP S60160644 A JPS60160644 A JP S60160644A JP 59015197 A JP59015197 A JP 59015197A JP 1519784 A JP1519784 A JP 1519784A JP S60160644 A JPS60160644 A JP S60160644A
Authority
JP
Japan
Prior art keywords
conductive layer
bonding pad
integrated circuit
circuit device
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59015197A
Other languages
Japanese (ja)
Inventor
Keiji Miyamoto
宮本　圭二
Toru Kawanobe
川野辺　徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59015197A priority Critical patent/JPS60160644A/en
Publication of JPS60160644A publication Critical patent/JPS60160644A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
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    • H01L2224/05644—Gold [Au] as principal constituent
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the corrosion resistance of a bonding pad by covering with an insulation film which has an aperture for exposing the upper surface of the first conductive layer provided on a semiconductor substrate, providing the second conductive layer on the first conductive layer through the aperture and providing the third conductive layer between the two conductive layers being adhered to each layer. CONSTITUTION:A conductive layer 8A adhered on the upper surface of a conductive layer 7 is made of a lower cost metal than that of a conductive layer 9, e.g., silver. Normally, the silver itself is apt to have electromigration due to infiltration of water but the surface of the conductive layer 8A is to be covered with an alloy of gold and silver due to the conductive layer 9 made of gold and the effect of the electromigration is reduced. The conductive layer 8A can be formed to a film thickness of approx. 5,000Angstrom using spattering technique. Besides, a bonding pad 10A mainly consists of a conductive layer 5, a conductive layer 7, the conductive layer 8A and the conductive layer 9 and can be formed by etching technique after the conductive layers 7, 8A and 9 are formed.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、半導体集積回路装置（以下、ＩＯという→に
適用して有効な技術に関するものであり、特に、ｌＯの
ポンディングパッド形成技術に適用して有効な技術に関
するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is effective when applied to semiconductor integrated circuit devices (hereinafter referred to as IO), and in particular, to a technology that is applicable to bonding pad formation technology for IO. It is about effective techniques.

〔背景技術〕[Background technology]

１０は、その周辺部に内部集積回路と外部装置とを電気
的に接続するためのポンディングパッド（外部端子）欠
具備している。これは、具体的には、半導体素子、絶縁
膜等を介して半導体基板上部に配置された導電層に、そ
の上面部を露出させる開口部７有する窒化シリコン膜等
の保護膜を覆い構成されている。ＩＯは、そのポンディ
ングパッドとリードとをボンディングワイヤを介して電
気的に接続し、前記リードの一部を露出してそれうｙｘ
レジン等の封止材をもって封止されている。10 is provided with a bonding pad (external terminal) on its periphery for electrically connecting the internal integrated circuit and an external device. Specifically, this is constructed by covering a conductive layer disposed above a semiconductor substrate via a semiconductor element, an insulating film, etc., with a protective film such as a silicon nitride film having an opening 7 that exposes the upper surface of the conductive layer. There is. IO electrically connects its bonding pad and lead via a bonding wire, exposes a part of the lead, and yx
It is sealed with a sealing material such as resin.

かかる技術における検討の結果、本発明者は、ｌＯのポ
ンディングパッドにおいて、その充分な電気的信頼性を
得ることができないという問題点７見い出した。本発明
者は、前記問題点が、以１に述べる原因によって誘発さ
れるであろうと考察している。As a result of studies on this technology, the present inventor found problem 7 in that sufficient electrical reliability could not be obtained with the 1O bonding pad. The present inventor considers that the above-mentioned problem is caused by the causes described in 1 below.

ＩＯは、半導体素子間を電気的に接続する配線としてア
ルミニウム配線が用いられており、この配線の形成工程
と同一形成工程、すなわち、ポンディングパッドがアル
ミニウム層によって構成されている。そして、前記リー
ドと封止材との熱膨張率差による微小な隙間により、外
気の水分がリード、ボンディングワイヤを介してポンデ
ィングパッドに付着する。これによって、ポンディング
パッド部は、腐食あるいは破壊されてしまう。In the IO, an aluminum wiring is used as a wiring for electrically connecting semiconductor elements, and a bonding pad is formed in the same formation process as the wiring, that is, a bonding pad is formed of an aluminum layer. Moisture from the outside air adheres to the bonding pad via the lead and the bonding wire due to a minute gap caused by the difference in thermal expansion coefficient between the lead and the sealing material. As a result, the bonding pad portion is corroded or destroyed.

そこで、アルεニウム層によって構成されたポンディン
グパッドの耐腐食性を改善するために、金によって構成
された導電層で覆うことが考えられる。Therefore, in order to improve the corrosion resistance of the bonding pad made of an aluminum layer, it is considered to cover it with a conductive layer made of gold.

しかしながら、本発明者の検討の結果、保護膜との被着
性が悪いために、ポンディングパッドの耐腐食性を充分
に改善することができないという問題点、ならびに、ポ
ンディングパッドから金によって構成された導電層への
固相拡散による突き抜けにより生じる耐腐食性の劣化を
防止するために、金によって構成された導電層を充分な
膜厚で設けることによるコストの増７１０’￥：誘発す
るという問題点をさらに見い出した。However, as a result of studies conducted by the present inventor, it was found that the corrosion resistance of the bonding pad could not be sufficiently improved due to poor adhesion with the protective film, and that the bonding pad was made of gold. In order to prevent deterioration of corrosion resistance caused by penetration by solid phase diffusion into the conductive layer made of gold, the cost increase due to providing a conductive layer made of gold with a sufficient film thickness is considered to be induced. I found more problems.

し発明の目的〕 本発明の王な目的は、ｌＯに具備されるポンディングパ
ッドの耐腐食性を向上することが可能な技術手段を提供
することにある。OBJECTS OF THE INVENTION The main object of the present invention is to provide technical means capable of improving the corrosion resistance of a bonding pad provided in an IO.

本発明の他の目的は、１０に具備されるポンディングパ
ッドにおける電気的特性を向上することが可能な技術手
段を提供することにある。Another object of the present invention is to provide technical means capable of improving the electrical characteristics of the bonding pad included in the device 10.

本発明の他の目的は、ＩＯに具備でれるホンディングパ
ッドの耐腐食性を低コストで向上することが可能な技術
手段乞提供することにある。Another object of the present invention is to provide a technical means that can improve the corrosion resistance of a bonding pad included in an IO at low cost.

本発明の他の目的は、ｌＯの信頼性を向上することが可
能な技術手段を提供することにある。Another object of the present invention is to provide technical means capable of improving the reliability of IO.

本発明の前記ならびに他の目的と新規な特徴は、本明細
書の記述および添付した図面によって明らかになるであ
ろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

し発明の概要〕 本ＢＢｒＣおいて開示でれる発明のうち、代表的なもの
の概要を簡単に説明すれば、下記のとおりである。Summary of the Invention] Among the inventions disclosed in this BBrC, a brief outline of typical inventions is as follows.

すなわち、保護膜の開口部において露出するアルミニウ
ムによって構成これてなる導１！層の上面部に、チタン
等の活性化金属層と、その上部に銀。That is, the conductor 1 is made of aluminum exposed at the opening of the protective film. On the top of the layer is a layer of activated metal such as titanium, and on top of that is silver.

パラジウム等の第１の貴金属層と、さらに、その上部に
金によって構成されてなる第２の貴金属層とを設けてポ
ンディングパッド乞構成することによって、前記保護膜
と活性化金属との被着性は良好で前記導電層への水分の
浸入を防止できるという作用、および、第２の貴金属層
の膜厚を第１の貴金属層で変換することができるという
作用で、ポンディングパッドの耐腐食性馨向上しｌＯの
信頼性を向上することができ、かつ、そのためのコスト
増力口を抑制することができる。By forming a bonding pad by providing a first noble metal layer such as palladium and a second noble metal layer made of gold on top of the first noble metal layer, adhesion of the protective film and the activated metal is achieved. The corrosion resistance of the bonding pad is improved by the ability to prevent moisture from entering the conductive layer, and by the ability to change the thickness of the second noble metal layer with the first noble metal layer. It is possible to improve performance and reliability of IO, and to suppress cost increases for this purpose.

以下、本発明の構成について、実施例とともに説明する
。なお全図において同一機能を有するものは同一符号ケ
付してそのくり返しの説明は省略する。Hereinafter, the configuration of the present invention will be explained along with examples. Components having the same functions in all the figures are given the same reference numerals, and repeated explanations will be omitted.

〔実施例〕〔Example〕

第１図は、本発明を用いて構成したポンディングパッド
を具備するＬＯｉ封止したレジンパッケージの一部欠き
斜視色である。FIG. 1 is a partially cutaway color perspective view of an LOi-sealed resin package that includes a bonding pad constructed using the present invention.

第１図において、１はレジン等によって構成された封止
部であり、後述するｌＯン中央部に具備し、それを外部
の悪条件から保護するとともに、例えはプリント基板に
配置するためのものである。In Fig. 1, numeral 1 is a sealing part made of resin or the like, which is provided in the center of the 1O2 to be described later, to protect it from adverse external conditions, and to place it on a printed circuit board, for example. It is.

２は封止部１の所定の位置に複数本設けられた例えば鉄
−ニッケル合金によって構成されたリードであり、後述
するＩＯと外部装置とを電気的に接続するためのもので
ある。３は本発明を用いて構成したポンディングパッド
をその周辺部に複数具備してなるＩＣであり、その中央
部にはたとえは多数の半導体素子ン用いて構成された論
理回路を具備している。４はリード２の一端部と１０３
のポンディングパッドとラミ党内に接続するためのボン
ディングワイヤであり、たとえば金によって構成されて
いる。なお、リード２の他端部は、例えばプリント基板
に電気的に接続されるようになっている。A plurality of leads 2 are provided at predetermined positions in the sealing part 1 and are made of, for example, an iron-nickel alloy, and are used to electrically connect an IO and an external device, which will be described later. 3 is an IC having a plurality of bonding pads constructed using the present invention in its peripheral portion, and a logic circuit constructed using, for example, a large number of semiconductor elements in its central portion. . 4 is one end of lead 2 and 103
A bonding wire for connecting the bonding pad and the inside of the laminate, and is made of, for example, gold. Note that the other end of the lead 2 is electrically connected to, for example, a printed circuit board.

次に、１０の周辺部に具備されるボンティングパッドの
具体的な構成について説明する。Next, a specific configuration of the bonding pad provided in the peripheral portion of the device 10 will be described.

第２図は、第１図の点線］で示した部分における要部拡
大平面図、第３図は、第２図のＩＩＩ　−Ｉｌｌ切断Ｉ
ｗＶＣおける要部拡大断面図である。FIG. 2 is an enlarged plan view of the main part of the part indicated by the dotted line in FIG.
FIG. 2 is an enlarged cross-sectional view of main parts of wVC.

第２図および第３図において、３Ａは１０３を構成する
半導体基板（図示していない）上部に半導体素子、半導
体素子間を接続する例えば製造プロセスにおける第１層
目の導電層上面部して設けられた絶縁膜であり、それら
とその上部に設けられる導電層とン電気的に分離するた
めのものである。５は絶縁膜３Ａ上部に設けられた例え
ば製造プロセスにおける第２７ｉｔ目の導Ｉ！＃であり
、１０３の中央部では半導体素子間等を接続するものと
して使用し、１０３の周辺部ではポンディングパッドを
構成するためのものである。これは、低抵抗値のアルミ
ニウムまたはアルミニウム合金を用いて構成すればよい
。６は導電層５′１を覆うようにして設けられたたとえ
ばプラズマ技術による窒化シリコンによって構成された
保護膜であり、導電層５の腐食等Ｉ０３ン外部の悪条件
から保護するためのものである。６Ａは導１１Ｌｆ＠５
のポンディングパッドが形成されるべき部分の上部の保
ｌａ膜６を選択的に除去して形成した開口部であり、導
電層５を露出してそこにポンディングパッドを構成させ
るためのものである。７は開口部６Ａを介して導を層５
の上面部に被着して設けられた導電層であり、マスク合
せズレ、保護膜６への被活性等ン考慮して、その一部は
開ロ部６Ａ周辺の保護膜６上面にも形成窟れる。導電層
７は、保護膜６との被着性が貴金属よりも良好であり耐
腐食性も良好な活性化金属、たとえばスパッタ技術によ
るチタンを用い、その膜厚を１５００〜２０００ＣＡ’
：ｌに形成すればよい。また、導電層７の膜厚は、第１
導電層５との接合部の面積と比較して充分に小さいので
、導を層７の抵抗値はそこを流れる電流に対して問題と
ならない。８は導電層７の上面部に被着して設けられた
導電層であり、後述するがその上部に、形成される金に
よって構成されるより低コストな貴金属、たとえばパラ
ジウムによって構成されている。導を層８は、金によっ
て構成される導電層の膜厚を低減し、ＩＣ３の低コスト
化７図るためのものである。In FIGS. 2 and 3, 3A is provided on the top of a semiconductor substrate (not shown) constituting 103 as a top surface of a semiconductor element and a first layer of conductive layer for connecting between semiconductor elements in the manufacturing process. This is an insulating film that is used to electrically isolate them from a conductive layer provided on top of the insulating film. 5 is, for example, the 27th it conductive I! provided on the upper part of the insulating film 3A in the manufacturing process! The central portion of 103 is used to connect semiconductor elements, and the peripheral portion of 103 is used to form a bonding pad. This may be constructed using low resistance aluminum or aluminum alloy. Reference numeral 6 denotes a protective film made of silicon nitride using plasma technology, which is provided to cover the conductive layer 5'1, and is used to protect the conductive layer 5 from adverse external conditions such as corrosion. . 6A is lead 11Lf@5
This opening is formed by selectively removing the laminated layer 6 above the portion where the bonding pad is to be formed, and is intended to expose the conductive layer 5 and form the bonding pad there. be. 7 conducts conduction through the opening 6A to the layer 5.
This is a conductive layer deposited on the top surface, and a part of it is also formed on the top surface of the protective film 6 around the opening 6A in consideration of mask misalignment, activation of the protective film 6, etc. I can cave. The conductive layer 7 is made of an activated metal that has better adhesion to the protective film 6 than noble metals and has better corrosion resistance, such as titanium produced by sputtering technology, and has a film thickness of 1500 to 2000 CA'.
:L. Further, the film thickness of the conductive layer 7 is
Since the area of the conductive layer 7 is sufficiently small compared to the area of the junction with the conductive layer 5, the resistance value of the conductive layer 7 does not matter with respect to the current flowing therethrough. Reference numeral 8 denotes a conductive layer provided on the upper surface of the conductive layer 7, and as will be described later, the conductive layer 8 is made of a noble metal such as palladium, which is lower in cost than the formed gold. The conductive layer 8 is intended to reduce the thickness of the conductive layer made of gold and to reduce the cost of the IC 3.

本発明者は、導ｔＪｉｌ＋７を形成する活性化金属が固
相拡散によって貴金属からなる導電層上面部に突き抜け
るのＺ避けるためには、貴金属からなる導電層の厚さは
５０００（Ａ）以上必要であるとしている。したがって
、前記導電層８の厚さは、後述する金によって構成され
る導電層の換厚乞考慮しスパッタ技術ビ用いて４０００
（Ａ）以上にすれはよい。９は導電層８上面部に被着し
て設けられた導を層であり、金によって構成されており
、ポンディングパッドとボンディングワイヤ４とのボン
ダビリティを向上するためのものである。導電層９は、
例えば、ホトレジストマスクを用い、無電界メッキ技術
によって、１０００〜３０００（Ａ）程度の膜厚で形成
すればよい。なお、ホトレジストマスクを形成すること
で、無電界メッキを施す際のメッキ液による保護膜６へ
の悪影響を防止することができる。ポンディングパッド
ｌＯは、王として、導ｔ７１５．導電層７．導電層８お
よび導電層９によって構成される。４Ａはポンディング
パッド１０とボンディングワイヤ４との電気的接続部に
設けられたワイヤヘッドである。ポンディングパッド１
０特に導電層９とボンデイン・グワイヤ４特にワイヤヘ
ッドｉｈとの被着性、すなわちボンダビリティは、極め
て良好である。The inventor has determined that the thickness of the conductive layer made of a noble metal must be 5000 (A) or more in order to prevent the activated metal forming the conductor tJil+7 from penetrating into the upper surface of the conductive layer made of the noble metal due to solid phase diffusion. It is said that there is. Therefore, the thickness of the conductive layer 8 is determined by using a sputtering technique of 4,000 mm, taking into consideration the thickness of the conductive layer made of gold, which will be described later.
(A) It's better than above. Reference numeral 9 denotes a conductive layer provided on the upper surface of the conductive layer 8, which is made of gold and is used to improve bondability between the bonding pad and the bonding wire 4. The conductive layer 9 is
For example, it may be formed with a film thickness of about 1000 to 3000 (A) by electroless plating using a photoresist mask. Note that by forming the photoresist mask, it is possible to prevent the protective film 6 from being adversely affected by the plating solution during electroless plating. Pounding pad lO as king, lead t715. Conductive layer 7. It is composed of a conductive layer 8 and a conductive layer 9. 4A is a wire head provided at the electrical connection between the bonding pad 10 and the bonding wire 4. Ponding pad 1
In particular, the adhesion between the conductive layer 9 and the bonding wire 4, especially the wire head ih, that is, the bondability, is extremely good.

次に、その実施例について説明する。Next, an example thereof will be described.

第４図は、本発明を用いて構成したポンディングパッド
を具備する１０の要部拡大断面図である。FIG. 4 is an enlarged cross-sectional view of ten main parts provided with a bonding pad constructed using the present invention.

第４囚において、８Ａは導電層７の上面部に被着して設
けられた導を層であり、導電層９より低コストな貴金属
、たとえば銀によって構成されている。通常、銀そのも
のは、水分の浸入によって工し・クトロマイグレーショ
ンを生じやすいが、金によって構成されてなる導電層９
によって、導電＃８Ａの表面部は金−銀合金で覆われる
ようになっており、エレクトロマイグレーションによる
影響は低減されるようになっている。導電層８Ａは、ス
バクタ技術を用い、　５０１）０（Ａ）程度の膜厚で形
成すればよい。なお、ポンディングパッドＩＯＡは、主
として、導電層５．導電層７．導！、＊８Ａおよび導電
層９によって構成されている。そして、それぞれの導１
［層７．８Ａ、９の形成後に、ホトレジストマスクを用
い、エツチング技術によって本発明はさらに変形可能で
ある。例えば第３図において導電層８の形状を導電層９
の形状と実質的に同一にすることも可能である。これは
導電層９１ホトリソグラフイ技術により形成後、導電層
９を形成するために用いたマスクをそのまま用いて、導
ＩＩ層８をエツチングすれば簡単に実現できる。In the fourth case, 8A is a conductive layer provided on the upper surface of the conductive layer 7, and is made of a noble metal lower in cost than the conductive layer 9, such as silver. Normally, silver itself is susceptible to deterioration and ctromigration due to the infiltration of moisture, but the conductive layer made of gold 9
As a result, the surface of conductor #8A is covered with a gold-silver alloy, and the influence of electromigration is reduced. The conductive layer 8A may be formed to a thickness of approximately 501)0(A) using Subactor technology. Note that the bonding pad IOA is mainly formed by the conductive layer 5. Conductive layer 7. Guide! , *8A and a conductive layer 9. And each lead 1
[After the formation of layers 7.8A, 9, the invention can be further modified by etching techniques using a photoresist mask. For example, in FIG. 3, the shape of the conductive layer 8 is changed to the shape of the conductive layer 9.
It is also possible to make the shape substantially the same as that of . This can be easily achieved by forming the conductive layer 91 by photolithography and then etching the conductive layer 8 using the same mask used to form the conductive layer 9.

〔効果〕〔effect〕

レジン等の封止部材を用いて封止したポンディングパッ
ドを具備するＩＣにおいて、以下に述べる効果を得るこ
とができる。In an IC including a bonding pad sealed using a sealing member such as resin, the following effects can be obtained.

（１１，アルミニウムまたはアルミニウム合金によりて
構成されてなる第１の導電層と、該第１の導電層の上面
部を露出させる開口部を有する保護膜を介して設けられ
た金によって構成されてなる第２１１１！層との間部に
、活性化金属によって構成されてなる第３の導電層を設
け、ポンディングパッドを構成することにより、前記保
護膜と第３の導電層との被着性が良好で前記第１の導電
層への水分の浸入を防止できるという作用で、ホンディ
ングパッドにおける耐腐食性を向上することができる。(11. A first conductive layer made of aluminum or an aluminum alloy, and gold provided through a protective film having an opening that exposes the upper surface of the first conductive layer. By providing a third conductive layer made of an activated metal between the 2111! layer and forming a bonding pad, the adhesion between the protective film and the third conductive layer is improved. The corrosion resistance of the bonding pad can be improved due to the effect of preventing moisture from entering the first conductive layer.

（２）、前記（１）により、その耐腐食性を向上するこ
とができるという作用で、ポンディングパッド忙おける
電気的特性を向上することができる。(2) Due to (1) above, the corrosion resistance can be improved, and the electrical characteristics of the bonding pad can be improved.

（３）、前記（２）により、ポンディングパッドにおけ
る電気的特性を向上することができるという作用で、１
０の信頼性を向上することができる。(3) Due to the above (2), the electrical characteristics of the bonding pad can be improved;
0 reliability can be improved.

（４１、前記第２の導電層と第３の導１１層との間部に
、銀またはパラジウム等によって構成されてなる第４の
導電層を設けることにより、第２の導を層の膜厚をそれ
よりも低コストの第４の導電層で変換することができる
という作用で、ＩＣのコスト増力り潜抑面１ｊすること
ができる。(41. By providing a fourth conductive layer made of silver, palladium, etc. between the second conductive layer and the third conductive layer 11, the thickness of the second conductive layer is reduced. This effect can be converted by the fourth conductive layer, which is lower in cost than the fourth conductive layer, thereby increasing the cost of the IC and reducing the potential.

（５）、前記（３ｉ、　［４１により、低コストで信頼
性が高いＩＯ％−得ることができる。(5), above (3i, [41), it is possible to obtain IO%- at low cost and with high reliability.

以上、本発明者によりてなされた発明を実施例とともに
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲において種々
変更可能であることはいうまでもない。Above, the invention made by the present inventor has been specifically explained along with Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

たとえば、前記活性化金属によって構成されてなる導を
層は、チタンの他にタングステン、クロム、タンタル等
でもよく、少なくとも保護膜と被着性の良い金属であれ
ばよい。また、それらの合金でもよい。For example, the conductive layer made of the activated metal may be made of tungsten, chromium, tantalum, etc. in addition to titanium, and any metal that has good adhesion to at least the protective film may be used. Also, alloys thereof may be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明を用いて構成した１０を封止し１こレ
ジンパッケージの一部欠き斜視図、第２図は、第１図の
点線■で示した部分における要部拡大平面図、 第３図は、第２図のＩＩＩ−ＩＩＩ切断線における要部
拡大断面図、 第４図は、本発明を用いて構成したｌＯの要部拡大断面
図である。 図中、１・・・封止部、２・・・リード、３・・・ＩＣ
。 ３Ａ・・・絶縁膜、４・・・ボンディングワイヤ、４Ａ
・・・ワイヤヘクト、５．７，８，８Ａ、９・・・導電
層、６・・・保護膜、６Ａ・・・開口部、１０．、ＩＯ
Ａ・・・ボンディングパッドである。 第　１　図 第　２　図FIG. 1 is a partially cutaway perspective view of a resin package 10 constructed using the present invention, and FIG. 2 is an enlarged plan view of the main part of the portion indicated by the dotted line ■ in FIG. 1. FIG. 3 is an enlarged cross-sectional view of the main part taken along the line III--III in FIG. 2, and FIG. 4 is an enlarged cross-sectional view of the main part of IO constructed using the present invention. In the figure, 1...Sealing part, 2...Lead, 3...IC
. 3A... Insulating film, 4... Bonding wire, 4A
... wire hect, 5.7, 8, 8A, 9 ... conductive layer, 6 ... protective film, 6A ... opening, 10. ,IO
A: Bonding pad. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 １、第１の絶縁Ｒ’４ｉ介して半導体基板上部に設けら
れた第１の導電層を、その上面部を露出させる開口部を
有する第２の絶縁膜で覆い、前記開口部を介し第１の導
電層上部に第２の導電層を具備し、前記第１の導′ｆＩ
Ｌ層と第２の導電層との間部にそれぞれと被着して第３
の導電層を具備してなること夕特徴とする半導体集積回
路装置。 ２、前記第１の導を層は、アルミニウムまたはアルミニ
ウム合金によって構成されてなることン特徴とする特許
請求の範囲第１項記載の半導体集積回路装置。 ３、前記第２の導電層は、金によって構成されてなるこ
とを特徴とする特許請求の範囲第１項記載の半導体集積
回路装置。 ４、前記第３の導１！層は、活性化金属によって構成さ
れてなることを特徴とする特許請求の範囲第１項記載の
半導体集積回路装置。 ５、前記第２の導電層と第３の導を層とは、その間部に
第２の導１！庵と異なる貴金属によって構成された第４
の導電層を具備してなることを特徴とする特許請求の範
囲第１項乃至第４項記載の半導一体集積回路装置。 ６、前記第４の導電層は、銀またはパラジウムによって
構成されてなることを特徴とする特許請求の範囲第５項
記載の半導体集積回路装置。 ７、前記露出された部分の第１の導電層、第２の導’ｉ
ｉｒ、＊、第３の導電層および第４の導を層は、ボン″
ディングパッドを構成してなること′４を特徴とする特
許請求の範囲第５項および第６項記載の半導体集積回路
装置。[Claims] 1. Covering the first conductive layer provided on the top of the semiconductor substrate via the first insulating layer R'4i with a second insulating film having an opening that exposes the top surface thereof; A second conductive layer is provided above the first conductive layer through an opening, and the first conductive layer
A third conductive layer is deposited between the L layer and the second conductive layer.
1. A semiconductor integrated circuit device comprising a conductive layer. 2. The semiconductor integrated circuit device according to claim 1, wherein the first conductive layer is made of aluminum or an aluminum alloy. 3. The semiconductor integrated circuit device according to claim 1, wherein the second conductive layer is made of gold. 4. The third lead 1! 2. The semiconductor integrated circuit device according to claim 1, wherein the layer is made of activated metal. 5. The second conductive layer and the third conductive layer have a second conductive layer between them. The fourth one is made of precious metals different from the hermitage.
5. A semiconductor integrated circuit device according to claim 1, comprising a conductive layer. 6. The semiconductor integrated circuit device according to claim 5, wherein the fourth conductive layer is made of silver or palladium. 7. The exposed portion of the first conductive layer and the second conductive layer
ir, *, the third conductive layer and the fourth conductive layer are bonded
The semiconductor integrated circuit device according to claims 5 and 6, characterized in that the semiconductor integrated circuit device comprises a pad.
JP59015197A 1984-02-01 1984-02-01 Semiconductor integrated circuit device Pending JPS60160644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59015197A JPS60160644A (en) 1984-02-01 1984-02-01 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59015197A JPS60160644A (en) 1984-02-01 1984-02-01 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS60160644A true JPS60160644A (en) 1985-08-22

Family

ID=11882134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59015197A Pending JPS60160644A (en) 1984-02-01 1984-02-01 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS60160644A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015010931A (en) * 2013-06-28 2015-01-19 富士電機株式会社 Semiconductor pressure sensor device and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015010931A (en) * 2013-06-28 2015-01-19 富士電機株式会社 Semiconductor pressure sensor device and manufacturing method of the same

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