JPS6015982B2 - Priority processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a priority processing device that controls the use of a communication channel that is used by a plurality of data processing devices in a time-sharing manner.

Conventionally, in this type of communication channel, when the communication channel is shared by multiple data processing devices, priority processing is performed by dividing the communication channel in time and then assigning the divisions to each data processing device. They shared a communication channel without any trouble.

In other words, as shown in FIG. 1, in the conventional priority processing system, a circuit 101 that generates a signal indicating a time delimiter and a priority determination circuit 102 that generates a signal for a data processing device that permits use of a communication channel are used. From the circuit 1 that manages the communication path including, one of the transmitting circuits 30, 30', 30r... connected to the signal line via the signal lines 201, 203 is selected, and only the selected one is selected. allows the data bus 202 connected to the transmitting circuit group to be used. That is, in each transmitting circuit, a comparison circuit 301 compares the number from the signal line 203 and the number generated by the own device using a signal from the signal line 201, and a circuit 302 transfers data according to this result. data bus 202
Transfer data using .

Note that the selection of the transmitting circuit using the signal lines 201 and 203 is performed by the circuit 303 that generates a signal requesting data transfer generating a signal on the data transfer request signal line 204, and in response to this, the priority determining circuit 102 selects the data bus. The number of the transmitting circuit that is permitted to be used is determined and the number is output to the signal line 203.

At the same time, this is done by generating a signal from the timing circuit 101 that indicates the usage time period of the data bus. Therefore, each data processing device is only able to use a communication path when it is designated by the signal line 203, and even if a communication path is available, it cannot use it.

Furthermore, it is necessary to specify the data processing device using the communication path using the signal line 203.

An object of the present invention is to connect transmitting circuits in cascade, and each transmitting circuit adds a signal indicating the use of the communication channel to a signal indicating the time division of the communication channel, and transmits the signal to the next cascaded transmitting circuit. On the other hand, the present invention provides a priority processing device that prohibits the use of the communication channel and enables time-division use of the communication channel according to the priority order generated by the connection order.

The present invention provides a priority processing specifying means for sending a priority processing signal indicating data transfer timing to a priority processing signal line, and a transmission circuit that sequentially lowers the priority in the order in which signals from the priority processing signal line are inputted to the priority processing signal line. a group of transmitting circuits connected in series by a signal line and a data bus; one or more receiving circuits connected to the transmitting circuit that last inputs the signal of the priority processing signal line among the transmitting circuit group; and the priority processing signal. When a line signal is input, if the transmitting circuit does not wish to transmit, it outputs the input signal as it is as a priority processing signal, and if the transmitting circuit wishes to transmit, it outputs the input signal as a priority processing signal. If the signal is not a data bus use indication signal,
A priority processing signal is output as a data bus usage indication signal, and data and the address of the transmitting circuit are output to the data bus during a time period corresponding to this data bus usage indication signal, so that the signal on the priority processing signal line is the data bus usage indication signal. The present invention is implemented by a priority processing device that does not output the data to the data bus if it is a bus use indication signal.

FIG. 2 is a diagram showing an embodiment of the present invention, and the priority processing device shown in this embodiment includes a timing circuit 10,
This timing circuit 1 is connected to the timing circuit 10
Priority processing signal line 201 that transmits the priority processing signal generated by
(general term for 2010, 2011...), and a plurality of transmitting circuits 30 connected to this priority processing signal line 201,
30'. 30r, a receiving circuit 40 connected via the priority processing signal line 201, and each transmitting circuit 30, 30', 30.
A data bus 202 (20
20, 2021, etc.).

Signals and data propagate in this device in the direction of the arrow.
Further, the transmitting circuits 30, 30', 30'' are connected in cascade according to the priority using the data bus 202.
In this embodiment, the timing circuits are connected so that the closer they are by one river, the higher the priority.

Next, an example of this operation will be explained using FIG. 3. First, the priority processing signal a generated from the timing circuit is a signal that is repeatedly generated with a pulse width to and a period T, and is applied to the three transmitting circuits via a signal line 2010. In response to the generation of the priority processing signal a, data A in which all signals on the data bus 202 are 0 is provided. now,
The transmitting circuit 30 does not request data transfer, the transmitting circuit 30' with the next highest priority requests data transfer, and the transmitting circuit 30^ with the lowest priority also requests data transfer. Suppose.

First, since the transmission circuit 30 does not declare the use of the data bus 202, the priority processing number a is transmitted to the next 2011 without any change.

At this time, data A is also transmitted to the signal line 2021 as is. Next, in the transmitting circuit 30', when the priority processing signal a is received through the signal line 2011, the priority processing signal a becomes the data bus use indication signal b and is output to the signal line 2012.

The pulse width t of this signal is smaller than T from a certain slit of data A to another slit, and moreover, the pulse width t of the priority processing signal generated from the timing circuit 10
This signal has a pulse width larger than o. A feature of the present invention is that this pulse width is made larger than the pulse width to of the input priority processing signal and output. In response to the output of this signal, the data bus 2022 is connected to the transmitting circuit 3.
Data B prepared by 0' is inserted and sent to the next transmitting circuit. The transmission circuit 30r receives the priority processing signal 201
When the data bus use indication signal b of 2 is received, the signal line 20
12, 2022 as is to the next signal line 2013,
2023. In this case, although the transmitting circuit 30'' declares the use of the data bus 202, its operation is inhibited.

Thereafter, each time the transmitting circuit 30'' receives the data bus use indication signal b on the priority processing signal line 2012, the transmission circuit 30''
, 2022 are sent as they are to the next circuit. Also, the priority processing signal line 201 to the transmission circuit 30^
2, if the priority processing signal a is received, the transmitting circuit 30
'Similarly, the priority processing signal a is used as the data bus use indication signal b.
and send it to the next circuit. Correspondingly, data prepared by the transmitting circuit 30'' is sent to the data bus 2023.

When the reception circuit 40 detects that the pulse width of the signal input from the priority processing signal line 2013 is the next pulse width (data bus use indication signal b), the receiving circuit 40 transfers the corresponding data to the priority processing signal line of the data bus 2023. It is received from the area corresponding to 201. Next, a specific example of the transmitting circuit will be described with reference to FIG. 4.

This circuit consists of a pulse width detection circuit 301 that detects the pulse width of the priority processing signal and a data transfer circuit 302. Among these, the pulse width detection circuit 301 receives a signal with a logical value of "1" from the data transfer circuit 302 when the eye bag devil requests data transfer, and connects this signal line 3011 and the priority processing signal line. AND circuit 3 that takes logical product with 201
010 and the output of this AND circuit 3010, a signal is generated at the rising edge of the signal, and the pulse width t.010 is the same as the data bus use indication signal. A monostable multipipulator (e.g. a one-shot circuit) 30 that generates a signal with
12, the output signal 3014 of this monostable multipipulator 3012, and the priority processing signal 201 are ORed.
The R circuit 3013 receives the output signal 3014 and the negative signal of the priority processing signal 201, and compares the pulse widths by performing an AND operation.The signals from the comparison circuit 3015 match. The width correction circuit 3016 is configured to cancel out a sharp waveform /z signal with a minute error even though the signal is output. Note that this width correction circuit is a design issue and is not essential to the present invention, and may or may not be added. Next, the data transfer circuit 302 includes a data transfer section 3020, a data transfer control section 3021, and other logic circuits. First, if the priority processing signal is a signal with a pulse width to and the Miya equipment is requesting data transfer, the monostable multipipulator 3012 sends a signal with a pulse width to
A signal of t, is output and a signal of pulse width t is sent to the priority processing signal line 201, and a signal of the difference between the pulse width t and the pulse width is output as an output of the comparison circuit 3015, and this signal is input to the data transfer control unit, and in response to this signal, since the comparison results do not match in this case, data is sent from the data transfer circuit 3020. Next, the own device is requesting data transfer and the priority processing signal is 20.
When the pulse width of 1 is different, the output signal from the comparator circuit 3015 has a logic value of "0".

In this case, no data is transferred.

If the device itself has not requested data transfer, no signal is input to the comparison circuit 3015 even if the pulse width of the priority processing signal 201 is appalling. In this case, that is, when a logical value "0" is output to the signal line 3011, data is not transferred from the data transfer circuit 201. As a result, as described above, only the transmitting circuit with the highest priority among the plurality of transmitting circuits that have declared use can use the data bus.

As a result, data is propagated to the data bus 202, and a data bus use indication signal is propagated to the priority processing signal line 201 and input to the receiving circuit 40.

An example of a concrete circuit of this receiving circuit is shown in FIG.

This receiving circuit 40 is composed of a data receiving section 402 and a signal detecting section 401 that detects a data bus use indication signal. This signal detection section 401 includes a monostable multipipulator 4012 similar to the transmitting circuit and an output signal 4021.
A comparison circuit 4017 that compares the signal with the priority processing signal 201
The comparison result is input to the data receiving section 402 via the signal line 4011. This data receiving section 40
2 includes a circuit that receives and stores data from data bus 202.

It is set and stored when the output signal 4011 of the signal detection circuit 401 described above is input.

If this is not done, all noise signals will also be stored, but if this point does not need to be taken into consideration, the signal detection circuit 401 is unnecessary. In addition, in order to identify which transmitter circuit the signal is from, calculate the pulse width and [2
, t3, respectively. In this case, the comparator circuit may detect a width of t or more.

Note that in this embodiment, the communication path is divided into a priority processing signal line and a data bus, but this is not an essential problem of the present invention;
One data bus can also be used as a priority processing signal line. Although the speed, the width of the data bus use indication signal, and the time between the rise times of each of the data A corresponding to the priority processing signal a are shown to be the same, they do not necessarily have to be the same. Furthermore, although the priority processing signal generated from the timing circuit 10 has been described as a signal with a constant period,
It is sufficient that the period is longer than the time required for data transfer, and does not necessarily have to be a constant period.

Furthermore, in this embodiment, when a priority processing signal is input from the transmitting circuit and the transmitting circuit requests data transfer, the pulse width of the signal is widened and used as a signal indicating the use of the data bus. Increasing the width is not an essential problem of the present invention, and may be implemented, for example, by changing the fin pressure value instead of the pulse width.

In this case, the reference pulse width generation circuit of this embodiment, which is the monostable multipipulator, is replaced with a reference pressure generation circuit, the comparison circuit becomes a circuit that compares voltage values, and the OR circuit calculates the sum of voltage values. This becomes the output circuit.

According to the present invention, when a data transfer request is made as described above, the transmitting circuit with the highest priority among the transmitting circuits uses the data bus, thereby producing the following effects.

In other words, conventionally, a data transfer request signal generation circuit, a data transfer request signal line for propagating the generated signal, and a priority determination circuit were required, but the purpose of this device can be achieved even without these. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a prior art priority processing device;
2 is a diagram showing an embodiment of the present invention, FIG. 3 is a time chart showing an example of the operation of the device shown in FIG. 2, and FIG. 4 is a diagram showing an example of the transmitting circuit shown in FIG. 2. circuit diagram and 5th
FIG. 2 is a circuit diagram showing an example of the receiving circuit shown in FIG. In FIG. 1, 101... A circuit that generates a signal indicating a time division, 102... A priority order determining circuit, 10... A circuit that manages a communication path.
Contains 1,102. 30.30', 30''...Transmission circuit, 301, 301'.30r...Comparison circuit included in the transmission circuit, 302, 302'.To 302...Data transfer circuit included in the transmission circuit , 303, 303',
303~...Circuit that requests data transfer to the circuit 10 included in the transmitting circuit, 40...Receiving circuit, 20
1,203,204...signal line, 202...data bus. In FIG. 2, 10...timing circuit, 30, 30
', 30r... Transmission circuit, 301, 301', 30r・
...Pulse width detection circuit, 302, 302', 30
2″...Data transfer circuit, 201 (2010,
2011, 2022, 2023)...Data bus,
40...Reception circuit. In Figure 4, 201...
...Signal line, 202, corresponding to 201 in Figure 2...
...data bus, 301 corresponding to 202 in Figure 2
...Pulse width detection circuit, 3 corresponding to 301 in Fig. 2
02...Nata transfer circuit, corresponding to 302 in Fig. 2, 3010...AND circuit, 3012...Single foot multipipulator, 3013...OR circuit, 3015
... Comparison circuit, 3016 ... Width correction circuit, 30
21...Data transfer control unit, 3020...
Data transfer section, 3011.3014...Signal line. In Fig. 5, 201...signal line, 201 in Fig. 2
Corresponding to 202...Signal line, 20 in Figure 2
401...Signal detection unit, 401 corresponding to 2
2... Monostable multipipulator, 4017... Comparison circuit, 402... Data receiving section, 4021.
4011...Signal line. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1 Priority processing specifying means for sending a priority processing signal indicating data transfer to a priority processing signal line at an interval longer than the data time width required for data transfer, and a priority processing specifying means for transmitting a priority processing signal indicating data transfer to a priority processing signal line at an interval longer than the data time width required for data transfer, and A transmitting circuit group in which the priority processing signal line is connected in cascade through a data bus, and a transmission circuit in which the signal of the priority processing signal line is input to the last one of the transmitting circuit group; When the above-mentioned receiving circuit and the signal of the priority processing signal line are input, if the transmission circuit does not wish to transmit, the input signal is output as is as a priority processing signal, and the transmission circuit desires transmission. In this case, if the signal on the priority processing signal line is not a data bus usage indication signal, the priority processing signal is output as a data bus usage indication signal, and the data is output in a time period corresponding to this data bus usage indication signal. A priority processing device that outputs an address of the transmitting circuit to the data bus, and does not output the data to the data bus if a signal on the priority processing signal line is a data bus use indication signal.