JPS6015719A - Digital phase servo circuit - Google Patents

Abstract

PURPOSE:To secure the shared use of a time base among plural servo circuits by detecting the time with a time base independent of the servo circuit. CONSTITUTION:When an interruption control signal is supplied at a CPU14, the count value of a latch circuit 11 is fetched and stored to an RAM16. At the same time, the time point where the preceding pulse signal is generated is read out and the cycle of the pulse signal is obtained. Then an error to a target cycle is detected from the target cycle stored in an ROM15, and this detected value is multiplied by the speed gain and stored to the RAM16. In the same way, an error to a target phase stored in the ROM15 is detected from the phase difference of the servo pulse signal and multiplied by the phase gain to be stored to the RAM16. These two values stored in the RAM16 are added together and delivered in response to the control range of a PWM converting circuit 19. Then the servo control is carried out with the phase and the speed of a motor 21. In the same way, the speed servo control is also given to a capstan motor 22.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital phase servo circuit that performs phase servo using a microprocessor.

Background Art and its Problems For example, in a recording/reproducing apparatus using a rotary head, it is necessary to perform speed servo, phase servo, or capstan speed servo of the drum of the rotary head.

In this case, in the phase servo, conventionally, for example, a counter is reset using a reference pulse, and this counter counts clock pulses.
A servo pulse obtained with each rotation is detected, and counting is stopped at this pulse, and control is performed so that the counted value at this time becomes a predetermined value.

However, when performing such servo, a dedicated counter is required for this phase servo. In order to increase the accuracy of the servo, a large circuit of, for example, 16 bits or more is used for the counter, so if multiple speed servos are performed in addition to the phase servo as mentioned above, a counter is required for each servo system. Since an extremely large number of counters are required, the circuit becomes large and complex, making it difficult to create a compact device.

OBJECTS OF THE INVENTION In view of these points, it is an object of the present invention to enable good phase servo with a simple configuration.

Summary of the Invention The present invention has a general-purpose time base, detects the time of arrival of a reference pulse from the time base at a desired time, and at the detected time corresponds to this one cycle for each cycle of the reference pulse. The time of the reference pulse after the desired time is detected by sequentially adding the time for which the servo pulse arrives, and the time of arrival of the servo pulse is detected from the time base, and the difference between these times is calculated. A digital phase servo circuit that detects the phase difference of a servo pulse with respect to the reference pulse and performs control so that the value of the difference becomes a predetermined value, and according to this digital phase servo circuit, it is possible to perform good phase servo with an ff1iR configuration. I can do it.

Embodiment In FIG. 1, the tape T is wound around a rotating head drum (11) rotated by, for example, 60117, and is transported by a capstan (2). a pulse generator 13 in each
), (41 are provided, and these generators +31, (
The servo pulse signals from 41 are sent to the waveform shaping circuit f.
5), flip-flop through f6) +7),
[8] is supplied to the data terminal. Also, the reference oscillator (
A clock signal of, for example, 2.8 MHz from 9) is supplied to a synchronization generation circuit (23) to form a vertical synchronization (reference) pulse of, for example, 6011z. Furthermore, the reference oscillator (
9) is sent to the flip-flop 171.9). +
81 clock terminal, and the 16-bit 1-
is supplied to the time base counter Om. The count value of each counter α0) is the data latch circuit (11), (1
2). Furthermore, the signal from the flip-flop (7) passes through the AND circuit (24) to the OR circuit (25).
The signal from the synchronization generating circuit (23) is supplied to the OR circuit (25) through the AND circuit (26), and the signal from this OR circuit (25) is supplied to the launch control terminal of the launch circuit (11). be done. A signal from the flip-flop is also supplied to the launch control terminal of the latch circuit (12). The numerical values of these launch circuits (11) and (12) are supplied to the data bus (13). A central processing circuit (CPU) (14), a read-only memory (ROM) (15), and a random access memory (RAM) (16) are connected to this data bus (13).

Further, an address signal from the CPU (14) is supplied to the address bus (17), and this '1 address signal is sent to the ROM (14).
5) is supplied to the RAM (16) and also to the read control terminals of the latch circuits (11) and (12). Furthermore, a flip-flop (8) and a synchronization generation circuit (
23) are supplied to the interrupt control circuit' (18), and determination signals corresponding to each signal are sent to the data bus (18).
3), and an interrupt control signal is also supplied to the CPU (1
4). Further, the reference pulse enable signal from the address bus is supplied to the AND circuit (26) and also to the AND circuit (24) through the inverter (27). Furthermore, the signal from the data bus (13) is PWM-converted. As well as being supplied to the circuits (19) and (20),
The address signal from the address bus (17) is sent to the conversion circuit (
19) and (20) are supplied to the write control terminals. PWM signals from the conversion circuits (19) and (20) are supplied to the drum motor (21) and capstan motor (22), respectively.

Furthermore, FIG. 2 shows a signal flow diagram for the drum motor (21). In the figure, a signal from a pulse generator (3) is supplied to a waveform shaping circuit (5), this signal is supplied to a data launch circuit (11) through an OR circuit (25), and a synchronization generation circuit (23) is supplied to the data launch circuit (II) through the OR circuit (25), and the time base counter 0 is
The count value from 0) is latched. In addition, the waveform shaping circuit (
5) and the synchronization generation circuit (23) are supplied to the interrupt control circuit (18), and the interrupt control signal is sent to the CPU (14).
).

When this interrupt control signal is supplied, the CPU (14
) takes in the latched count value into the latch circuit (11) at a predetermined timing.

Here, the counter αω counts the reference clock signal, so that this total value indicates the reference time.

In the CPU (14), first, when the reference pulse enable signal is "1-1" and an interrupt control signal is supplied by the signal from the synchronization generation circuit (23), step (39
), the count value of the latch circuit (11) is taken in, the time of occurrence of the taken reference pulse is stored in the RAM (16), and the reference pulse enable signal is set to rOJ.

When the interrupt control signal from the waveform shaping circuit (5) is supplied during the period when the reference pulse enable signal is rOJ, the count value of the latch circuit (11) is fetched in step (31). The generation time of the servo pulse signal is stored in the RAM (16), and the generation time of the previous pulse signal is read out, and the value of this difference is found. The value of this difference corresponds to the period of the pulse signal mentioned above.

Next, in step (32), ROM (1
5) The value of the target period indicated by (, 1) is subtracted. As a result, the value of the error from the target period is detected.

Further, in step (33), this error value is multiplied by a speed gain and stored in the RAM (16).

Further, when an interrupt control signal is supplied from the synchronization generation circuit (23) during the period when the reference pulse enable signal is 10'', the generation time of the reference pulse stored in the RAM (16) is determined in step (40). A value corresponding to the time of one cycle of the reference pulse stored in the ROM (15) is added to calculate the generation time of a new reference pulse, and this value is returned to step (39) and stored in the RAM ( 16)
is memorized. Further, in step (35), the count value of the launch circuit (11) is fetched, and the captured generation time of the servo pulse signal is subtracted from the above-described calculated reference pulse generation time. The value of this difference corresponds to the phase difference between the reference pulse and the servo pulse signal.

Next, in step (36), the ROM (
The target phase difference value stored in 15) is subtracted. As a result, the value of the error with respect to the target phase difference is detected.

Furthermore, in step (37), a phase gain is applied to this error value and stored in the RAM (16).

The two values stored in this RAM (16) are the step (
38), and the subsequent PWM is added in step (34).
The value range is regulated according to the control range of the conversion circuit (19) and output.

The PWM conversion circuit (19) is configured to obtain a predetermined rotation speed by supplying a predetermined drive current to the motor (21) at a predetermined rate of one rotation of the drum, and is adapted to obtain the predetermined rotation speed as described above. Speed and phase servo is performed by controlling the duty of the drive current that can be fully supplied to the motor (21) according to the supplied value.

Similarly, the speed servo of the capstan motor (22) is also performed.

Phase servo is performed in this way, but according to this circuit, time can be detected on a time base independent of servo. Therefore, the time base can be shared by multiple servos, and the configuration becomes extremely simple.

In other words, only one counter is required for a plurality of servos, making it possible to create a compact device with a simple circuit.

Furthermore, in the above-mentioned circuit, by calculating the reference pulse, the phase difference can be determined by providing only one latch circuit, and the configuration becomes extremely simple.

Further, as described above, when the servo pulse signal for phase servo is also used as the servo pulse signal for speed servo, it is sufficient to provide only one latch circuit for both the speed servo and the phase servo.

Note that in the above circuit, if the pulse generator (3) is configured such that the speed servo pulse is not generated during a predetermined period such as when XL rises, the AND circuit ll (24
) and inverter (27) are not required, and only an AND circuit (26) that cuts off the reference pulse after capturing the generation time of the reference pulse is required. This AND circuit (26) prevents confusion between speed servo pulses and reference pulses during operation.

In addition, as mentioned above, in a circuit without the AND circuit (24), if the speed servo pulse is generated from the beginning, the C
The period of the pulse is measured at the PU (14), and this period is R.
The time when the period becomes equal to the period stored in OM('15) may be set as the generation time of the reference pulse.

Furthermore, the time base can also be used for general purposes such as servos for reel motors, dynamic lighting of displays, etc.

Further, although the value of the counter QQI returns to 0 at approximately 7611z in the above example, an appropriate period and phase difference can be obtained by ignoring the borrow output during subtraction.

Further, at startup, etc., processing is not performed until a predetermined number of interrupts occur in a predetermined period of time, thereby preventing malfunctions during low-speed rotation.

Furthermore, these processes may be incorporated as part of the main routine instead of as an interrupt.

Furthermore, flip-flops +71 and +81 are provided to avoid changes in the value of the counter QOI.

Further, the PWM conversion circuits (19) and (20) may be DA conversion circuits.

Furthermore, by rewriting the target value stored in the I ROM (15) in the above-mentioned circuit, servo can be applied to any desired value, and the circuit can be used as a general-purpose circuit.

Effects of the Invention According to the present invention, good phase servo can be performed with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an example of the present invention, and FIG. 2 is a diagram for explaining the same. fi+ is a rotating head drum, (2) is a capstan, (
3). (4) is a pulse generator, (51, +61 is a waveform shaping circuit, QO) is a time base counter, (11), (12)
) is the data latch circuit, (14) is the central processing circuit, (1
5) is a read-only memory, (16) is a random access memory, (18) is an interrupt control circuit, (19), (
20) is a PWM conversion circuit, (21) is a drum motor, (
22) is a capstan motor, and (23) is a synchronization generating circuit.

Claims (1)

[Claims] It has a general-purpose time base, detects the arrival time of the reference pulse from the time base at a desired time, and sequentially adds the time equivalent to this one cycle to the detected time for each cycle of the reference pulse. detecting the time of the reference pulse after the desired time, detecting the time of arrival of the servo pulse from the time base, and finding the difference between these times;
A digital phase servo circuit that detects a phase difference between the servo pulse and the reference pulse based on the value of this difference, and performs control so that the value of the difference becomes a predetermined value.