JPS60153277A - Synchronizing clock generating circuit - Google Patents

Abstract

PURPOSE:To prevent a picture from horizontal jitter by generating a sampling clock holding a fixed phase to a horizontal synchronizing signal in a device displaying television picture. CONSTITUTION:Frequency 6fsc of three times sampling frequency 2ffc is generated by a PLL50. Then, six clocks phi0-phi5 having the same frequency as the sampling frequency and different phases in each 60 deg. are generated by a frequency divider 51. Three pulses having a fixed phase to a horizontal synchronizing signal and having different phases by 120 deg. respectively are selected by sampling clock switching circuits 52a-52c. Video signals are sampled by using the three clocks having different phases by 120 deg. respectively. Consequently, video information compensated at its phase to the horizontal synchronizing signal and the sampling clock are kept at a fixed phase.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention is a method for generating an electron beam in each section when a screen coated with a phosphor is vertically divided into a plurality of sections. It is a device that displays a television image as a whole by deflecting each electron beam in the vertical direction for each section and displaying a plurality of lines. The present invention relates to a synchronous clock generation circuit used in a sampling clock generation circuit for demodulated R, , G, and B video signals of an image display device having the feature that the position of a pixel is determined.

(Structure of the conventional example and its problems) One basic example of the structure of the image display element used here will be described with reference to FIG. 1.

This display element has a back electrode 1. Line cathode 2 as beam source, vertical focusing electrodes 3, 3'
, a vertical deflection electrode 4, a beam flow control electrode 5, a horizontal focusing electrode 6, a horizontal deflection electrode 7, a beam acceleration electrode 8, and a screen plate 9 are arranged, and these are connected to a flat glass bulb (not shown). It is housed inside a vacuum chamber.

A line cathode 2 serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction. In the figure, only four wires 2-2 are shown). In this example, it is assumed that 15 are provided. Let's call them 2i~2yo. These wire cathodes 2 are constructed by coating the surface of a tungsten wire with a diameter of 10 to 20/lφ with an oxide cathode material for thermionic emission.

These line cathodes 2A to 2Y are heated so as to generate a thermionic electron beam by passing an electric current through them, and as will be described later, the electron beams are generated sequentially for a certain period of time starting from the line cathode 2I. controlled to emit. The back electrode 1 suppresses generation of electron beams from line cathodes 2 other than the line cathode 2 that is controlled to emit electron beams for a certain period of time, and directs the generated electron beams only in the forward direction. It has the effect of pushing out. The back electrode 1 may be formed by a coating of electrically conductive material applied to the inner surface of the rear wall of the glass bulb. Further, instead of the back electrode 1 and the linear cathode 2, a planar electron beam emitting cathode may be used.

The vertical focusing electrode 3 is a conductive plate 11 having a horizontally long slit 10 facing each of the line cathodes 2a to 2yo, and directs the electron beam emitted from the line cathode 2 through the slit.
10 and vertically focused.

Electron beams for one horizontal line (360 pixels) are taken out at the same time.

In the figure, only one section in the horizontal direction is shown. The slits 10 may be provided with slits at appropriate intervals in the middle, or may be substantially a row of through holes arranged horizontally at small intervals (nearly touching each other). It may also be configured as a slit. The vertical focusing electrode 3' is also similar.

A plurality of vertical deflection electrodes 4 are arranged horizontally in the middle of each of the slits 10, and are each composed of conductors 13 and 13' provided on the upper and lower surfaces of the insulating substrate 12. has been done. Then, a vertical deflection voltage is applied between the opposing conductors 13 and 13',
Deflect the electron beam vertically. In this embodiment, the electron beam from one line cathode 2 is vertically deflected to a position corresponding to 16 lines by a pair of conductors 13, 13'.

The 16 vertical deflection electrodes 4 constitute 15 pairs of conductors corresponding to each of the 15 line cathodes 2, and in the end, the electron beams are emitted so as to draw 240 horizontal lines on the screen plate 9. deflect.

Next, the control electrodes 5 are composed of conductive plates 15 each having a vertically long slit 14, and a plurality of control electrodes 15 are arranged in parallel in the horizontal direction at predetermined intervals. In this embodiment, 180 conductive plates 15a to 15n for control electrodes are provided (only nine are shown in the figure). Each of the control electrodes 5 extracts the electron beam horizontally by dividing it into two picture elements each, and controls the amount of electron beam passing therethrough according to the video signal for displaying each picture element.

Therefore, the conductive plates 15a to 15n for the control electrode 5 are
If 0 lines are provided, 360 picture elements can be displayed per horizontal line. In order to display the image in color, each picture element is displayed with phosphors of three colors, R, G, and H, and each control electrode 5 has two picture elements of R, G, and B. Each video and image signal is added sequentially.

To each of the 180 conductive plates 15a to 15n for the control electrodes 5, 180 pairs of video signals (2 pixels per river) for one line are simultaneously applied, and the video for one line is simultaneously applied. Is displayed.

The horizontal focusing electrode 6 is composed of a conductive plate 17 having a plurality of vertically long slits 16 (180 slits 16) facing the control electrode 5 (s') y) 14, and each picture divided in the horizontal direction. Each elemental electron beam is focused horizontally into a narrow electron beam.

A plurality of horizontal deflection electrodes 7 are electrically conductive plates 18 arranged vertically on both sides of the slit 16,
18', each electrode 18, 18
A six-step horizontal deflection voltage is applied to the screen 9 to deflect the electron beam of each picture element in the horizontal direction.
Above, the two sets of R, G', and B phosphors are sequentially irradiated to emit light.

In this example, the deflection range is two picture elements wide for each electron beam.

The acceleration electrode 8 is composed of a plurality of conductive plates 19 provided horizontally at the same position as the vertical deflection electrode 4.
The electron beam is accelerated so as to collide with the screen 9 with sufficient energy.

The screen 9 is constructed by applying a phosphor 20 that emits light when irradiated with an electron beam to the back surface of a glass plate 21, and adding a metal back layer (not shown).

The phosphors 20 are provided with two pairs of phosphors of three colors, R2G and B, for each slit 14 of the control electrode 5, that is, for each horizontally divided electron beam. It is applied in vertical stripes.

In FIG. 1, the broken lines drawn on the screen 9 indicate divisions in the vertical direction that are displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines correspond to each of the plurality of control electrodes 5. Indicates the horizontal division displayed. As shown in the enlarged view in Fig. 2, one section partitioned by these two has two R', G, and B phosphors for two pixels in the horizontal direction.
0, and has a width of 16 lines in the vertical direction. The size of one compartment is, for example, 1 block in the horizontal direction,
The vertical direction is 10 bamboos.

Please note that in FIG. 1, the horizontal length is greatly expanded relative to the vertical direction for clarity.

In this example, for one control electrode 5, that is, for one electron beam, the R, G, and H phosphors 20 are 1/2 picture elements.
Only pairs are provided, but of course one picture element or three
More than one picture element may be provided, and in that case, the control electrode 5
R, G, and B video signals for one picture element or three or more picture elements are inputted in sequence, and horizontal deflection is performed in synchronization with this.

Next, the basic configuration of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, the driving portion that irradiates the screen 9 with an electron beam to emit raster light will be explained.

The power supply circuit 22 is a circuit for applying a predetermined Gia Sumi pressure (operating voltage) to each electrode of the display element, -v1 to the back electrode 1 and v3゜■3 to the vertical focusing electrodes 3, 3'. ′,
A DC voltage of V6 is applied to the horizontal focusing electrode 6, V8° to the accelerating electrode 8, and V9 to the screen 9.

Next, a composite video signal of a television signal is applied to the input terminal 23, and a synchronization separation circuit 24 separates and extracts a vertical synchronization signal (2) and a horizontal synchronization signal (H).

The vertical deflection drive circuit 40 includes a vertical deflection counter 25.
Memory 27 for storing vertical deflection signals. It is constituted by a digital-to-analog converter 39 (hereinafter referred to as a DA converter). As input signals to the vertical deflection drive circuit 40, a vertical synchronizing signal V and a horizontal synchronizing signal H shown in FIG. 4 are used. The vertical deflection counter 25 (8 bits) is reset by the vertical synchronization signal (2) and counts the horizontal synchronization signal H. This vertical deflection counter 25 counts the effective scanning period (here, a period of 240H) excluding the vertical retrace period of the vertical period, and this count output is supplied to the address of the memory 27. memory 27
The vertical deflection signal data (in this case, 8 bits) corresponding to each address is outputted from the DA converter 39 and outputted from the DA converter 39 as shown in FIG.

V' is converted into a vertical deflection signal. In this circuit 240
There is a memory address for storing a vertical deflection signal corresponding to each line of H minutes, and by storing regular data in the memory every 16H minutes, a 16-step vertical deflection signal can be obtained.

On the other hand, the line cathode drive circuit 26 uses the vertical synchronization signal V and the output of the vertical deflection counter 25 to create line cathode drive pulses [I to YO]. FIG. 5(a) shows the vertical synchronizing signal ■, the horizontal synchronizing signal H, and the lower five of the vertical deflection counter 25.
Shows the relationship between bits. Fig. 5(b) shows the linear cathode drive and pulse every 1f3H using these signals.
We will show you how to make one. In FIG. 5, LSB indicates the lowest bit, and (LSB+1) means the bit one higher than the LSB.

The first line cathode drive pulse [A'] can be created using an R-S flip-flop or the like using the vertical synchronization signal V and the output (LSB+4) of the vertical deflection counter 25.
The line cathode drive pulses [A' to 'Y'] are clocked using a shift register, and the inverted version of the output (LSB -1-3) of the vertical deflection counter 25 is used to clock the line cathode drive pulses [A']. It can be obtained by transferring.

This drive pulse [A' to Y'] is inverted and inverted, and is kept at a low potential only during each pulse period, and during other periods, it is approximately 20
It is converted into line cathode drive pulses [I to YO] at a high potential of S and applied to each line cathode 2I to 2Y.

Each line cathode 2I to 2Y is heated by a current flowing through it during the high potential of its driving force [I to YO], and it emits electrons during the low potential period of the driving force [I to YO]. The heated state is maintained so that it can be released. As a result, each of the 15 line cathodes 2A to 2Y receives a low potential drive pulse [I to YO].
Electrons are emitted only during the 16H period when . During the period in which a high potential is applied, the potential applied to the line cathodes 2I to 2Y is lower than the potential at the position of the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the vertical focusing electrode 3. Since the higher potential of the wire is positive, electrons are emitted from the wire cathodes 2-2. Thus,
In the line cathode 2, electrons are sequentially emitted from the upper line cathode 2a toward the lower line cathode 2y every 16H period during the effective vertical scanning period.

The emitted electrons are pushed forward by the back electrode 1, pass through the opposing slits 10 of the vertical focusing electrode 3, and are focused in the vertical direction to form a flat electron beam.

Next, the line cathode drive pulses [I to Y] and the vertical deflection signal v
, v' will be explained using FIG. FIG. 6(a) is a waveform diagram of the line cathode/gurus, FIG. 6(b) is a waveform diagram of the vertical deflection signal, and FIG. 6(c) is a waveform diagram of the horizontal deflection signal. The vertical deflection signals v and v' shown in FIG. 6(b) change in 16 steps by 1H during the 16H period of each line cathode beam (I to Y) of FIG. 6(a). The vertical deflection signals V and V' both have a center voltage of V4, and are expressed so that they change in opposite directions, such that 2 increases sequentially and v/ decreases sequentially. These vertical deflection signals V
and V' are respectively applied to the electrodes 13 and 13' of the vertical deflection electrode 4, and as a result, the electron beams generated from each of the line cathodes 2I to 2Y are vertically deflected in 16 steps, as described above. As shown above, on the screen 9, one electron beam is deflected so as to sequentially draw a raster line of 16 lines one line at a time from the top.

As a result of the above, an electron beam is emitted from each of the 15 line cathodes 2A to 2Y in sequence for a period of 16H, and each electron beam is sequentially emitted from the top to the bottom within 15 sections in the vertical direction. By being deflected line by line, on the screen 9, from the first line at the top to the 24
The electron beam is vertically deflected by one line on each 11th page up to the 0th line, and a raster of 240 lines on the gold side is drawn.

The electron beam thus vertically deflected is horizontally divided into 180 sections by the control electrode 5 and the horizontal focusing electrode 6 and extracted. Figure 1 shows one of these categories. The amount of electron beam passing through each section is controlled by a control electrode 5, and is focused horizontally by a horizontal focusing electrode 6 into a single narrow electron beam 9.
Next, the light is deflected horizontally in six steps by the horizontal deflection means, and is sequentially irradiated onto the R, G, B combined light body 20 corresponding to two picture elements on the screen 9. FIG. 2 shows the vertical and horizontal divisions. Each of control electrodes 5 15a to 1'
The phosphors corresponding to 5n are R, G, and B for two picture elements, but for convenience of explanation, one picture element is R1, Gl + Bl, and the other is R2+G2 r82.

The horizontal deflection drive circuit 41 includes a horizontal deflection counter (11
(bit), a memory 29 storing horizontal deflection signals, and a DA converter 38. The input pulse of the horizontal deflection drive circuit 41 is synchronized with the vertical synchronizing signal V and the horizontal synchronizing signal H, as shown in FIG. 7, and uses a pulse 6H having a repetition frequency six times that of the horizontal synchronizing signal H.

The horizontal deflection counter 28 is reset by the vertical synchronizing signal V and counts 6 times the horizontal angle 6H.

This horizontal deflection counter 28 is used 6 times during IH, 1
During this period, the count is counted 240 H×6/H=1440 times, and this count output is supplied to the address of the memory 29. The memory 29 outputs horizontal deflection signal data (here, 8 pits) according to the address, and the D-A converter 38 converts it into horizontal deflection signals such as h and h' shown in FIG. be done.

This circuit has memory addresses for storing horizontal deflection signals corresponding to each of 6 x 240 lines.
By storing six pieces of regular data for each line in the memory, a six-step wave horizontal deflection signal can be obtained in a 1H period.

This horizontal deflection signal is a pair of horizontal deflection signals h' and h' that change in 6 steps as shown in Figure 7, and both have a center voltage of V7, h decreases sequentially, and 11' These horizontal deflection signals h and h' are respectively applied to electrodes 18 and 18' of the horizontal deflection electrode 7. As a result, each of the horizontally divided The electron beam scans R, G, B, R of the screen 9 during each horizontal period.

c + B(RI I G, , Bl, R21G2
It is horizontally deflected so that the phosphor 182) is sequentially irradiated with V6. As a result, in each line raster, the electron beam is RI + for each of the 180 horizontal sections.
Gl + 13+ +R2, G2. Each phosphor 20 of B2
are irradiated sequentially.

Therefore, the electron beam is R1+ for each horizontal section of each line.
A color television image can be displayed on the screen 9 by modulating it with the video signals of G 1+ B 1 and R2+ G 2 r B 2 .

Next, the modulation control portion of the electron beam will be explained.

First, the composite video signal applied to the television signal input terminal 23 is applied to the color demodulation circuit 30, where the R-Y
and B-Y color difference signals are demodulated, the G-Y color difference signals are matrix-synthesized, and further, they are combined with the luminance signal Y to generate R, G, and B primary color signals (hereinafter R, G, and B). (referred to as a video signal) is output. These R, G, and B video signals are transmitted to 180 sample hold circuit sets 31a to 31.
added to n. Each Zansol hold circuit group 31a to 3
1n is for R1 + Gl + BI + R2, G
For 2.

It has six sample and hold circuits for B2.

These sample and hold outputs are respectively applied to holding memory sets 32a-32Tl.

On the other hand, the reference clock oscillator 33 is composed of a PLL (phase-locked Drousot) circuit, etc., and in this example generates a base clock 6fsc that is six times as large as the color subcarrier fsc and a reference clock 2f8c that is twice as large as the color subcarrier fsc. . The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H.

The reference clock 2fso is added to the deflection/gurus generation circuit 42 to obtain a signal 6H which is six times the horizontal synchronizing signal H and signal switching pulses r1, gl, bl, r2, g2, b2 for each R. . On the other hand, the reference clock 6 fsc is applied to the sampling pulse generation circuit 34, where it is delayed by one clock period by a shift register, etc., so that the effective horizontal scanning period (approximately 50 ttsec) of the horizontal period (63,5μ5ec) ), 1080 sampling pulses Ra1 to Bn2i:I1 are generated, and one transfer pulse t is generated thereafter. When one line of the image to be displayed is divided into 360 picture elements in the horizontal direction, the position corresponds to each picture element, and its position is determined by the horizontal synchronization signal H.
is controlled so that it is always constant.

These 1080 sampling pulses Ra1 to Bn2 are connected to 180 sample hold circuit sets 31a.
~31n, and each sample and hold circuit group 31a~31nK has 180 pixels per line.
R1 and GI for each two picture elements when divided into
+ Bl + R2 + G2 + B2 each video signal is individually sampled and held. The sample held 180 pairs of R1 + GI + Bl +
Each video signal of R2+G2+'B2 is stored in the memory 32a of 18011i after the completion of sample hold for l life.
It is transferred one time by a 32nK transfer pulse t, and is held here for the next one horizontal period. This retained B+
+GI+B++R2+G2+B2 signals are applied to switching circuits 35a to 35n.

Each of the switching circuits 35a to 35n is R
, + Gl + Bl , R2+G2. It is composed of a tri-state or analog gate having individual input terminals of B2 and a common output terminal that sequentially switches and outputs them.

The L power of each switching circuit 35a-35n is applied to 180 pairs of pulse width modulation (PWM) circuits 37a-37n, where the sampled and held R1 +GI
, B, 1R21G21B2 Depending on the size of the video signal, the reference signal becomes /? The pulse width is modulated and output. The repetition period of the reference signal is as follows:
It is desirable that the pulse width be sufficiently smaller than the pulse width of b2, and for example, a pulse width of about 1.10 to 1100 is used.

The outputs of the Norse width modulation circuits 37a to 37n are individually applied to the 180 conductive plates 15a to 15n of the control electrode 5 of the display element as control signals for modulating the electron beam. Each of the switching circuits 35a to 35n receives switching pulses r, + gl + J + r2 + g2 applied from the switching pulse generating circuit 36.
” 2.The switching pulse generation circuit 36 is simultaneously controlled by the above-mentioned deflection/P pulse generation circuit 4.
Signal switching from 2・Grus r+ + g1+ b1+
It is controlled by r2' + g2 + b2, and each horizontal period is divided into six, and each switching circuit 358 is connected to V6.
~ Switch 35n, B+ + C+ + 13+ +
R2+G2. The switching signals r1'gI, b1+r2+g2+ are used to time-divide and sequentially output each video signal of B2 and supply it to the pulse width modulation circuits 37a to 37n.
Generate b2.

What should be noted here is that the switching circuits 35a to 3
R4 + G1.5n. Bl + R2, G2
, B2 video signal supply switching and the electron beam R1+ (z+ + Bi +
The irradiation switching horizontal deflection of R2+G2+B2 to the phosphor is synchronously controlled so that they completely match both in timing and order. As a result, when the R1 phosphor is irradiated with the electron beam, the irradiation amount of the electron beam is controlled by the R1 video signal, and Gl+Bl+R2+G2+B2 is similarly controlled, so that the B+ of each picture element , GI y
Since the light emission of each party light B1, R2+G2+B2 is controlled by the video signal of R1+GI IBI 1R21GJ, 1B2 of the picture element, each picture element is displayed by emitting light according to the input video signal.

Such control is performed simultaneously for 180 sets of 1 line (2 picture elements each) to display an image of 360 picture elements for 1 line, and then sequentially for 240 minutes of lines starting from the upper line. One image will be displayed.

The above operations are performed on one input television signal.
This is repeated for each field, and as a result, a moving television image is displayed on the screen 9 in the same way as a normal television receiver.

By the way, in the above description of the image display device, the reference clock 6fsc generated by the reference clock oscillator 33 is applied to the sampling pulse generation circuit 34, and 1080 sampling pulses Ra1 to Ra1 are generated during the effective horizontal scanning period.
However, as shown in FIG. 8, in the concrete circuit, the reference clock 6fsC is first distributed to the three clocks R, G, and H of the color demodulation circuit 30 in the sampling clock generator 341 in order to avoid complicated wiring. Three sampling clocks corresponding to the output of CKR, CKG,
Divided into CKB. At this time, the sampling clocks CKR, CKG, and CKB have a phase difference of 1200 with each other. The sampling/gurus generation circuit 34 is
The above sampling clocks CKR, CKG, CKB
Three shift registers 342, 3 corresponding to each of
43°344, and the start signal St generated at the start of the effective horizontal scanning period is transferred to the three shift registers 3.
/12, 343, and 344, and three corresponding sampling clocks CKR, CKG, and CKB to generate 360 sampling clocks per shift register by delaying the sampling clock by one period. That is, the shift register 342 to which CKR is applied as a clock receives the sampling pulse R.
al, Ra2, Rbl, Rb2・−.

The shift register 343, which generates R"l + Rn2 and is supplied with the clock CKG, receives the sampling pulse G.
al+ Ga2+ Gbl+ Gb2 ・Gnl +
Generates Gr+2.

Shift register 344 to which clock CKB is applied
The same applies to

Now, as a means for distributing the reference clock 6fsc into three sampling clocks CKR, CKG, and CKB, for example, a method using a ring counter can be considered, but in this method, the reference clock 6fsc is divided into three sampling clocks CKR, CKG, and CKB.
If the relationship that 8c exists in integer multiples of 3 does not hold, a phenomenon such as a clock that should be allocated to CKR may be allocated to CKG may occur. That is, the phase relationship between the sampling clock and the horizontal synchronization signal H is no longer compensated. This applies to black-and-white video signals that do not contain burst signals, or signals such as video recorder outputs that contain burst signals but do not compensate for the phase of horizontal synchronization signal H and color subcarrier fBc. Similarly, the phase relationship between the sampling clock and horizontal synchronization signal H is not compensated.

Below, the phase of the sampling clock is the horizontal synchronization signal H
We will discuss the deterioration in image quality caused by changes in the image quality. The video information included in the video signal has its phase relationship compensated with respect to the horizontal synchronization signal H, and the color subcarrier f
There is no direct relationship to the phase of sc. By the way, the above-mentioned image display device uses 1080 sampling signals Ral~ which have a certain phase relationship with respect to the color subcarrier fsc.
Bn2 sequentially samples the video signal during one effective horizontal scanning period. The 1080 pieces of video information subjected to ZANF0 ring are held in the sample and hold circuit sets 31a to 31n, and are stored in the memory sets 32a to 32. transferred to n,
During the next horizontal period, the pulse width is modulated and applied to the control electrode 5 to control the electron beam on the screen 9.
A phosphor 20 is caused to emit light at the top, and an image is displayed with rapid changes in brightness. At this time, the positions of the phosphors are fixed on the screen 9, and the image information added to each phosphor is given by the sampling signals l'La1 to Bn2. On a screen with a light body, video information sampled by a certain sampling pulse during each horizontal scanning period is arranged vertically on the screen. In this way, there is a one-to-one correspondence between each sampling pulse and the horizontal position on the screen, so
When the phase of the sampling clock changes with respect to the phase of the horizontal synchronization signal H, the image often fluctuates (knocks) in the horizontal direction. Since the sampling clock for each color is 2f8c, for example, in a 10-inch image display device, a knock of 500 μm occurs, resulting in deterioration of image quality.

(Object of the Invention) The present invention provides an image display having the feature that the position of each pixel is determined by the phase of the sampling clock as described above, that is, there is a one-to-one correspondence between each sampling pulse and the horizontal position of each pixel. The present invention provides a synchronous clock generation circuit that makes it possible to prevent horizontal fluctuations (knocks) in an image in an apparatus.

(Structure of the Invention) In order to achieve the above object, the present invention provides a clock generation circuit for sampling a video signal, which has the same frequency as the sampling frequency, and whose phase at each 360° is -T- (N is By having means for generating N clocks that are different by (a natural number), and means for selecting a clock having a constant phase relationship within a range of 360°N with respect to the horizontal synchronization signal from among the N clocks. , a synchronous clock generation circuit that can generate a sampling clock that maintains a constant phase with respect to a horizontal synchronous signal is constructed, thereby making it possible to obtain an image with less jitter.

(Description of Embodiment) An embodiment of the present invention will be described below with reference to FIG. 9. In this example, the sampling frequency is 2 fsc
(7.14 MHz), 1) Using the LL circuit 50, a clock signal with a frequency three times the sampling frequency,
(6f8o) is generated. Next, using a frequency divider 51, the frequency is the same as the sampling frequency, and the phase is 60°.
Six different clocks ψ.

~ ψ5 is generated. Further, the sampling clock switching circuits 52a to 52'c perform the above six clocks every scanning line period.
Sampling clock switching circuits 52a and 52b select three pulses having a constant phase with respect to the horizontal synchronizing signal H and having phases different from each other by 120 degrees from among the clocks ψ0 to ψ5.

Information on which one of the six clock signals ψ0 to ψ5 is to be selected by the clock signal 52c is generated by the horizontal synchronizing signal H and the sampling clock switching pulse generation circuit 53.

FIG. 10 shows three sampling clocks CKR using a reference clock generated by a PLL circuit.

This shows a specific example of how to obtain cKG and CKB. In the same figure, 54 is a T flip-flop Fl
, F2 and a Nant gate G1, which divides the reference clock 6f8c by 1/3 to generate a clock φ having a frequency of 2f8c.

55 is a shift reno star composed of D flip 70 knobs F3 to F8, which shifts the phase of the clock φ by 60 degrees.
Frequency 2fsc whose phase is different by 60' by delaying each other
A waveform shaping circuit 56 that outputs six clocks, and these six clocks are composed of ANDG2 to G7.
Therefore, the square wave ψ of various duties of 50 shown in FIG.
. The waveform is shaped to ~ψ5.

The above clocks ψ0 to ψ5 are connected to six D flip-flops f
This becomes the data input of the latch circuit 58 composed of F9 to F14, and is latched at the edge of the horizontal synchronizing signal H. No matter what timing they are latched, of the six outputs ξ0 to ξ5 of the latch circuit 58, three outputs are at the "H" level and the other three are at the 'L' level, and their state is determined by the horizontal synchronizing signal H. What timing τ is the edge relative to clocks ψ0 to ψ5? This state is maintained for one horizontal scanning period depending on whether the input is made at ~τ5. FIG. 11 shows, as an example, a timing chart when the horizontal synchronizing signal H is input at timing τ3; in this case, ξ. ,ξ4. ξ5
is °゛H″H″ level (output ξ0 of latch circuit 58 ~
Note that ξ5 is taken from the current output of each D flip-flop fF9 to F]4).

Output ξ of latch circuit 58. ~ξ5-key Nando Kate G8
~G]3 is decoded by the decoder 59. In this circuit example, the horizontal synchronizing signal H is τ0
If input at timing τ, ζ0, if input at τ, ζ1, if input at τ2, ζ2, if input at τ3, ζ3, if input at τ4, ζ4,
5, ζ5 is decoded so that it reaches the °'L" level, and the others are decoded so that it becomes the "°H" level.Furthermore, the gate G1.3 is decoded so that the clock ψ is inputted in the latch circuit 58. .

It also functions as a protection circuit to prevent malfunctions when a change in ψ5 and an input of the horizontal synchronizing signal H occur simultaneously. 11th
When the horizontal synchronizing signal H is input at the timing shown in the figure, only ζ3 is at “L” level, and the others are at “H” level.
level.

Three sets of sampling clock switching circuits 57a, 57b, 57'c consisting of G]4 to G34 switch clocks ψ corresponding to the outputs ζ0 to ζ5 of the decoder 57, respectively.
Select one from 0 to ψ5 and output.

When the horizontal synchronizing signal H is input at the timing shown in FIG. 11, among the decoder outputs ζ0-ζ5, ζ3
Only the outputs CKR of the sampling clock switching circuits 57a, 57b, and 57c are at the "L" level.
CKG and CKB are clocks ψ3゜ψ5. ψ
It becomes 1. Of course, the phase relationship between the horizontal synchronizing signal H and the sampling clocks C'KR, CKG, and CKB can be arbitrarily determined by the decoding method.

The sampling link noculus CKR, CKG, CKB once selected as above is valid for one horizontal scanning period, and the clock ψ is activated by the input horizontal synchronizing signal in the next horizontal scanning period. Since the operation of selecting a new clock that has a certain relationship with the horizontal synchronizing signal H from ~ψ5 is repeated, it is possible to always select a clock that has a certain phase with respect to the horizontal synchronizing signal. .

(Effects of the Invention) As explained above, the present invention provides the following advantages: - Coust signal and PL
3n times the sampling clock (n-
An oscillator is created to generate pulses to create a sampling clock, and a latch circuit, a decoder circuit, etc. are used to generate 6n oscillators that have the same frequency as the sampling clock but differ in phase by 36 G'. Create a clock, select a clock having a constant phase with respect to the horizontal synchronization signal from among the 6n clocks for each -0 scanning line period,
120° and 24° relative to the selected clock
The clocks with different phases of 0° are also selected at the same time, and the video signal is sampled using the above three clocks with different phases of 120° each. The video information whose relationship has been compensated for and the sampling clock are kept at a constant phase, making it possible to obtain an image with less knocking.

[Brief explanation of the drawing]

Fig. 1 is an exploded perspective view showing an example of an image display element used in an image display device to which the present invention is applied, Fig. 2 is an enlarged direction of the fluorescent surface of the image display element, and Fig. 3 is the image display. FIG. 4 is a block diagram of a drive circuit devised prior to the present invention to drive an element. 5, 6, and 7 are waveform diagrams of various parts of the drive circuit, respectively, to explain the operation of the same drive circuit, and FIG. 8 is a block diagram showing a specific example of the Sunsoling Noculus generation circuit in FIG. 3. 9 is a block diagram of a synchronous clock generation circuit according to an embodiment of the present invention, FIG. 10 is a circuit diagram showing the configuration of the main part of the circuit, and FIG. 11 is a block diagram for explaining the operation of the circuit. FIG. 2.2 I~2 Y line cathode, 4... Vertical deflection electrode, 5... Beam flow control electrode, 7... Horizontal deflection electrode, 9... Screen, ]G0 slit, 20... Fluorescent material , 23・Input terminal, 24・Synchronization separation circuit, 25・Vertical deflection counter, 26・Line cathode drive circuit, 27・Memory, 28
・・・Horizontal deflection counter, 29・Memory, 30...
Color demodulation circuit, 31a to 31n/sample hold circuit,
32a-32n...Memory, 33-Reference clock oscillator, 34...Sampling and pulse generation circuit, 35a
〜35n・Switching circuit, 36・・Switching/response generation circuit, 37・・・37n −PWM circuit, 38− D/A converter, 39・・D/A converter, 40・・Vertical deflection drive Circuit, 41...Horizontal deflection, drive circuit, 42...Deflection/relance generation circuit, 50-P
LL circuit, 51/frequency divider, 52a. 52b, 52c... sampling clock switching circuit,
53...-Sampling clock switching/9 pulse generation circuit, 54-1/3 frequency divider, 55...-Shift reno star, 5
6-AND gate, 57a, 57b, 5
7 c'=Suncilling clock switching circuit, 58...
Latch circuit, 59...decoder, Fl, F2...T flip-flop, G1...NAND gate, F3~F1
4 ・D frill rough 0 flop, 62~G7...AND dirt, 68~G] 3 ・NAND gate, G1
4 ~ G 3 ] -OR key-), G 32 ~ G 3
4-AND Kes-1・, G 35-・Inverter. Figure 4 Figure 5 (a) (b) B1 7th Figure m-'' Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] A screen on a screen is vertically divided into a plurality of sections, and an electron beam is generated for each vertical section, and the electron beam is sequentially deflected in the vertical direction for each of the vertical sections. The screen is divided horizontally into multiple sections, and phosphors of multiple colors such as red, green, and blue are arranged horizontally in each horizontal section. The electron beam is divided into the horizontal sections, each of which is deflected in a plurality of steps for a fixed period of time in the horizontal direction by a step-wave horizontal deflection voltage for each horizontal section. Colored phosphors are irradiated once to emit light, and video signals for each of the horizontal sections are sampled and held from the received color television signal, and the horizontal of the electron beam is sampled for each of the horizontal sections. In synchronization with the irradiation of the phosphors of the plurality of colors by deflection, the electron beams for each horizontal section are sequentially morph-width modulated for each color using the held video signal, so that the electron beams are This is a synchronous clock generation circuit used in a clock generation circuit for sampling the video signal in an image display device so as to irradiate it onto a screen, and has the same frequency as the sampling frequency, and each phase is 360' ( (N is a natural number), and from among the N clocks, N clocks having a constant phase relationship within a range of □ with respect to the horizontal synchronization signal 360° are provided. What is claimed is: 1. A synchronous clock generation circuit, comprising: means for selecting a synchronous clock, thereby generating a sampling clock that maintains a constant phase with respect to a horizontal synchronous signal.