JPS60153224A - Counter - Google Patents

Abstract

PURPOSE:To shorten delay up to the stop of a counter by cascading plural blocks for executing counter operation and supplying a pause signal to two blocks or more in parallel. CONSTITUTION:The counter blocks 11 are cascaded with a counter block 12 having a pause signal input enabling terminal 10. Exclusive OR between a data signal from an input 1 and an output 3 of a shift register 9 is found out by an exclusive OR7 and outputted as a counter output 3. If a pause signal ''0'' is inputted, a signal through gates 4, 5 is turned to ''0'', the output of a NOR circuit 8 is made the same value as the output 3 of the SR9 by a feedback signal from the output terminal 3, so that the output of the SR9 is made the same as the outputs of the pre-SR and post SR. A pause signal of the succeeding stage or after is inputted through the pre-stage gates 4, 5, but the pause signal inputted at the initial stage is inputted directly from the terminal 10 to the block 12 in parallel to stop the counter, so that the delay time of the pause signal is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a counter that stops counting in response to a PAUSE signal.

[Technical background of the invention and its problems]

A conventional example of this type of counter is shown in FIG.

That is, conventionally, two or more blocks 11 are connected in series to construct a counter with a number of bits corresponding to the number of connections. In the figure, 1 is the input part for the data signal and pause (stops the counter) signal, 2 is the initial load input, 3 is the counter output, 4 is the NAND circuit, 5 is the inverter, 6 is the NOR circuit, and 7 is the clock drive. 8 is a clocked NOR circuit, 9 is a shift register (1 bit), and 1' is an output.

In block 11 in FIG. 1, data is input from input section 1 and enters NOR circuit 6, and from this NOR circuit 6 becomes one input of clocked NOR circuit 8. On the other hand, data is input from the input section 1, enters the NAND circuit 4, and is transferred to the inverter 5.
becomes the other input of the clocked NOR circuit 8. The signal enters the shift register 9 from this circuit 8, becomes data, and is output from the output section 3. The data fed back from the output section 3 and the data input from the input 1 are subjected to an exclusive OR operation and are input to the shift register 9, where they become the next data. Also, when a pause signal is input to the human power 1, this pause signal stops the counter of its own block from the gate 8 as per dirt 4.5'ft, and
This signal enters input 1 of the next stage block and becomes a counter stop signal for the next stage.

In the above configuration, more pause signals than input 1 of the first stage block are input, and the next stage input I
Since a large K input is input, a delay occurs in the pause signal at the next stage due to the capacity of the dart 4.5 compared to the pause signal at the first stage. In addition, since the counter is configured with a cascade connection of blocks 1 and 1, as the number of bits increases, the pause signal is input through the gate 4.5 of each block, which has the disadvantage that the delay increases as it goes to the later stage. Ta.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to shorten the delay of the pause signal input to each block of the counter, and to shorten the delay until the counter stops due to the pause signal.

[Summary of the invention]

In the present invention, a plurality of blocks that receive a data signal and perform a counter operation are connected in cascade, and a pause signal is supplied to two or more of the blocks in parallel to stop the blocks.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Second
The figure shows the blocks used in the same example.
Since it almost corresponds to that in the figure, corresponding parts will be given the same reference numerals and explanations will be omitted. The difference between FIG. 1 and FIG. 2 is that a terminal 10 to which a pause signal can be input is added to the NAND circuit 4, and the NAND circuit 4 is powered by three people.

FIG. 3 shows the above embodiment, in which the seven blocks of FIG. 1 and the block 12 of FIG. 2 are all cascade-connected to form an 8-bit block counter.

This configuration normally performs an exclusive OR with the data signal input to the human input 1 and the output 3 of the shift register 9.
Assuming that the counter output is 3, when the pause signal "0" is input to the input 1, the signal passing through the dart 4.5 is "0#", and the output of the NOR circuit 8 is the output from the output terminal 3. The feed signal and the input signal have the same value as the output 3 of the shift register 9. Therefore, the output of the shift register 9 is the same as the previous shift register output.

Pause signals from the next stage onwards are inputted through gates 4 and 5 at the previous stage, but in addition to this, the pause signal input at the first stage is directly inputted in parallel from terminal 10 to block 12 to stop the counter. It is something.

According to the above embodiment, when a pause signal is input to the counter, the blocks 12 at the next stage and thereafter are sent to the dart 4 at the previous stage,
Since the pause signal is input directly to terminal 1θ without passing through 5, the number of front-stage darts through which the pause signal in the latter stage passes is reduced.
The delay time of the pause signal for stopping the counter is shortened.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, block 12 may be used instead of block 11 in FIG.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a power counter that can shorten the delay time until the count is stopped by a pause signal.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of blocks that constitute a conventional counter.
FIG. 2 is a circuit diagram of blocks constituting a counter used in one embodiment of the present invention, and FIG. 3 is an overall configuration diagram showing the counter of the same embodiment. 9...Shift register, 10...Pause signal input terminal, 11.12...Block. Applicant's agent Patent attorney Takehiko Suzue Figure 1 11 Figure 2

Claims (1)

[Claims] A counter characterized in that a plurality of blocks that receive a data signal and operate as a counter are connected in cascade, and a pause signal is supplied to two or more of the blocks in parallel to stop the blocks.