JPS60153207A - Differential amplifier circuit - Google Patents
Differential amplifier circuitInfo
- Publication number
- JPS60153207A JPS60153207A JP59009781A JP978184A JPS60153207A JP S60153207 A JPS60153207 A JP S60153207A JP 59009781 A JP59009781 A JP 59009781A JP 978184 A JP978184 A JP 978184A JP S60153207 A JPS60153207 A JP S60153207A
- Authority
- JP
- Japan
- Prior art keywords
- current
- differential amplifier
- circuit
- transistor
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は差動増幅回路に係り、特に、レベルメータ回
路等の計測回路に好適な差動増幅の改善に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential amplification circuit, and particularly to an improvement in differential amplification suitable for a measurement circuit such as a level meter circuit.
第1図はレベルメータ回路に用いられている差動増幅回
路を示している。即ち、差動増幅器2はトランジスタ4
.6.8.10、ダイオード12及び抵抗14.16で
構成され、トランジスタ8で動作電流が設定され、トラ
ンジスタ4のベースには、抵抗18及びダイオード20
.22で一定のバイアスが加えられ、端子24には一定
電圧が加えられる。またス トランジスタ6のベースに
は抵抗16を介して入力端子26が形成され、入力信号
が与えられる。この差動増幅器2において、トランジス
タ10とダイオード12で電流反転回路を構成し、差動
出力はトランジスタ6のコレクタから取出され、出力回
路28に加えられる。FIG. 1 shows a differential amplifier circuit used in a level meter circuit. That is, the differential amplifier 2 is connected to the transistor 4
.. 6.8.10, consists of a diode 12 and a resistor 14.16, the operating current is set by the transistor 8, and the base of the transistor 4 has a resistor 18 and a diode 20.
.. A constant bias is applied at 22 and a constant voltage is applied to terminal 24. Further, an input terminal 26 is formed at the base of the transistor 6 via a resistor 16, and an input signal is applied thereto. In this differential amplifier 2, the transistor 10 and the diode 12 constitute a current inversion circuit, and the differential output is taken out from the collector of the transistor 6 and applied to the output circuit 28.
出力回路28は、トランジスタ30,32.34.36
.38及び抵抗40で構成されている。基準電位点端子
42と電源端子44との間には、電圧Vccの駆動電源
が接続され、出力はトランジスタ36のコレクタに形成
された出力端子46から取出される。The output circuit 28 includes transistors 30, 32, 34, 36
.. 38 and a resistor 40. A driving power source of voltage Vcc is connected between the reference potential point terminal 42 and the power source terminal 44, and the output is taken out from an output terminal 46 formed at the collector of the transistor 36.
このような差動増幅回路において、差動増幅器2を構成
するトランジスタ4.6の特性の不整合等によって入力
が無い場合にも、僅かに電流が流れ、これが出力回路2
8から発生する。In such a differential amplifier circuit, even when there is no input due to a mismatch in the characteristics of the transistors 4 and 6 constituting the differential amplifier 2, a slight current flows, and this flows into the output circuit 2.
Occurs from 8.
例えば、入力端子26に第2図Aに示す交流信号を与え
、出力端子46から半波整流出力を取出す場合、本来無
出力となるべき区間の抵抗40に僅かに電流が流れ、第
2図Bに示すようにその積で与えられる電圧降下VLが
発生する。For example, when applying an AC signal shown in FIG. 2A to the input terminal 26 and taking out a half-wave rectified output from the output terminal 46, a slight current flows through the resistor 40 in a section that should normally have no output, and as shown in FIG. 2B. A voltage drop VL given by the product occurs as shown in FIG.
このような誤出力は、レベルメータ回路等の場合では、
メータに僅かの振れや表示素子の点灯を生しさせること
になり、計測精度を低下させる原因になる。Such erroneous output occurs in the case of level meter circuits, etc.
This causes a slight fluctuation in the meter and lighting of the display element, which causes a decrease in measurement accuracy.
この発明は、不必要な出力を抑制した差動増幅回路の提
供を目的とする。An object of the present invention is to provide a differential amplifier circuit that suppresses unnecessary output.
この発明は、差動増幅器と共通の動作電流が与えられて
電流出力を発生する定電流回路を設置し、この定電流回
路の出力電流で差動増幅器の信号入力側にアイドリング
電流を流すことにより、不必要な出力の発生を防止した
ものである。This invention installs a constant current circuit that generates a current output when given an operating current common to that of a differential amplifier, and uses the output current of this constant current circuit to flow an idling current to the signal input side of the differential amplifier. , which prevents unnecessary output from occurring.
以下、この発明を図面を参照して詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to the drawings.
第3図はこの発明の差動増幅回路の実施例を示し、第1
図の回路と同一部分には同一符号を付しである。FIG. 3 shows an embodiment of the differential amplifier circuit of the present invention.
The same parts as those in the circuit shown in the figure are given the same reference numerals.
この差動増幅回路には、差動増幅器2の入力側にアイド
リング電流を流す定電流回路48が設置されている。こ
の定電流回路48は差動増幅器2と共通の動作電流が与
えられ、所定の定電流をトランジスタ6のベースに加え
る。即ち、この定電流回路48は、トランジスタ50.
52.54.56及び抵抗58で構成され、トランジス
タ52のベースにはトランジスタ8のベースと共通にバ
イアス電流が与えられている。トランジスタ50はトラ
ンジスタ52と直列に接続され、また、トランジスタ5
4.56は、電流反転回路を構成しており、トランジス
タ50のベース電流を反転してトランジスタ6のベース
に加える。 −以上の構成に基づき、その動作を説明す
る。トランジスタ8に流れる電流を■とすると、l・ラ
ンジスタ4.6にはI/2の電流が流れるので、トラン
ジスタ56からトランジスタ6に加えるアイドリング電
流の値は、電流増幅率hFEを考慮し、1/2hFEに
設定されている。この電流を設定するため、トランジス
タ54のエミッタ面積は、トランジスタ56のそれの2
倍に設定する。This differential amplifier circuit is provided with a constant current circuit 48 that supplies an idling current to the input side of the differential amplifier 2. This constant current circuit 48 is supplied with an operating current common to that of the differential amplifier 2, and applies a predetermined constant current to the base of the transistor 6. That is, this constant current circuit 48 includes transistors 50.
52, 54, 56 and a resistor 58, and a bias current is applied to the base of the transistor 52 and the base of the transistor 8 in common. Transistor 50 is connected in series with transistor 52, and transistor 50 is connected in series with transistor 52.
4.56 constitutes a current inversion circuit, which inverts the base current of the transistor 50 and applies it to the base of the transistor 6. - The operation will be explained based on the above configuration. Assuming that the current flowing through the transistor 8 is ■, a current of I/2 flows through the transistor 4.6, so the value of the idling current applied from the transistor 56 to the transistor 6 is 1/2, taking into account the current amplification factor hFE. It is set to 2hFE. To set this current, the emitter area of transistor 54 is twice that of transistor 56.
Set to double.
このようにすれば、トランジスタ6のベースには信号入
力の有無に無関係に一定のアイドリング電流r/2hp
Eが与えられ、トランジスタ6のベースバイアスが深く
なるため、入力端子26に信号が与えられない限り、出
力を生じない。この結果、レベルメータ回路では零点調
整が不要になり、精度の高い計測出力を得ることができ
る。In this way, the base of the transistor 6 has a constant idling current r/2hp regardless of the presence or absence of a signal input.
E is applied, and the base bias of transistor 6 becomes deep, so that no output is produced unless a signal is applied to input terminal 26. As a result, the level meter circuit does not require zero point adjustment, and a highly accurate measurement output can be obtained.
また、このような差動増幅回路を半導体集積回路で構成
する場合、構成トランジスタの整合性を向上させること
ができるので、量産によって電流増幅率hFEが相対的
に変動しても回路動作上同等不都合を生じないものであ
る。Furthermore, when such a differential amplifier circuit is constructed using a semiconductor integrated circuit, it is possible to improve the consistency of the constituent transistors, so even if the current amplification factor hFE changes relatively due to mass production, the same disadvantages in terms of circuit operation can be avoided. It does not cause
以上説明したようにこの発明によれば、無人力時の不必
要な出力発生を効果的に除くことができる。As described above, according to the present invention, unnecessary output generation during unmanned operation can be effectively eliminated.
第1図は従来の差動増幅回路を示す回路図、第2図はそ
の動作波形を示す説明図、第3図はこの発明の差動増幅
回路の実施例を示す回路図である。
2・・・差動増幅器、48・・・定電流回路。FIG. 1 is a circuit diagram showing a conventional differential amplifier circuit, FIG. 2 is an explanatory diagram showing its operating waveforms, and FIG. 3 is a circuit diagram showing an embodiment of the differential amplifier circuit of the present invention. 2... Differential amplifier, 48... Constant current circuit.
Claims (1)
力を発生する定電流回路を設置し、この定電流回路によ
って差動増幅器の信号入力側にアイドリング電流を流す
ことを特徴とする差動増幅回路。 (2)前記アイドリング電流は、差動増幅器に流れる動
作電流の1/2の電流を差動増幅器を構成するトランジ
スタの電流増幅率で除した値に設定したことを特徴とす
る特許請求の範囲第1項に記載の差動増幅回路。[Claims] (11) A constant current circuit that is supplied with an operating current common to the differential amplifier and generates a current output is provided, and an idling current is caused to flow through the signal input side of the differential amplifier by this constant current circuit. A differential amplifier circuit characterized by: (2) The idling current is set to a value obtained by dividing 1/2 of the operating current flowing through the differential amplifier by the current amplification factor of the transistors forming the differential amplifier. A differential amplifier circuit according to claim 1, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59009781A JP2500261B2 (en) | 1984-01-22 | 1984-01-22 | Differential amplifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59009781A JP2500261B2 (en) | 1984-01-22 | 1984-01-22 | Differential amplifier circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60153207A true JPS60153207A (en) | 1985-08-12 |
JP2500261B2 JP2500261B2 (en) | 1996-05-29 |
Family
ID=11729778
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59009781A Expired - Lifetime JP2500261B2 (en) | 1984-01-22 | 1984-01-22 | Differential amplifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2500261B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0193908A (en) * | 1987-10-05 | 1989-04-12 | Rohm Co Ltd | Direct-coupled amplifier |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5261459A (en) * | 1975-11-14 | 1977-05-20 | Shin Shirasuna Electric Corp | Amplifier circuit |
JPS5623323A (en) * | 1979-08-06 | 1981-03-05 | Toshiba Corp | Press forming method of metal plate material |
JPS5760710A (en) * | 1980-09-27 | 1982-04-12 | Pioneer Electronic Corp | Adjusting circuit for input bias of amplifier |
JPS58200610A (en) * | 1982-05-18 | 1983-11-22 | Sony Corp | Buffer circuit |
-
1984
- 1984-01-22 JP JP59009781A patent/JP2500261B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5261459A (en) * | 1975-11-14 | 1977-05-20 | Shin Shirasuna Electric Corp | Amplifier circuit |
JPS5623323A (en) * | 1979-08-06 | 1981-03-05 | Toshiba Corp | Press forming method of metal plate material |
JPS5760710A (en) * | 1980-09-27 | 1982-04-12 | Pioneer Electronic Corp | Adjusting circuit for input bias of amplifier |
JPS58200610A (en) * | 1982-05-18 | 1983-11-22 | Sony Corp | Buffer circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0193908A (en) * | 1987-10-05 | 1989-04-12 | Rohm Co Ltd | Direct-coupled amplifier |
Also Published As
Publication number | Publication date |
---|---|
JP2500261B2 (en) | 1996-05-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |